github.com/ibm2030.IBM2030
1
0
Fork 0
mirror of https://github.com/ibm2030/IBM2030.git synced 2026-01-11 23:52:47 +00:00
Code Issues Releases Wiki Activity

Change for 2-wire interface to panel switches & status lamps via Maxim MAX7318

Browse Source
This commit is contained in:
ibm2030 2015-11-27 16:47:13 +01:00
parent 664a3b711a
commit 1a4b810f7c
4 changed files with 224 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
digilentSP3.ucf
View File

@ -206,11 +206,15 @@ NET "serialTx" LOC="R13";
# expansion connectors # expansion connectors
# #
# B1 # B1
# 1 Gnd
# 2 VU (+5V)
# 3 Vcco (+3.3V)
NET "MAX7219_CLK" LOC="C10"; # B1- 4 NET "MAX7219_CLK" LOC="C10"; # B1- 4
NET "MAX7219_LOAD" LOC="T3"; # B1- 5 NET "MAX7219_LOAD" LOC="T3"; # B1- 5
NET "MAX7219_DIN" LOC="E10"; # B1- 6 NET "MAX7219_DIN" LOC="E10"; # B1- 6
NET "MAX7318_SCL" LOC="N11"; # B1- 7 NET "MAX7318_SCL" LOC="N11"; # B1- 7
NET "MAX7318_SDA" LOC="C11"; # B1- 8 NET "MAX7318_SDA" LOC="C11"; # B1- 8
NET "MAX7318_SDA" PULLUP;
#NET "B1-09" LOC="P10"; # B1- 9 #NET "B1-09" LOC="P10"; # B1- 9
NET "MAX6951_CLK" LOC="D11"; # B1-10 NET "MAX6951_CLK" LOC="D11"; # B1-10
NET "MAX6951_CS0" LOC="R10"; # B1-11 NET "MAX6951_CS0" LOC="R10"; # B1-11

166
ibm2030-switches.vhd
View File

@ -127,9 +127,14 @@ entity switches is
RawSw_Chk_Chk_Restart, RawSw_Chk_Diagnostic, RawSw_Chk_Stop, RawSw_Chk_Disable : in STD_LOGIC; -- Check Control RawSw_Chk_Chk_Restart, RawSw_Chk_Diagnostic, RawSw_Chk_Stop, RawSw_Chk_Disable : in STD_LOGIC; -- Check Control
pb : in std_logic_vector(3 downto 0); -- On-board pushbuttons pb : in std_logic_vector(3 downto 0); -- On-board pushbuttons
sw : in std_logic_vector(7 downto 0); -- On-board slide switches sw : in std_logic_vector(7 downto 0); -- On-board slide switches
-- Scanned switch inputs - MAX7318 connections
SCL : out STD_LOGIC;
SDA : inout STD_LOGIC;
-- Other inputs -- Other inputs
clk : in STD_LOGIC; -- 50MHz clk : in STD_LOGIC; -- 50MHz
status_lamps : in STD_LOGIC_VECTOR(4 downto 0);
-- Conditioned switch outputs: -- Conditioned switch outputs:
SwA,SwB,SwC,SwD,SwF,SwG,SwH,SwJ : out STD_LOGIC_VECTOR(3 downto 0); SwA,SwB,SwC,SwD,SwF,SwG,SwH,SwJ : out STD_LOGIC_VECTOR(3 downto 0);
@ -158,8 +163,9 @@ signal scan : std_logic_vector(3 downto 0) := "0000";
signal counter : std_logic_vector(14 downto 0) := (others=>'0'); signal counter : std_logic_vector(14 downto 0) := (others=>'0');
signal counter1k : std_logic_vector(15 downto 0) := (others=>'0'); signal counter1k : std_logic_vector(15 downto 0) := (others=>'0');
signal timerCounter : std_logic_vector(5 downto 0) := (others=>'0'); signal timerCounter : std_logic_vector(5 downto 0) := (others=>'0');
signal SwE_raw : std_logic_vector(3 downto 0) := "0000"; signal SwE_raw,SwE_combined : std_logic_vector(3 downto 0) := "0000";
signal SwAC : std_logic_vector(3 downto 0) := "0000"; -- Address Compare switch signal UseInner,UseMid,UseOuter : Boolean;
signal SwAC,SwAC_combined : std_logic_vector(3 downto 0) := "0000"; -- Address Compare switch
signal Parity_in : std_logic; signal Parity_in : std_logic;
signal RawSw_PowerOff, RawSw_Interrupt, RawSw_Load, RawSw_SystemReset, RawSw_RoarReset, RawSw_Start, signal RawSw_PowerOff, RawSw_Interrupt, RawSw_Load, RawSw_SystemReset, RawSw_RoarReset, RawSw_Start,
RawSw_SetIC, RawSw_CheckReset, RawSw_Stop, RawSw_IntTmr, RawSw_Store, RawSw_LampTest, RawSw_SetIC, RawSw_CheckReset, RawSw_Stop, RawSw_IntTmr, RawSw_Store, RawSw_LampTest,
@ -170,28 +176,39 @@ signal debouncePowerOff, debounceInterrupt, debounceLoad,
debounceStop, debounceIntTmr, debounceStore, debounceLampTest, debounceDisplay : debounce; debounceStop, debounceIntTmr, debounceStore, debounceLampTest, debounceDisplay : debounce;
signal timerOut : std_logic := '0'; signal timerOut : std_logic := '0';
signal sClock1ms : std_logic := '0'; signal sClock1ms : std_logic := '0';
signal max7318_switches : std_logic_vector(0 to 63);
constant divider : std_logic_vector(14 downto 0) := "100111000100000"; -- 20,000 gives 2.5kHz constant divider : std_logic_vector(14 downto 0) := "100111000100000"; -- 20,000 gives 2.5kHz
constant divider2000 : std_logic_vector(14 downto 0) := "110000110101000"; -- 25,000 gives 2kHz constant divider2000 : std_logic_vector(14 downto 0) := "110000110101000"; -- 25,000 gives 2kHz
constant sample : std_logic_vector(14 downto 0) := "100111000011110"; -- 19,999 constant sample : std_logic_vector(14 downto 0) := "100111000011110"; -- 19,999
constant divider100 : std_logic_vector(4 downto 0) := "11001"; --- 25 converts 2.5kHz to 100Hz for timer constant divider100 : std_logic_vector(4 downto 0) := "11001"; --- 25 converts 2.5kHz to 100Hz for timer
begin begin
max7318 : entity panel_Switches port map (
clk => clk,
SCL => SCL,
SDA => SDA,
LEDs => status_lamps,
Switches => max7318_switches -- If the MAX7318 is not present, this vector should be all zero
);
Parity_in <= EvenParity(Hex_in); Parity_in <= EvenParity(Hex_in);
scan_counter: process(clk) scan_counter: process(clk)
begin begin
if (rising_edge(clk)) then if (rising_edge(clk)) then
if counter=sample then if counter=sample then
if scan="0000" then SwA <= Hex_in; SwAP <= Parity_in; end if; if scan="0000" then SwA <= Hex_in or max7318_switches(12 to 15); SwAP <= Parity_in; end if;
if scan="0001" then SwB <= Hex_in; SwBP <= Parity_in; end if; if scan="0001" then SwB <= Hex_in or max7318_switches(16 to 19); SwBP <= Parity_in; end if;
if scan="0010" then SwC <= Hex_in; SwCP <= Parity_in; end if; if scan="0010" then SwC <= Hex_in or max7318_switches(20 to 23); SwCP <= Parity_in; end if;
if scan="0011" then SwD <= Hex_in; SwDP <= Parity_in; end if; if scan="0011" then SwD <= Hex_in or max7318_switches(24 to 27); SwDP <= Parity_in; end if;
if scan="0100" then SwE_raw <= Hex_in; end if; if scan="0100" then SwE_raw <= Hex_in or max7318_switches(36 to 39); end if;
if scan="0101" then SwF <= Hex_in; SwFP <= Parity_in; end if; if scan="0101" then SwF <= Hex_in or max7318_switches(28 to 31); SwFP <= Parity_in; end if;
if scan="0110" then SwG <= Hex_in; SwGP <= Parity_in; end if; if scan="0110" then SwG <= Hex_in or max7318_switches(40 to 43); SwGP <= Parity_in; end if;
if scan="0111" then SwH <= Hex_in; SwHP <= Parity_in; end if; if scan="0111" then SwH <= Hex_in or max7318_switches(44 to 47); SwHP <= Parity_in; end if;
if scan="1000" then SwJ <= Hex_in; SwJP <= Parity_in; end if; if scan="1000" then SwJ <= Hex_in or max7318_switches(48 to 51); SwJP <= Parity_in; end if;
if scan="1001" then SwAC <= Hex_in; end if; if scan="1001" then SwAC <= Hex_in or max7318_switches(4 to 7); end if;
end if; end if;
if counter=divider then if counter=divider then
counter<=(others=>'0'); counter<=(others=>'0');
@ -201,18 +218,18 @@ scan_counter: process(clk)
scan <= scan + 1; scan <= scan + 1;
end if; end if;
debouncePowerOff <= debouncePowerOff(1 to 3) & rawSw_PowerOff; debouncePowerOff <= debouncePowerOff(1 to 3) & rawSw_PowerOff;
debounceInterrupt <= debounceInterrupt(1 to 3) & rawSw_Interrupt; debounceInterrupt <= debounceInterrupt(1 to 3) & (rawSw_Interrupt or max7318_switches(53));
debounceLoad <= debounceLoad(1 to 3) & rawSw_Load; debounceLoad <= debounceLoad(1 to 3) & (rawSw_Load or max7318_switches(52));
debounceSystemReset <= debounceSystemReset(1 to 3) & rawSw_SystemReset; debounceSystemReset <= debounceSystemReset(1 to 3) & (rawSw_SystemReset or max7318_switches(63));
debounceRoarReset <= debounceRoarReset(1 to 3) & rawSw_RoarReset; debounceRoarReset <= debounceRoarReset(1 to 3) & (rawSw_RoarReset or max7318_switches(61));
debounceStart <= debounceStart(1 to 3) & rawSw_Start; debounceStart <= debounceStart(1 to 3) & (rawSw_Start or max7318_switches(56));
debounceSetIC <= debounceSetIC(1 to 3) & rawSw_SetIC; debounceSetIC <= debounceSetIC(1 to 3) & (rawSw_SetIC or max7318_switches(60));
debounceCheckReset <= debounceCheckReset(1 to 3) & rawSw_CheckReset; debounceCheckReset <= debounceCheckReset(1 to 3) & (rawSw_CheckReset or max7318_switches(58));
debounceStop <= debounceStop(1 to 3) & rawSw_Stop; debounceStop <= debounceStop(1 to 3) & (rawSw_Stop or max7318_switches(55));
debounceIntTmr <= debounceIntTmr(1 to 3) & rawSw_IntTmr; debounceIntTmr <= debounceIntTmr(1 to 3) & (rawSw_IntTmr or max7318_switches(62));
debounceStore <= debounceStore(1 to 3) & rawSw_Store; debounceStore <= debounceStore(1 to 3) & (rawSw_Store or max7318_switches(59));
debounceLampTest <= debounceLampTest(1 to 3) & rawSw_LampTest; debounceLampTest <= debounceLampTest(1 to 3) & (rawSw_LampTest or max7318_switches(57));
debounceDisplay <= debounceDisplay(1 to 3) & rawSw_Display; debounceDisplay <= debounceDisplay(1 to 3) & (rawSw_Display or max7318_switches(54));
if (debouncePowerOff = "0000") then Sw_PowerOff <= '0'; else if (debouncePowerOff = "1111") then Sw_PowerOff <= '1'; end if; end if; if (debouncePowerOff = "0000") then Sw_PowerOff <= '0'; else if (debouncePowerOff = "1111") then Sw_PowerOff <= '1'; end if; end if;
if (debounceInterrupt = "0000") then Sw_Interrupt <= '0'; else if (debounceInterrupt = "1111") then Sw_Interrupt <= '1'; end if; end if; if (debounceInterrupt = "0000") then Sw_Interrupt <= '0'; else if (debounceInterrupt = "1111") then Sw_Interrupt <= '1'; end if; end if;
if (debounceLoad = "0000") then Sw_Load <= '0'; else if (debounceLoad = "1111") then Sw_Load <= '1'; end if; end if; if (debounceLoad = "0000") then Sw_Load <= '0'; else if (debounceLoad = "1111") then Sw_Load <= '1'; end if; end if;
@ -266,67 +283,72 @@ SwAC_scan <= '1' when scan="1001" else '0';
-- Inner ring -- Inner ring
SwE.I_SEL <= '1' when SwE_raw="0000" and SW_E_INNER='1' else '0'; UseInner <= (SW_E_INNER='1' or max7318_switches(34)='1');
SwE.J_SEL <= '1' when SwE_raw="0001" and SW_E_INNER='1' else '0'; UseMid <= SW_E_INNER='0' and max7318_switches(34)='0' and SW_E_OUTER='0' and max7318_switches(35)='0';
SwE.U_SEL <= '1' when SwE_raw="0010" and SW_E_INNER='1' else '0'; UseOuter <= (SW_E_OUTER='1' or max7318_switches(35)='1');
SwE.V_SEL <= '1' when SwE_raw="0011" and SW_E_INNER='1' else '0'; SwE_combined <= SwE_raw or max7318_switches(36 to 39);
SwE.L_SEL <= '1' when SwE_raw="0100" and SW_E_INNER='1' else '0'; SwE.I_SEL <= '1' when SwE_combined="0000" and UseInner else '0';
SwE.T_SEL <= '1' when SwE_raw="0101" and SW_E_INNER='1' else '0'; SwE.J_SEL <= '1' when SwE_combined="0001" and UseInner else '0';
SwE.D_SEL <= '1' when SwE_raw="0110" and SW_E_INNER='1' else '0'; SwE.U_SEL <= '1' when SwE_combined="0010" and UseInner else '0';
SwE.R_SEL <= '1' when SwE_raw="0111" and SW_E_INNER='1' else '0'; SwE.V_SEL <= '1' when SwE_combined="0011" and UseInner else '0';
SwE.S_SEL <= '1' when SwE_raw="1000" and SW_E_INNER='1' else '0'; SwE.L_SEL <= '1' when SwE_combined="0100" and UseInner else '0';
SwE.G_SEL <= '1' when SwE_raw="1001" and SW_E_INNER='1' else '0'; SwE.T_SEL <= '1' when SwE_combined="0101" and UseInner else '0';
SwE.H_SEL <= '1' when SwE_raw="1010" and SW_E_INNER='1' else '0'; SwE.D_SEL <= '1' when SwE_combined="0110" and UseInner else '0';
SwE.FI_SEL <= '1' when SwE_raw="1011" and SW_E_INNER='1' else '0'; SwE.R_SEL <= '1' when SwE_combined="0111" and UseInner else '0';
SwE.FT_SEL <= '1' when SwE_raw="1100" and SW_E_INNER='1' else '0'; SwE.S_SEL <= '1' when SwE_combined="1000" and UseInner else '0';
SwE.G_SEL <= '1' when SwE_combined="1001" and UseInner else '0';
SwE.H_SEL <= '1' when SwE_combined="1010" and UseInner else '0';
SwE.FI_SEL <= '1' when SwE_combined="1011" and UseInner else '0';
SwE.FT_SEL <= '1' when SwE_combined="1100" and UseInner else '0';
-- Mid ring -- Mid ring
SwE.MS_SEL <= '1' when SwE_raw="0000" and SW_E_INNER='0' and SW_E_OUTER='0' else '0'; SwE.MS_SEL <= '1' when SwE_combined="0000" and UseMid else '0';
SwE.LS_SEL <= '1' when SwE_raw="0001" and SW_E_INNER='0' and SW_E_OUTER='0' else '0'; SwE.LS_SEL <= '1' when SwE_combined="0001" and UseMid else '0';
-- Outer ring -- Outer ring
SwE.E_SEL_SW_GS <= '1' when SwE_raw="0000" and SW_E_OUTER='1' else '0'; SwE.E_SEL_SW_GS <= '1' when SwE_combined="0000" and UseOuter else '0';
SwE.E_SEL_SW_GT <= '1' when SwE_raw="0001" and SW_E_OUTER='1' else '0'; SwE.E_SEL_SW_GT <= '1' when SwE_combined="0001" and UseOuter else '0';
SwE.E_SEL_SW_GUV_GCD <= '1' when SwE_raw="0010" and SW_E_OUTER='1' else '0'; SwE.E_SEL_SW_GUV_GCD <= '1' when SwE_combined="0010" and UseOuter else '0';
SwE.E_SEL_SW_HS <= '1' when SwE_raw="0011" and SW_E_OUTER='1' else '0'; SwE.E_SEL_SW_HS <= '1' when SwE_combined="0011" and UseOuter else '0';
SwE.E_SEL_SW_HT <= '1' when SwE_raw="0100" and SW_E_OUTER='1' else '0'; SwE.E_SEL_SW_HT <= '1' when SwE_combined="0100" and UseOuter else '0';
SwE.E_SEL_SW_HUV_HCD <= '1' when SwE_raw="0101" and SW_E_OUTER='1' else '0'; SwE.E_SEL_SW_HUV_HCD <= '1' when SwE_combined="0101" and UseOuter else '0';
SwE.Q_SEL <= '1' when SwE_raw="0110" and SW_E_OUTER='1' else '0'; SwE.Q_SEL <= '1' when SwE_combined="0110" and UseOuter else '0';
SwE.C_SEL <= '1' when SwE_raw="0111" and SW_E_OUTER='1' else '0'; SwE.C_SEL <= '1' when SwE_combined="0111" and UseOuter else '0';
SwE.F_SEL <= '1' when SwE_raw="1000" and SW_E_OUTER='1' else '0'; SwE.F_SEL <= '1' when SwE_combined="1000" and UseOuter else '0';
SwE.TT_SEL <= '1' when SwE_raw="1001" and SW_E_OUTER='1' else '0'; SwE.TT_SEL <= '1' when SwE_combined="1001" and UseOuter else '0';
SwE.TI_SEL <= '1' when SwE_raw="1010" and SW_E_OUTER='1' else '0'; SwE.TI_SEL <= '1' when SwE_combined="1010" and UseOuter else '0';
SwE.JI_SEL <= '1' when SwE_raw="1011" and SW_E_OUTER='1' else '0'; SwE.JI_SEL <= '1' when SwE_combined="1011" and UseOuter else '0';
-- SwE.IJ_SEL <= '1' when (SwE_raw="0000" or SwE_raw="0001") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2 -- SwE.IJ_SEL <= '1' when (SwE_raw="0000" or SwE_raw="0001") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- SwE.UV_SEL <= '1' when (SwE_raw="0010" or SwE_raw="0011") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2 -- SwE.UV_SEL <= '1' when (SwE_raw="0010" or SwE_raw="0011") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- Address Compare -- Address Compare
Sw_ADDR_COMP_PROC <= '1' when SwAC="0000" else '0'; SwAC_combined <= SwAC or max7318_switches(4 to 7);
Sw_SAR_DLYD_STOP <= '1' when SwAC="0001" else '0'; Sw_ADDR_COMP_PROC <= '1' when SwAC_combined="0000" else '0';
Sw_SAR_STOP <= '1' when SwAC="0010" else '0'; Sw_SAR_DLYD_STOP <= '1' when SwAC_combined="0001" else '0';
Sw_SAR_RESTART <= '1' when SwAC="0011" else '0'; Sw_SAR_STOP <= '1' when SwAC_combined="0010" else '0';
Sw_ROAR_RESTT_STOR_BYPASS <= '1' when SwAC="0100" else '0'; Sw_SAR_RESTART <= '1' when SwAC_combined="0011" else '0';
Sw_ROAR_RESTT <= '1' when SwAC="0101" else '0'; Sw_ROAR_RESTT_STOR_BYPASS <= '1' when SwAC_combined="0100" else '0';
Sw_ROAR_RESTT_WITHOUT_RST <= '1' when SwAC="0110" else '0'; Sw_ROAR_RESTT <= '1' when SwAC_combined="0101" else '0';
Sw_EARLY_ROAR_STOP <= '1' when SwAC="0111" else '0'; Sw_ROAR_RESTT_WITHOUT_RST <= '1' when SwAC_combined="0110" else '0';
Sw_ROAR_STOP <= '1' when SwAC="1000" else '0'; Sw_EARLY_ROAR_STOP <= '1' when SwAC_combined="0111" else '0';
Sw_ROAR_SYNC <= '1' when SwAC="1001" else '0'; Sw_ROAR_STOP <= '1' when SwAC_combined="1000" else '0';
Sw_ROAR_SYNC <= '1' when SwAC_combined="1001" else '0';
-- ROS Control -- ROS Control
Sw_Proc_Inh_CF_Stop <= '1' when RawSw_Proc_Inh_CF_Stop='1' else '0'; Sw_Proc_Inh_CF_Stop <= '1' when RawSw_Proc_Inh_CF_Stop='1' or max7318_switches(0)='1' else '0';
Sw_Proc_Proc <= '1' when RawSw_Proc_Inh_CF_Stop='0' and RawSw_Proc_Scan='0' else '0'; Sw_Proc_Proc <= '1' when RawSw_Proc_Inh_CF_Stop='0' and RawSw_Proc_Scan='0' and max7318_switches(0 to 1)="00" else '0';
Sw_Proc_Scan <= '1' when RawSw_Proc_Scan='1' else '0'; Sw_Proc_Scan <= '1' when RawSw_Proc_Scan='1' or max7318_switches(1)='1' else '0';
-- Rate -- Rate
Sw_Rate_Single_Cycle <= '1' when RawSw_Rate_Single_Cycle='1' else '0'; Sw_Rate_Single_Cycle <= '1' when RawSw_Rate_Single_Cycle='1' or max7318_switches(3)='1' else '0';
Sw_Rate_Process <= '1' when RawSw_Rate_Single_Cycle='0' and RawSw_Rate_Instruction_Step='0' else '0'; Sw_Rate_Process <= '1' when RawSw_Rate_Single_Cycle='0' and RawSw_Rate_Instruction_Step='0' and max7318_switches(2 to 3)="00" else '0';
Sw_Rate_Instruction_Step <= '1' when RawSw_Rate_Instruction_Step='1' else '0'; Sw_Rate_Instruction_Step <= '1' when RawSw_Rate_Instruction_Step='1' or max7318_switches(2)='1' else '0';
-- Check Control -- Check Control
Sw_Chk_Chk_Restart <= '1' when RawSw_Chk_Chk_Restart='1' else '0'; Sw_Chk_Chk_Restart <= '1' when RawSw_Chk_Chk_Restart='1' or max7318_switches(11)='1' else '0';
Sw_Chk_Diagnostic <= '1' when RawSw_Chk_Diagnostic='1' else '0'; Sw_Chk_Diagnostic <= '1' when RawSw_Chk_Diagnostic='1' or max7318_switches(8)='1' else '0';
Sw_Chk_Stop <= '1' when RawSw_Chk_Stop='1' else '0'; Sw_Chk_Stop <= '1' when RawSw_Chk_Stop='1' or max7318_switches(10)='1' else '0';
Sw_Chk_Process <= '1' when RawSw_Chk_Chk_Restart='0' and RawSw_Chk_Diagnostic='0' and RawSw_Chk_Stop='0' and RawSw_Chk_Disable='0' else '0'; Sw_Chk_Process <= '1' when RawSw_Chk_Chk_Restart='0' and RawSw_Chk_Diagnostic='0' and RawSw_Chk_Stop='0' and RawSw_Chk_Disable='0' and max7318_switches(8 to 11)="0000"else '0';
Sw_Chk_Disable <= '1' when RawSw_Chk_Disable='1' else '0'; Sw_Chk_Disable <= '1' when RawSw_Chk_Disable='1' or max7318_switches(9)='1' else '0';
-- Unimplemented switches -- Unimplemented switches
RawSw_PowerOff <= '0'; RawSw_PowerOff <= '0';

27
ibm2030.vhd
View File

@ -76,6 +76,9 @@ entity ibm2030 is
-- Video output -- Video output
vga_r,vga_g,vga_b,vga_hs,vga_vs : out std_logic; -- VGA output RGB+Sync vga_r,vga_g,vga_b,vga_hs,vga_vs : out std_logic; -- VGA output RGB+Sync
-- Panel switches input
MAX7318_SCL : out std_logic;
MAX7318_SDA : inout std_logic;
-- Panel lights output -- Panel lights output
MAX7219_CLK,MAX7219_LOAD,MAX7219_DIN : out std_logic; MAX7219_CLK,MAX7219_LOAD,MAX7219_DIN : out std_logic;
-- MAX6951 is charlieplexed LED mux (miniature panel) -- MAX6951 is charlieplexed LED mux (miniature panel)
@ -193,6 +196,8 @@ signal Clock1ms : STD_LOGIC; -- 1kHz clock for single-shots etc.
signal DEBUG : DEBUG_BUS; -- Passed to all modeles to probe signals signal DEBUG : DEBUG_BUS; -- Passed to all modeles to probe signals
signal LED_vector : std_logic_vector(0 to 255); signal LED_vector : std_logic_vector(0 to 255);
signal LED2_vector : std_logic_vector(0 to 4);
signal Switch_vector : std_logic_vector(0 to 63);
begin begin
@ -527,10 +532,19 @@ begin
Sw_ADDR_COMP_PROC => SW_ADDR_COMP_PROC, Sw_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
Sw_SAR_DLYD_STOP => SW_SAR_DLYD_STOP, Sw_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
Sw_SAR_STOP => SW_SAR_STOP, Sw_SAR_STOP => SW_SAR_STOP,
Sw_SAR_RESTART => SW_SAR_RESTART, Sw_SAR_RESTART => SW_SAR_RESTART,
-- MAX7318
SCL => MAX7318_SCL,
SDA => MAX7318_SDA,
-- Clocks etc. -- Clocks etc.
clk => clk, -- 50MHz clock clk => clk, -- 50MHz clock
status_lamps(4) => IND_LOAD,
status_lamps(3) => IND_TEST,
status_lamps(2) => IND_WAIT,
status_lamps(1) => IND_MAN,
status_lamps(0) => IND_SYST,
-- Clock1ms => Clock1ms, -- Clock1ms => Clock1ms,
Timer => N60_CY_TIMER_PULSE -- Output from Switches is actually 50Hz Timer => N60_CY_TIMER_PULSE -- Output from Switches is actually 50Hz
); );
@ -791,8 +805,15 @@ begin
254 => IND_CHK_ALU, 254 => IND_CHK_ALU,
255 => IND_CHK_A_REG, 255 => IND_CHK_A_REG,
others => '0'); others => '0');
LED2_vector <= (
0=>IND_LOAD,
1=>IND_TEST,
2=>IND_WAIT,
3=>IND_MAN,
4=>IND_SYST);
front_panel : entity panel_LEDs front_panel_LEDs : entity panel_LEDs
generic map( generic map(
clock_divider => 2, clock_divider => 2,
number_LEDs => 256 number_LEDs => 256
@ -813,7 +834,7 @@ begin
MAX6951_CS3 => MAX6951_CS3, MAX6951_CS3 => MAX6951_CS3,
MAX6951_DIN => MAX6951_DIN MAX6951_DIN => MAX6951_DIN
); );
DEBUG.Selection <= CONV_INTEGER(unsigned(SW_J)); DEBUG.Selection <= CONV_INTEGER(unsigned(SW_J));
SerialTx <= SO.SerialTx; SerialTx <= SO.SerialTx;

108
panel_Switches.vhd
View File

@ -70,6 +70,7 @@ type SPI_state_type is (idle_h,start_h,start_hl,data_l,data_lh,data_hl,ack_l,ack
signal SPI_state, new_SPI_state : SPI_state_type := idle_h; signal SPI_state, new_SPI_state : SPI_state_type := idle_h;
type MAX7318_state_type is (idle,writing45,writing67,writing2,delay,reading1); type MAX7318_state_type is (idle,writing45,writing67,writing2,delay,reading1);
signal MAX7318_state, new_MAX7318_state : MAX7318_state_type := idle; signal MAX7318_state, new_MAX7318_state : MAX7318_state_type := idle;
signal SPI_error,new_SPI_error : Boolean := false;
signal bit_counter, new_bit_counter : integer range 0 to 8; signal bit_counter, new_bit_counter : integer range 0 to 8;
signal byteCount, new_byteCount : integer range 0 to 4; signal byteCount, new_byteCount : integer range 0 to 4;
signal delayCounter, new_delayCounter : integer range 0 to 50000; signal delayCounter, new_delayCounter : integer range 0 to 50000;
@ -98,6 +99,91 @@ signal switchVector, new_switchVector : switchArrayType := (others=>"00000000");
-- Write 06,07: Write Command=6, Register6, Register7 -- Write 06,07: Write Command=6, Register6, Register7
-- Write 02, Wait 1ms, Read 01: Write Command=2, Register2, Wait, Write Command=1, Read Register1 -- Write 02, Wait 1ms, Read 01: Write Command=2, Register2, Wait, Write Command=1, Read Register1
-- Basic scan allocation is:
-- Scan Switches
-- 0 ROS,RATE,ADDR_COMP
-- 1 CHECK_CTL,A
-- 2 B,C
-- 3 D,E
-- 4 E_O,SwSpare,E_I
-- 5 G,H
-- 6 J,SwPower,SwLeft1
-- 7 SwLeft2
-- Switch bit allocation is:
-- Pos Scan Bit Switch Position
-- 0 0 7 ROSCTL_1 INH CF STOP
-- 1 0 6 ROSCTL_3 ROS SCAN
-- 2 0 5 RATE_1 INSN STEP
-- 3 0 4 RATE_3 SINGLE CYC
-- 4 0 3 ADDR_COMP_3
-- 5 0 2 ADDR_COMP_2
-- 6 0 1 ADDR_COMP_1
-- 7 0 0 ADDR_COMP_0
-- 8 1 7 CHECK_CTL_1 DIAGNOSTIC
-- 9 1 6 CHECK_CTL_2 DISABLE
-- 10 1 5 CHECK_CTL_4 STOP
-- 11 1 4 CHECK_CTL_5 RESTART
-- 12 1 3 A_3
-- 13 1 2 A_2
-- 14 1 1 A_1
-- 15 1 0 A_0
-- 16 2 7 B_3
-- 17 2 6 B_2
-- 18 2 5 B_1
-- 19 2 4 B_0
-- 20 2 3 C_3
-- 21 2 2 C_2
-- 22 2 1 C_1
-- 23 2 0 C_0
-- 24 3 7 D_3
-- 25 3 6 D_2
-- 26 3 5 D_1
-- 27 3 4 D_0
-- 28 3 3 F_3
-- 29 3 2 F_2
-- 30 3 1 F_1
-- 31 3 0 F_0
-- 32 4 7 SPARE_4
-- 33 4 6 SPARE_2
-- 34 4 5 EI_1 Black/Inner
-- 35 4 4 EI_3 Grey/Outer
-- 36 4 3 EO_3 \
-- 37 4 2 EO_2 \ 0
-- 38 4 1 EO_1 \ =
-- 39 4 0 EO_0 \ ?
-- 40 5 7 G_3
-- 41 5 6 G_2
-- 42 5 5 G_1
-- 43 5 4 G_0
-- 44 5 3 H_3
-- 45 5 2 H_2
-- 46 5 1 H_1
-- 47 5 0 H_0
-- 48 6 7 J_3
-- 49 6 6 J_2
-- 50 6 5 J_1
-- 51 6 4 J_0
-- 52 6 3 PWR_4 LOAD
-- 53 6 2 PWR_2 INTERRUPT
-- 54 6 1 PB_20 DISPLAY
-- 55 6 0 PB_18 STOP
-- 56 7 7 PB_16 START
-- 57 7 6 PB_14 LAMP TEST
-- 58 7 5 PB_12 CHECK RESET
-- 59 7 4 PB_10 STORE
-- 60 7 3 PB_8 SET IC
-- 61 7 2 PB_6 ROAR RESET
-- 62 7 1 PB_4 INT TMR
-- 63 7 0 PB_2 SYSTEM RESET
-- LED Driver allocation
-- Bit Output Lamp
-- 4 7 LOAD
-- 3 6 TEST
-- 2 5 WAIT
-- 1 4 MAN
-- 0 3 SYS
begin begin
gen_clk : process (clk) is gen_clk : process (clk) is
@ -128,6 +214,7 @@ max7318 : process (clk_out) is
new_writeByte <= writeByte; new_writeByte <= writeByte;
new_switchBank <= switchBank; new_switchBank <= switchBank;
new_switchVector <= switchVector; new_switchVector <= switchVector;
new_SPI_error <= SPI_error;
case (SPI_state) is case (SPI_state) is
when idle_h => when idle_h =>
@ -137,6 +224,7 @@ max7318 : process (clk_out) is
new_MAX7318_SDA <= '0'; new_MAX7318_SDA <= '0';
new_MAX7318_SCL <= '1'; new_MAX7318_SCL <= '1';
new_SPI_state <= start_hl; new_SPI_state <= start_hl;
new_SPI_error <= false;
when start_hl => when start_hl =>
-- Min 600ns (tSU STA) -- Min 600ns (tSU STA)
new_MAX7318_SDA <= '0'; new_MAX7318_SDA <= '0';
@ -186,15 +274,14 @@ max7318 : process (clk_out) is
if (writeByte(3)='0') then if (writeByte(3)='0') then
if (MAX7318_SDA = '0') then if (MAX7318_SDA = '0') then
-- Ok -- Ok
new_SPI_state <= ack_hl;
else else
-- Error -- Error
new_SPI_state <= ack_hl; new_SPI_error <= true;
end if; end if;
else else
new_MAX7318_SDA <= '0'; new_MAX7318_SDA <= '0';
new_SPI_state <= ack_hl;
end if; end if;
new_SPI_state <= ack_hl;
when ack_hl => when ack_hl =>
-- Min 300ns (tHD DAT) -- Min 300ns (tHD DAT)
new_MAX7318_SCL <= '0'; new_MAX7318_SCL <= '0';
@ -266,7 +353,9 @@ max7318 : process (clk_out) is
end if; end if;
when reading1 => when reading1 =>
if (SPI_state = idle_h) then if (SPI_state = idle_h) then
new_switchVector(to_integer(unsigned(switchBank))) <= dataIn(7 downto 0); if (not SPI_error) then
new_switchVector(to_integer(unsigned(switchBank))) <= dataIn(7 downto 0);
end if;
new_switchBank <= std_logic_vector(unsigned(switchBank) + 1); new_switchBank <= std_logic_vector(unsigned(switchBank) + 1);
new_MAX7318_state <= idle; new_MAX7318_state <= idle;
end if; end if;
@ -280,9 +369,11 @@ max7318 : process (clk_out) is
if (reset='0') then if (reset='0') then
SPI_state <= new_SPI_state; SPI_state <= new_SPI_state;
MAX7318_state <= new_MAX7318_state; MAX7318_state <= new_MAX7318_state;
SPI_error <= new_SPI_error;
else else
SPI_state <= idle_h; SPI_state <= idle_h;
MAX7318_state <= idle; MAX7318_state <= idle;
SPI_error <= false;
end if; end if;
delayCounter <= new_delayCounter; delayCounter <= new_delayCounter;
dataOut <= new_dataOut; dataOut <= new_dataOut;
@ -293,8 +384,13 @@ max7318 : process (clk_out) is
-- Outputs -- Outputs
switches <= switchVector(0) & switchVector(1) & switchVector(2) & switchVector(3) & switchVector(4) & switchVector(5) & switchVector(6) & switchVector(7); switches <= switchVector(0) & switchVector(1) & switchVector(2) & switchVector(3) & switchVector(4) & switchVector(5) & switchVector(6) & switchVector(7);
SCL <= MAX7318_SCL; SCL <= new_MAX7318_SCL;
SDA <= MAX7318_SDA; if (new_MAX7318_SDA = '0') then
-- Simulate Open Collector output - pin is defined in UCF to be PULLUP
SDA <= '0';
else
SDA <= 'Z';
end if;
end if; end if;
end process; end process;