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Add 7-segment display of WX registers
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ibm2030
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129
7seg_LEDs.vhd
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129
7seg_LEDs.vhd
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---------------------------------------------------------------------------
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-- Copyright © 2015 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: 7seg_LEDs.vhd
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-- Creation Date: 19:50:00 30/11/2015
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-- Description:
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-- 360/30 7-segment LED drivers
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-- This drives the 7-segment display on the Digilent S3BOARD
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--
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2015-11-30
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity segment_LEDs is
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Generic (
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Clock_divider : integer := 50000 -- Default for 50MHz clock is 1kHz
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);
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Port ( -- Input vector
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number : in std_logic_vector(15 downto 0) := (others=>'0'); -- 15-13=LHS 3-0=RHS
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dp : in std_logic_vector(3 downto 0) := (others=>'0'); -- 1 for ON
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-- Other inputs
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clk : in STD_LOGIC; -- 50MHz
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-- Driver outputs
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anodes : out std_logic_vector(3 downto 0); -- 3=LHS 0=RHS
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cathodes : out std_logic_vector(7 downto 0) -- 7=dp 6=g 5=f 4=e 3=d 2=c 1=b 0=a
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);
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end segment_LEDS;
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architecture Behavioral of segment_LEDS is
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signal clk_out : std_logic := '0';
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type segmentArrayType is array(0 to 15) of std_logic_vector(6 downto 0);
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signal segments : segmentArrayType := (
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0 => "1000000",
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1 => "1111001",
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2 => "0100100",
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3 => "0110000",
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4 => "0011001",
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5 => "0010010",
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6 => "0000010",
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7 => "1111000",
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8 => "0000000",
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9 => "0010000",
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10 => "0001000",
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11 => "0000011",
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12 => "1000110",
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13 => "0100001",
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14 => "0000110",
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15 => "0001110"
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);
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type digitArrayType is array(0 to 3) of std_logic_vector(3 downto 0);
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signal digits : digitArrayType := (
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0 => "1110",
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1 => "1101",
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2 => "1011",
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3 => "0111"
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);
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signal digit : integer range 0 to 3 := 0;
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begin
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gen_clk : process (clk) is
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variable divider : integer := Clock_divider;
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begin
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if rising_edge(clk) then
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if (divider=0) then
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divider := Clock_divider;
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clk_out <= not clk_out;
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else
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divider := divider - 1;
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end if;
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end if;
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end process;
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scan : process (clk_out) is
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begin
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if rising_edge(clk_out) then
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if (digit=3) then
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digit <= 0;
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else
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digit <= digit + 1;
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end if;
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anodes <= digits(digit);
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cathodes <= not dp(digit) & segments(to_integer(unsigned(number(digit*4+3 downto digit*4))));
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end if;
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end process;
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end behavioral;
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@ -17,7 +17,7 @@
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<files>
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<file xil_pn:name="ibm2030.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
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</file>
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<file xil_pn:name="FMD2030_5-01A-B.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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@ -247,6 +247,10 @@
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<file xil_pn:name="digilentSP3.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="7seg_LEDs.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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</file>
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</files>
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<properties>
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@ -38,20 +38,20 @@ NET "pb<1>" LOC = "M14";
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NET "pb<0>" LOC = "M13";
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# seven segment display - shared segments
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#NET "ssd<7>" LOC = "P16";
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#NET "ssd<6>" LOC = "N16";
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#NET "ssd<5>" LOC = "F13";
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#NET "ssd<4>" LOC = "R16";
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#NET "ssd<3>" LOC = "P15";
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#NET "ssd<2>" LOC = "N15";
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#NET "ssd<1>" LOC = "G13";
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#NET "ssd<0>" LOC = "E14";
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NET "ssd<7>" LOC = "P16";
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NET "ssd<6>" LOC = "N16";
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NET "ssd<5>" LOC = "F13";
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NET "ssd<4>" LOC = "R16";
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NET "ssd<3>" LOC = "P15";
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NET "ssd<2>" LOC = "N15";
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NET "ssd<1>" LOC = "G13";
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NET "ssd<0>" LOC = "E14";
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# seven segment display - anodes
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#NET "ssdan<3>" LOC = "E13";
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#NET "ssdan<2>" LOC = "F14";
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#NET "ssdan<1>" LOC = "G14";
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#NET "ssdan<0>" LOC = "D14";
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NET "ssdan<3>" LOC = "E13";
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NET "ssdan<2>" LOC = "F14";
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NET "ssdan<1>" LOC = "G14";
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NET "ssdan<0>" LOC = "D14";
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# VGA port
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NET "vga_r" LOC = "R12";
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13
ibm2030.vhd
13
ibm2030.vhd
@ -51,8 +51,8 @@ use work.all;
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entity ibm2030 is
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Port ( -- Physical I/O on Digilent S3 Board
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-- Seven-segment displays
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-- ssd : out std_logic_vector(7 downto 0); -- 7-segment segment cathodes (not used)
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-- ssdan : out std_logic_vector(3 downto 0); -- 7-segment digit anodes (not used)
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ssd : out std_logic_vector(7 downto 0); -- 7-segment segment cathodes - active=0, a=bit0, g=bit6, dp=bit7
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ssdan : out std_logic_vector(3 downto 0); -- 7-segment digit anodes - active=0, RHS=bit0
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-- Discrete LEDs
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led : out std_logic_vector(7 downto 0); -- 8 LEDs
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@ -835,6 +835,15 @@ begin
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MAX6951_DIN => MAX6951_DIN
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);
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number_LEDs : entity segment_LEDs
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port map(
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clk => clk,
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number(15 downto 13) => "000",
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number(12 downto 0) => WX_IND(0 to 12),
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anodes => ssdan,
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cathodes => ssd
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);
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DEBUG.Selection <= CONV_INTEGER(unsigned(SW_J));
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SerialTx <= SO.SerialTx;
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