diff --git a/FLL.vhd b/FLL.vhd new file mode 100644 index 0000000..6b06a1e --- /dev/null +++ b/FLL.vhd @@ -0,0 +1,39 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:25:51 06/17/2015 +-- Design Name: +-- Module Name: FLL - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- FLL is a level-triggered SR flip-flop + +entity FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end; + +architecture slt of FLL is +begin +process(S,R) +begin +if (S='1') then -- Set takes priority + Q<='1' after 1ns; +elsif (R='1') then + Q<='0' after 1ns; +end if; +end process; +end slt; + + diff --git a/FLVL.vhd b/FLVL.vhd new file mode 100644 index 0000000..ba60a69 --- /dev/null +++ b/FLVL.vhd @@ -0,0 +1,40 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:35:52 06/17/2015 +-- Design Name: +-- Module Name: FLVL - slt +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity FLVL is port( S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end; + +architecture slt of FLVL is +alias S1 : STD_LOGIC_VECTOR(Q'range) is S; +alias R1 : STD_LOGIC_VECTOR(Q'range) is R; +begin +process (S1,R1) +begin +for i in Q'range loop +if (S1(i)='1') then -- Set takes priority + Q(i)<='1'; +elsif (R1(i)='1') then + Q(i)<='0'; +end if; +end loop; +end process; +end slt; + diff --git a/FMD2030_5-01A-B.vhd b/FMD2030_5-01A-B.vhd index e8c5e19..56d5fc4 100644 --- a/FMD2030_5-01A-B.vhd +++ b/FMD2030_5-01A-B.vhd @@ -173,24 +173,24 @@ BEGIN -- Fig 5-01A -- ROS Indicator register ROSAR_IND_LATCH_Set <= (ANY_MACH_CHK and CHK_OR_DIAG_STOP_SW) or EARLY_ROAR_STOP; -ROSAR_IND_LATCH: FLL port map(ROSAR_IND_LATCH_Set,MACH_START_RST,FL_ROSAR_IND); -- AA3G4,AA3H4 +ROSAR_IND_LATCH: entity FLL port map(ROSAR_IND_LATCH_Set,MACH_START_RST,FL_ROSAR_IND); -- AA3G4,AA3H4 sSET_IND_ROSAR <= (not ALU_CHK or not CHK_OR_DIAG_STOP_SW) and not FL_ROSAR_IND; -- AA3H4 -- sSET_IND_ROSAR <= '1'; -- Debug SET_IND_ROSAR <= sSET_IND_ROSAR; SET_IND <= (T4 and sSET_IND_ROSAR) or MACH_RST_SET_LCH; -- AA3J4 -WINDP: PH port map(W_P,SET_IND,W_IND_P_X); -- AA3J2 +WINDP: entity PH port map(W_P,SET_IND,W_IND_P_X); -- AA3J2 W_IND_P <= W_IND_P_X or TEST_LAMP; -XINDP: PH port map(X_P,SET_IND,X_IND_P_X); -- AA3J3 +XINDP: entity PH port map(X_P,SET_IND,X_IND_P_X); -- AA3J3 X_IND_P <= X_IND_P_X or TEST_LAMP; -WXIND: PHV13 port map(sWX,SET_IND,WX_IND_X); -- AA3J2,AA3J3 +WXIND: entity PHV13 port map(sWX,SET_IND,WX_IND_X); -- AA3J2,AA3J3 WX_IND <= WX_IND_X or (WX_IND'range=>TEST_LAMP); -- SALS parity checking -- ?? I have added a latch (FL) on PA to hold it at T4, as are W_IND_P and X_IND_P -- This keeps WX_CHK valid during T1, T2 and T3 - it is checked during T2 of the following cycle -- Without this, spurious ROS_ADDR checks are generated because PA is not always valid at the next T2 -PA_PH: PH port map(SALS.SALS_PA,T4,PA_LCH); +PA_PH: entity PH port map(SALS.SALS_PA,T4,PA_LCH); WX_CHK <= not(PA_LCH xor W_IND_P_X xor X_IND_P_X); -- AA2J4 ?? Inverted ?? sSAL_PC <= not EvenParity(USE_BASIC_CA_DECODER & SALS.SALS_AK & SALS.SALS_PK & SALS.SALS_CH & SALS.SALS_CL & SALS.SALS_CM & SALS.SALS_CU & SALS.SALS_CA & SALS.SALS_CB & SALS.SALS_CK & SALS.SALS_PA & SALS.SALS_PS) @@ -242,26 +242,26 @@ SET_W2A <= not ANY_PRIORITY_PULSE_PWR or not ALU_CHK_LCH or not CHK_SW_PROC_SW; SET_W2B <= sGT_BU_ROSAR_TO_WX_REG or not NORMAL_ENTRY; -- AA2F2 SET_W2 <= SET_W2A and SET_W2B; -- AA2H5,AA2F2 Wired-AND SET_W_REG <= ((GT_CA_TO_W_REG or GT_CK_TO_W_REG or SET_W2) and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ?? -REG_W: PHV5 port map(W_ASSM(3 to 7),SET_W_REG,sWX(0 to 4)); -- AA2D2 -REG_WP: PH port map(W_ASSM(8),SET_W_REG,W_P); -- AA2D2 +REG_W: entity PHV5 port map(W_ASSM(3 to 7),SET_W_REG,sWX(0 to 4)); -- AA2D2 +REG_WP: entity PH port map(W_ASSM(8),SET_W_REG,W_P); -- AA2D2 -- X_LATCH: SET_X_REG <= (not INH_ROSAR_SET and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ?? -REG_X: PHV8 port map(X_ASSM(0 to 7),SET_X_REG,sWX(5 to 12)); -- AA2D3 -REG_XP: PH port map(X_ASSM(8),SET_X_REG,X_P); -- AA2D3 +REG_X: entity PHV8 port map(X_ASSM(0 to 7),SET_X_REG,sWX(5 to 12)); -- AA2D3 +REG_XP: entity PH port map(X_ASSM(8),SET_X_REG,X_P); -- AA2D3 WX <= sWX; -- Backup ROSAR regs SET_F <= (MPX_SHARE_PULSE and T4) or MACH_RST_4; -- AA3G3 SET_FW <= SET_F; -FWX_LCH: PHV13 port map(sWX,SET_F,FWX); -- AA3H2,AA3H3 -FWP_LCH: PH port map(W_P,SET_F,FW_P); -- AA3H2 -FXP_LCH: PH port map(X_P,SET_F,FX_P); -- AA3H3 +FWX_LCH: entity PHV13 port map(sWX,SET_F,FWX); -- AA3H2,AA3H3 +FWP_LCH: entity PH port map(W_P,SET_F,FW_P); -- AA3H2 +FXP_LCH: entity PH port map(X_P,SET_F,FX_P); -- AA3H3 SET_G <= (SX_CHAIN_PULSE and T4) or MACH_RST_5; -- AA3K2 -GWX_LCH: PHV13 port map(sWX,SET_G,GWX); -- AA2K5,AA2L2 -GWP_LCH: PH port map(W_P,SET_G,GW_P); -- AA2K5 -GXP_LCH: PH port map(X_P,SET_G,GX_P); -- AA2L2 +GWX_LCH: entity PHV13 port map(sWX,SET_G,GWX); -- AA2K5,AA2L2 +GWP_LCH: entity PH port map(W_P,SET_G,GW_P); -- AA2K5 +GXP_LCH: entity PH port map(X_P,SET_G,GX_P); -- AA2L2 -- CROS triggering diff --git a/FMD2030_5-01C-D.vhd b/FMD2030_5-01C-D.vhd index 06025e9..9c508b4 100644 --- a/FMD2030_5-01C-D.vhd +++ b/FMD2030_5-01C-D.vhd @@ -127,39 +127,39 @@ CD_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST); CD_LCH: FLVL port map(CD_LCH_Set,CD_LCH_Reset,sCTRL.CTRL_CD); -- AA2C6 STRAIGHT_LCH_Set <= sCTRL_REG_RST or (SET_CTRL_REG and not SALS_CF(0)); -STRAIGHT_LCH: FLL port map(STRAIGHT_LCH_Set, T1, sCTRL.STRAIGHT); +STRAIGHT_LCH: entity FLL port map(STRAIGHT_LCH_Set, T1, sCTRL.STRAIGHT); CROSSED_LCH_Set <= SET_CTRL_REG and SALS_CF(0); -CROSSED_LCH: FLL port map(CROSSED_LCH_Set, AUX_CTRL_REG_RST, sCTRL.CROSSED); +CROSSED_LCH: entity FLL port map(CROSSED_LCH_Set, AUX_CTRL_REG_RST, sCTRL.CROSSED); CC2_LCH_Set <= SET_CTRL_REG and SALS_CC(2); CC2_LCH_Reset <= T1 or sCTRL_REG_RST; -CC2_LCH: FLL port map(CC2_LCH_Set, CC2_LCH_Reset, sCTRL.CTRL_CC(2)); +CC2_LCH: entity FLL port map(CC2_LCH_Set, CC2_LCH_Reset, sCTRL.CTRL_CC(2)); GTAHI_LCH_Set <= SET_CTRL_REG and SALS_CF(1); GTAHI_LCH_Reset <= T1 or sCTRL_REG_RST; -GTAHI_LCH: FLL port map(GTAHI_LCH_Set, GTAHI_LCH_Reset, sCTRL.GT_A_REG_HI); +GTAHI_LCH: entity FLL port map(GTAHI_LCH_Set, GTAHI_LCH_Reset, sCTRL.GT_A_REG_HI); GTALO_LCH_Set <= SET_CTRL_REG and SALS_CF(2); GTALO_LCH_Reset <= T1 or sCTRL_REG_RST; -GTALO_LCH: FLL port map(GTALO_LCH_Set, GTALO_LCH_Reset, sCTRL.GT_A_REG_LO); +GTALO_LCH: entity FLL port map(GTALO_LCH_Set, GTALO_LCH_Reset, sCTRL.GT_A_REG_LO); COMPCY_LCH_Set <= SET_CTRL_REG and COMPUTE; COMPCY_LCH_Reset <= T1 or sCTRL_REG_RST; -COMPCY_LCH: FLL port map(COMPCY_LCH_Set, COMPCY_LCH_Reset, sCTRL.COMPUTE_CY_LCH); +COMPCY_LCH: entity FLL port map(COMPCY_LCH_Set, COMPCY_LCH_Reset, sCTRL.COMPUTE_CY_LCH); CG0_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(0)); CG_Reset <= T1 or (MACH_RST_SW or ANY_PRIORITY_LCH); -- ?? Required to prevent simultaneous Set & Reset of CG by MANUAL_STORE -CG0: FLL port map(CG0_Set, CG_Reset, sCTRL.CTRL_CG(0)); sCTRL.GT_B_REG_HI <= sCTRL.CTRL_CG(0); +CG0: entity FLL port map(CG0_Set, CG_Reset, sCTRL.CTRL_CG(0)); sCTRL.GT_B_REG_HI <= sCTRL.CTRL_CG(0); CG1_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(1)); -CG1: FLL port map(CG1_Set, CG_Reset, sCTRL.CTRL_CG(1)); sCTRL.GT_B_REG_LO <= sCTRL.CTRL_CG(1); +CG1: entity FLL port map(CG1_Set, CG_Reset, sCTRL.CTRL_CG(1)); sCTRL.GT_B_REG_LO <= sCTRL.CTRL_CG(1); CV_LCH_Set <= SALS_CV and (0 to 1 => SET_CTRL_REG); CV_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST); -CV_LCH: FLVL port map(CV_LCH_Set,CV_LCH_Reset,sCTRL.CTRL_CV); -- AA2D6 +CV_LCH: entity FLVL port map(CV_LCH_Set,CV_LCH_Reset,sCTRL.CTRL_CV); -- AA2D6 CC01_LCH_Set <= SALS_CC(0 to 1) and (0 to 1 => SET_CTRL_REG); CC01_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST); -CC01_LCH: FLVL port map(CC01_LCH_Set,CC01_LCH_Reset,sCTRL.CTRL_CC(0 to 1)); -- AA2D6 +CC01_LCH: entity FLVL port map(CC01_LCH_Set,CC01_LCH_Reset,sCTRL.CTRL_CC(0 to 1)); -- AA2D6 CS_LCH_Set <= SALS_CS and (0 to 3 => SET_CTRL_REG); CS_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST); -CS_LCH: FLVL port map(CS_LCH_Set,CS_LCH_Reset,sCTRL.CTRL_CS); -- AA2D7 +CS_LCH: entity FLVL port map(CS_LCH_Set,CS_LCH_Reset,sCTRL.CTRL_CS); -- AA2D7 CTRL <= sCTRL; CK_SAL_P_BIT_TO_MPX <= SALS_PK and not MACH_RST_MPX; diff --git a/FMD2030_5-02A-B.vhd b/FMD2030_5-02A-B.vhd index 9d9c9e2..67055f9 100644 --- a/FMD2030_5-02A-B.vhd +++ b/FMD2030_5-02A-B.vhd @@ -212,17 +212,17 @@ USE_CA_BASIC_DECODER <= sUSE_CA_BASIC_DECODER; REST0_LCH_Set <= T2 and sGT_GWX_TO_WX_REG; REST0_LCH_Reset <= MACH_RST_SW or T1; -REST0_LCH: FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0 +REST0_LCH: entity FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0 SXREST_LCH_Set <= T4 and RESTORE_0; SXREST_LCH_Reset <= MACH_RST_SW or T3; -SXREST_LCH: FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1 +SXREST_LCH: entity FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1 MPXROS_LCH_Set <= T2 and sGT_FWX_TO_WX_REG; MPXROS_LCH_Reset <= MACH_RST_SW or T1; -MPXROS_LCH: FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2 +MPXROS_LCH: entity FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2 MPX_ROS_LCH <= sMPX_ROS_LCH; MPXREST_LCH_Set <= T4 and sMPX_ROS_LCH; MPXREST_LCH_Reset <= MACH_RST_SW or T3; -MPXREST_LCH: FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3 +MPXREST_LCH: entity FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3 X6_DATA <= X6_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6 X7_DATA <= X7_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6 @@ -231,11 +231,11 @@ GT_MPX_LCH <= (MPX_SHARE_PULSE and T1) or MACH_RST_SW; -- AA3L4,AA3E3 GT_SX_LCH <= (SX_CHAIN_PULSE and T1) or MACH_RST_SW; -- AA3F3,AA3L6 -- ASCII latch plus X6,X7 storage for -ASC_LCH: PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3 -M7_LCH: PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3 -S7_LCH: PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3 -M6_LCH: PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3 -S6_LCH: PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3 +ASC_LCH: entity PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3 +M7_LCH: entity PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3 +S7_LCH: entity PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3 +M6_LCH: entity PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3 +S6_LCH: entity PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3 STORED_X6 <= (SX_CH_ROAR_RESTORE and SX_CH_X6) or (MPX_CH_ROAR_RESTORE and MPX_CH_X6); -- AA3K6 STORED_X7 <= (SX_CH_ROAR_RESTORE and SX_CH_X7) or (MPX_CH_ROAR_RESTORE and MPX_CH_X7); -- AA3K6 diff --git a/FMD2030_5-03A.vhd b/FMD2030_5-03A.vhd index 9c5d806..d40d367 100644 --- a/FMD2030_5-03A.vhd +++ b/FMD2030_5-03A.vhd @@ -164,17 +164,17 @@ SUPPR_MACH_CHK_TRAP <= sSUPPR_MACH_CHK_TRAP; -- ?? -- SUPPR_MACH_CHK_TRAP <= not RECYCLE_RST; -- ?? sANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE; -- AB3D7 ANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE_2; -ANY_PRIORITY: PH port map(sANY_PRIORITY_PULSE_2,T1,sANY_PRIORITY_LCH); -- AB3D7,AB3J2 +ANY_PRIORITY: entity PH port map(sANY_PRIORITY_PULSE_2,T1,sANY_PRIORITY_LCH); -- AB3D7,AB3J2 ANY_PRIORITY_LCH <= sANY_PRIORITY_LCH; -S1_DLYD: PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2 -WX_SABC: PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2 +S1_DLYD: entity PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2 +WX_SABC: entity PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2 GT_SW_TO_WX_LCH <= sGT_SW_TO_WX_LCH; CD0101 <= '1' when SALS_CDREG="0101" else '0'; PRIOR_RST_Latch <= T4 or MACH_RST_SW; -PRIOR_RST_CTRL_PH: PHR port map(D=>CD0101,L=>PRIOR_RST_Latch,R=>sANY_PRIORITY_PULSE,Q=>PRIOR_RST_CTRL); -- AB3J2 +PRIOR_RST_CTRL_PH: entity PHR port map(D=>CD0101,L=>PRIOR_RST_Latch,R=>sANY_PRIORITY_PULSE,Q=>PRIOR_RST_CTRL); -- AB3J2 MEMP_LCH_Set <= sDATA_READY and ALLOW_PROTECT and PROT_LOC_CPU_OR_MPX; MEMP_LCH_Reset <= READ_CALL or RECYCLE_RST; -STG_PROT_REQ: FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7 +STG_PROT_REQ: entity FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7 MEM_PROTECT_REQ <= sMEM_PROTECT_REQ; sHZ_DEST_RST <= (P4 and sGT_SW_TO_WX_LCH) or (T3 and PRIOR_RST_CTRL); -- AB3K5,AB3J4 @@ -186,7 +186,7 @@ DATA_READY <= sDATA_READY; PRI_LCH_Set <= (T1 and DIAGNOSTIC_SW) or MACH_RST_LCH or (not HARD_STOP_LCH and T3 and sANY_PRIORITY_LCH); PRI_LCH_Reset <= sHZ_DEST_RST or sGT_SW_MACH_RST; -PRIORITY: FLL port map(S=>PRI_LCH_Set,R=>PRI_LCH_Reset,Q=>PRIORITY_LCH); -- AB3J4,AB3L4 +PRIORITY: entity FLL port map(S=>PRI_LCH_Set,R=>PRI_LCH_Reset,Q=>PRIORITY_LCH); -- AB3J4,AB3L4 -- Priority stack register - all inputs are inverted AB3L2 PRIORITY_STACK_IN(0) <= GT_SWS_TO_WX_PWR; @@ -199,7 +199,7 @@ PRIORITY_STACK_IN(6) <= STOP_REQ; PRIORITY_STACK_IN(7) <= SUPPR_A_REG_CHK and not H_REG_5_PWR and SEL_ROS_REQ; PRIORITY_STACK_IN(8) <= FT_3_MPX_SHARE_REQ and not H_REG_6 and not H_REG_5_PWR; PRISTK_LCH_Latch <= MACH_RST_6 or (not ALLOW_WRITE and T3) or (P4 and GT_SWS_TO_WX_PWR); -PRISTK_LCH: PHV9 port map( D => PRIORITY_STACK_IN, +PRISTK_LCH: entity PHV9 port map( D => PRIORITY_STACK_IN, L => PRISTK_LCH_Latch, Q => PRIORITY_STACK_OUT); sGT_SWS_TO_WX_LCH <= PRIORITY_STACK_OUT(0); @@ -234,7 +234,7 @@ SX_CHAIN_PULSE_1 <= SX_CHAIN_PULSE; sMPX_SHARE_PULSE <= not SX_CHAIN_PULSE and not STOP_PULSE and not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and MPX_SHARE_REQ_LCH and not (H(5) or H(6)); -- ?? MPX_SHARE_PULSE <= sMPX_SHARE_PULSE; -SRP_LCH: FLL port map(MACH_RST_SW,T4,sSYS_RST_PRIORITY_LCH); -- AB3L3 +SRP_LCH: entity FLL port map(MACH_RST_SW,T4,sSYS_RST_PRIORITY_LCH); -- AB3L3 SYS_RST_PRIORITY_LCH <= sSYS_RST_PRIORITY_LCH; sANY_PRIORITY_PULSE <= sMPX_SHARE_PULSE or SX_CHAIN_PULSE or STOP_PULSE or PROTECT_PULSE or HI_PRIORITY or sSYS_RST_PRIORITY_LCH; -- AB3K4 ?? diff --git a/FMD2030_5-03B.vhd b/FMD2030_5-03B.vhd index e009d90..7b8b826 100644 --- a/FMD2030_5-03B.vhd +++ b/FMD2030_5-03B.vhd @@ -117,12 +117,12 @@ CHECK_MPX_WRAP <= H_REG_6 and not H_REG_5_PWR; -- AB2L4 CARRY_OUT <= CARRY_OUT_TRUE or CARRY_OUT_COMP; -- AB2L3 UWRAP_LCH_Reset <= RECYCLE_RST or RESET_WRAP; -UWRAP_LCH: PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4 -IWRAP_LCH: PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4 +UWRAP_LCH: entity PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4 +IWRAP_LCH: entity PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4 I_WRAPPED_CPU <= sI_WRAPPED_CPU; -UMPX_LCH: PHR port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,R=>RECYCLE_RST,Q=>sU_WRAPPED_MPX); -- AB2M4 ?? Doesn't have reset in FMD - causes Diag failure +UMPX_LCH: entity PHR port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,R=>RECYCLE_RST,Q=>sU_WRAPPED_MPX); -- AB2M4 ?? Doesn't have reset in FMD - causes Diag failure U_WRAPPED_MPX <= sU_WRAPPED_MPX; -WBUFF_LCH: PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ?? +WBUFF_LCH: entity PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ?? WRAP64 <= (not H_REG_6 and GT_V_TO_N_REG and U_WRAP_CPU) or (GT_J_TO_N_REG and not H_REG_6 and sI_WRAPPED_CPU) or @@ -137,7 +137,7 @@ MEM_WRAP <= sMEM_WRAP; MWR_LCH_Set <= MAIN_STORAGE and T2 and (sMEM_WRAP and not ALLOW_WRITE); -- ?? ALLOW_WRITE use unclear - dot logic MWR_LCH_Reset <= READ_CALL or RECYCLE_RST; -MWR_LCH: FLL port map(MWR_LCH_Set,MWR_LCH_Reset,sMEM_WRAP_REQ); +MWR_LCH: entity FLL port map(MWR_LCH_Set,MWR_LCH_Reset,sMEM_WRAP_REQ); MEM_WRAP_REQ <= sMEM_WRAP_REQ; SEL_DATA_READY <= (DATA_READY_1 or DATA_READY_2) and not sMEM_WRAP_REQ; diff --git a/FMD2030_5-03C.vhd b/FMD2030_5-03C.vhd index 6888e1a..3f5c596 100644 --- a/FMD2030_5-03C.vhd +++ b/FMD2030_5-03C.vhd @@ -180,46 +180,46 @@ signal CSC_LCH_Set,SSR_LCH_Set,SSR_LCH_Reset,ECS_LCH_Set,ECS_LCH_Reset,LKI_LCH_S BEGIN -- Fig 5-03C -- STT RST INLK -SRI_LCH: FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output +SRI_LCH: entity FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output -- STT RST SSR_LCH_Set <= ALLOW_MAN_OPER and STT_RST_INLK and not SW_START; SSR_LCH_Reset <= T2 or MACH_RST_SW; -SSR_LCH: FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7 +SSR_LCH: entity FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7 START_SW_RST <= sSTART_SW_RST; -- CLK STT CTRL CSC_LCH_Set <= sCLOCK_RST or sE_CY_STOP_SAMPLE; -CSC_LCH: FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5 +CSC_LCH: entity FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5 -- E CY STOP SAMPLE ECS_LCH_Set <= SET_IC_START or (FT3_MPX_SHARE_REQ and M_CONV_OSC and PROC_STOP_LOOP_ACTIVE) or (M_CONV_OSC and PROC_STOP_LOOP_ACTIVE and SEL_ROS_REQ) or (not SW_START and M_CONV_OSC and not CLK_STT_CTRL); -- "not CLK_STT_CTRL" ?? is CLK_STT_CTRL meant to be inverted? ECS_LCH_Reset <= MACH_RST_SW or T4; -ECS_LCH: FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7 +ECS_LCH: entity FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7 E_CY_STOP_SAMPLE <= sE_CY_STOP_SAMPLE; -- LOAD KEY INLK LKI_LCH_Set <= (not SW_LOAD and MACH_RST_3) or LOAD_KEY; -LKI_LCH: FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output +LKI_LCH: entity FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output LOAD_KEY_INLK <= sLOAD_KEY_INLK; -- LOAD KEY LK_LCH_Set <= not sLOAD_KEY_SW and sLOAD_KEY_INLK; LK_LCH_Reset <= T4 or sCLOCK_RST; -LK_LCH: FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7 +LK_LCH: entity FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7 sLOAD_KEY_SW <= SW_LOAD; LOAD_KEY_SW <= sLOAD_KEY_SW; -- SET IC INLK SI_LCH_Set <= (CLOCK_ON and SW_SET_IC) or MACH_RST_3 or sSET_IC_ALLOWED; -- MACH_RST_3 inverted?? SI_LCH_Reset <= not SW_SET_IC; -- FMD is missing invert on switch output?? -SI_LCH: FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7 +SI_LCH: entity FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7 -- SET IC SIA_LCH_Set <= ALLOW_MAN_OPER and not SET_IC_INLK and SW_SET_IC; SIA_LCH_Reset <= T2 or MACH_RST_SW; -SIA_LCH: FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7 +SIA_LCH: entity FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7 SET_IC_ALLOWED <= sSET_IC_ALLOWED; SET_IC_START <= not FORCE_IJ_REQ_LCH and M_CONV_OSC and sSET_IC_ALLOWED; -- AC1D6 -- PROCESS STOP PS_LCH_Set <= sSET_IC_ALLOWED or SW_STOP or (SAR_DLYD_STOP_SW and MATCH) or (INSTRUCTION_STEP_SW and T4); PS_LCH_Reset <= sSTART_SW_RST or '0'; -- ?? What is second reset input? -PS_LCH: FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5 +PS_LCH: entity FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5 DEBUG <= PROCESS_STOP; -- ?? DEBUG ?? -- PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed?? PROC_STOP_LOOP_ACTIVE <= ((USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed?? and inverter on AA2G5 removed?? @@ -228,7 +228,7 @@ STOP_REQ <= PROCESS_STOP and not S_REG_1_DLYD and not INTERRUPT and END_OF_E_CY_ -- CF STOP CF100T4 <= SALS.SALS_CF(0) and not SALS.SALS_CF(1) and not SALS.SALS_CF(2) and T4; -- AA2G5 CFS_LCH_Reset <= (not CF100T4 and T4) or (not FORCE_IJ_REQ and not sROS_SCAN and not SW_PROC) or MACH_START_RST; -- AC1G5 AC1K6 AC1M5 AC1F2 ?? SW_INH_CF_STOP instead of SW_PROC ?? -CFS_LCH: FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5 +CFS_LCH: entity FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5 sROS_SCAN <= SW_SCAN; ROS_SCAN <= sROS_SCAN; ROS_CTRL_PROC_SW <= SW_PROC; @@ -240,7 +240,7 @@ INSTRUCTION_STEP_SW <= SW_INSTRUCTION_STEP; sRST_LOAD <= GT_CK_DECODE and SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3); -- AB3F7 RST_LOAD <= sRST_LOAD; sRST_SEL_CHNL_DIAG_LCHS <= MACH_RST_3 or sRST_LOAD; -- AC1F5,AC1H6 -LOAD_REQ_FL: FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5 +LOAD_REQ_FL: entity FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5 RST_SEL_CHNL_DIAG_LCHS <= sRST_SEL_CHNL_DIAG_LCHS; LOAD_IND <= sLOAD_IND; LOAD_REQ <= sLOAD_IND; @@ -249,7 +249,7 @@ FT_4_LD_IND <= sLOAD_IND; -- CLOCK START CS_LCH_Set <= (LOAD_KEY and P_CONV_OSC) or (P_CONV_OSC and sE_CY_STOP_SAMPLE and not MAN_OPERATION); CS_LCH_Reset <= sCLOCK_RST or sCLOCK_STOP; -CS_LCH: FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6 +CS_LCH: entity FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6 CLOCK_START_LCH <= sCLOCK_START_LCH; sSEL_CHNL_CPU_CLOCK_STOP <= not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and T4) and @@ -262,13 +262,13 @@ CLOCK_START <= sCLOCK_START; -- 2ND ERR STP N2E_LCH_Set <= MACH_CHK_PULSE and P1; N2E_LCH_Reset <= MACH_CHK_RST or HZ_DEST_RST; -N2E_LCH: FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4 +N2E_LCH: entity FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4 N2ND_ERROR_STOP <= sN2ND_ERROR_STOP; --PWR OFF sPWR_OFF_SW <= SW_PWR_OFF; PWR_OFF_SW <= sPWR_OFF_SW; PO_LCH_Set <= sPWR_OFF_SW and T3 and not ALLOW_WRITE; -PO_LCH: FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4 +PO_LCH: entity FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4 -- HARD STOP HS_MACH_CHK <= (sN2ND_ERROR_STOP and T4 and FIRST_MACH_CHK) or (CHK_OR_DIAG_STOP_SW and ANY_MACH_CHK); -- AB3F4 sEARLY_ROAR_STOP <= MATCH_LCH and EARLY_ROAR_STOP_SW; -- AC1K5 @@ -282,7 +282,7 @@ HS_MATCH <= (SAR_STOP_SW and MATCH_LCH and T4) or (ROAR_STOP_SW and T4 and MATCH HS_INSTR <= T4 and INSTRUCTION_STEP_SW and ANY_PRIORITY_PULSE_PWR and sROS_SCAN; -- AB3H2 HS_LCH_Set <= HS_MACH_CHK or sEARLY_ROAR_STOP or HS_ALU_CHK or HS_DIAG or HS_MATCH or HS_INSTR; -HS_LCH: FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6 +HS_LCH: entity FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6 HARD_STOP_LCH <= sHARD_STOP_LCH; sCLOCK_RST <= MACH_RST_3 or (sHARD_STOP_LCH and M_CONV_OSC_2) or (M_CONV_OSC_2 and not GT_J_REG_TO_A_BUS and CF_STOP); -- AC1F6,AC1G5 diff --git a/FMD2030_5-03D.vhd b/FMD2030_5-03D.vhd index d4b6ddb..eb2b090 100644 --- a/FMD2030_5-03D.vhd +++ b/FMD2030_5-03D.vhd @@ -136,25 +136,25 @@ sALLOW_MAN_OPERATION <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CLOCK ALLOW_MAN_OPERATION <= sALLOW_MAN_OPERATION; UMD_LCH_Set <= (sALLOW_MAN_OPERATION and SW_DSPLY) or (sALLOW_MAN_OPERATION and SW_STORE); UMD_LCH_Reset <= E_CY_STOP_SMPL or sMACH_RST_3; -UMD_LCH: FLL port map(UMD_LCH_Set,UMD_LCH_Reset, sUSE_MANUAL_DECODER); -- AC1G4 +UMD_LCH: entity FLL port map(UMD_LCH_Set,UMD_LCH_Reset, sUSE_MANUAL_DECODER); -- AC1G4 USE_MANUAL_DECODER <= sUSE_MANUAL_DECODER; USE_MAN_DECODER_PWR <= not E_CY_STOP_SMPL and sUSE_MANUAL_DECODER; -- AC1J4 -- MAN DSPLY AC1D4 <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CONV_OSC); -- AC1G2,AC1D4 -- Inverter removed ?? MD_LCH_Set <= CLOCK_OFF and SW_DSPLY and AC1D4; -MD_LCH: FLL port map(MD_LCH_Set,not SW_DSPLY,sMANUAL_DISPLAY); -- AC1G4 - FMD missing invert on Reset input ?? +MD_LCH: entity FLL port map(MD_LCH_Set,not SW_DSPLY,sMANUAL_DISPLAY); -- AC1G4 - FMD missing invert on Reset input ?? MANUAL_DISPLAY <= sMANUAL_DISPLAY; -- MAN STORE R sSTORE_S_REG_RST <= not CLOCK_ON and SW_STORE; -- AC1J6 STORE_S_REG_RST <= sSTORE_S_REG_RST; MS_LCH_Set <= AC1D4 and sSTORE_S_REG_RST; -MS_LCH: FLL port map(MS_LCH_Set,not SW_STORE,sMAN_STORE); -- AC1E5 +MS_LCH: entity FLL port map(MS_LCH_Set,not SW_STORE,sMAN_STORE); -- AC1E5 MAN_STORE <= sMAN_STORE; -- MAN_STORE_PWR <= sMAN_STORE; -- AC1F3 -- Need to delay this a bit -MAN_STORE_DELAY: AR port map(sMAN_STORE,Clk,sMAN_STORE2); -- AC1F3 -MAN_STORE2_DELAY: AR port map(sMAN_STORE2,Clk,MAN_STORE_PWR); -- AC1F3 +MAN_STORE_DELAY: entity AR port map(sMAN_STORE,Clk,sMAN_STORE2); -- AC1F3 +MAN_STORE2_DELAY: entity AR port map(sMAN_STORE2,Clk,MAN_STORE_PWR); -- AC1F3 sMAN_STOR_OR_DSPLY <= sMANUAL_DISPLAY or sMAN_STORE; -- AC1J2,AC1F3 MAN_STOR_OR_DSPLY <= sMAN_STOR_OR_DSPLY; @@ -181,7 +181,7 @@ CPU_SET_ALLOW_WR_LCH <= sCPU_SET_ALLOW_WR_LCH; -- ALLOW WR AW_LCH_Set <= sCPU_SET_ALLOW_WR_LCH or SEL_AUX_RD_CALL; AW_LCH_Reset <= sMACH_RST_3 or SEL_WR_CALL or MAN_WR_CALL or (ROAR_RESTT_STOR_BYPASS and RECYCLE_RST) or (CPU_WR_PWR and T2); -ALLOW_WRITE_LCH: FLL port map(AW_LCH_Set,AW_LCH_Reset,sALLOW_WRITE); -- AA1J2,AA1F6,AA1H3 +ALLOW_WRITE_LCH: entity FLL port map(AW_LCH_Set,AW_LCH_Reset,sALLOW_WRITE); -- AA1J2,AA1F6,AA1H3 ALLOW_WRITE <= sALLOW_WRITE; DELAY_ALLOW_WR : entity AR port map (D=>sALLOW_WRITE,clk=>Clk,Q=>sALLOW_WR); -- AA1H2,AA1J7 ALLOW_WR_DLYD <= sALLOW_WR; @@ -189,14 +189,14 @@ ALLOW_WR_DLYD <= sALLOW_WR; -- MAN WR CALL MW_LCH_Set <= (sALLOW_WR and LOAD_KEY_INLK) or (sALLOW_WR and sSYSTEM_RST_SW) or (sALLOW_WR and POWER_OFF_SW) or (sMAN_STOR_OR_DSPLY and READ_ECHO); MW_LCH_Reset <= CLOCK_ON or MAN_WR_CALL_RST; -MW_LCH: FLL port map(MW_LCH_Set,MW_LCH_Reset,MAN_WR_CALL); -- AC1J2,AC1F4,AC1H5 +MW_LCH: entity FLL port map(MW_LCH_Set,MW_LCH_Reset,MAN_WR_CALL); -- AC1J2,AC1F4,AC1H5 -- MAN RD INLK -MAN_RD_INLK_FL: FLL port map(MAN_RD_CALL_LCH,not sMAN_STOR_OR_DSPLY,MAN_RD_INLK); -- AC1F4 +MAN_RD_INLK_FL: entity FLL port map(MAN_RD_CALL_LCH,not sMAN_STOR_OR_DSPLY,MAN_RD_INLK); -- AC1F4 -- MAN RD CALL MRC_LCH_Set <= sSTG_MEM_SEL and not MAN_RD_INLK and sMAN_STOR_OR_DSPLY; MRC_LCH_Reset <= not sMAN_STOR_OR_DSPLY or READ_ECHO; -MAN_RD_CALL_FL: FLL port map(MRC_LCH_Set,MRC_LCH_Reset,MAN_RD_CALL_LCH); -- AC1J2,AC1E2 +MAN_RD_CALL_FL: entity FLL port map(MRC_LCH_Set,MRC_LCH_Reset,MAN_RD_CALL_LCH); -- AC1J2,AC1E2 sMAN_RD_CALL <= MAN_RD_CALL_LCH and not sALLOW_WR; -- AC1J2 MAN_RD_CALL <= sMAN_RD_CALL; @@ -212,7 +212,7 @@ MANUAL_OPERATION <= sMAN_RD_CALL or MAN_WR_CALL or MAN_WR_CALL_RST or READ_ECHO; -- STORE R SR_LCH_Set <= MAN_WR_CALL or (T1 and USE_R); SR_LCH_Reset <= SEL_T1 or (T1 and not CU_SALS(0) and CU_SALS(1)); -SR_LCH: FLL port map(SR_LCH_Set,SR_LCH_Reset,sSTORE_R); -- 06C +SR_LCH: entity FLL port map(SR_LCH_Set,SR_LCH_Reset,sSTORE_R); -- 06C STORE_R <= sSTORE_R; MAN_WRITE_CALL <= not READ_ECHO and MAN_WR_CALL and sSTORE_R; -- AC1G3 diff --git a/FMD2030_5-04A-B.vhd b/FMD2030_5-04A-B.vhd index bd1477e..8932089 100644 --- a/FMD2030_5-04A-B.vhd +++ b/FMD2030_5-04A-B.vhd @@ -176,7 +176,7 @@ BEGIN -- Fig 5-04A NW_LCH_Set <= N_CTRL_N and XOR_OR_OR and T2; NW_LCH_Reset <= not S_REG_7_BIT or sRECYCLE_RST; -NW_LCH: FLL port map(NW_LCH_Set,NW_LCH_Reset,NWAIT); --AC1E6,AC1F6 +NW_LCH: entity FLL port map(NW_LCH_Set,NW_LCH_Reset,NWAIT); --AC1E6,AC1F6 sCLOCK_OUT <= (not NWAIT and CLOCK_ON) or MAN_STOR_OR_DSPLY; -- AC1G6 CLOCK_OUT <= sCLOCK_OUT; CHNL_TO_METER <= not HARD_STOP_LCH and (MPX_METERING_IN or METER_IN_SX1 or METER_IN_SX2); -- AC1K4,AC1F2 ?? @@ -203,16 +203,16 @@ IND_SEL_CHNL <= H_REG_5_PWR or sLAMP_TEST; TEST <= (not ROS_CTRL_PROC_SW) or (not RATE_SW_PROC_SW) or (not SW_ADDR_COMP_PROC) or (not ODD) or (not sCHK_SW_PROCESS_SW) or INTRODUCE_ALU_CHK; -- AC1C4,AC1K5,AC1D4,AC1K5 ?? MRS_LCH_Reset <= not LOAD_KEY_SW and not SYSTEM_RESET_SW; -MRS_LCH: FLL port map(MACH_RST_SW,MRS_LCH_Reset,sMACH_RST_SET_LCH); -- AA2H5,AA2F5 +MRS_LCH: entity FLL port map(MACH_RST_SW,MRS_LCH_Reset,sMACH_RST_SET_LCH); -- AA2H5,AA2F5 MACH_RST_SET_LCH <= sMACH_RST_SET_LCH; MACH_RST_SET_LCH_DLYD <= sMACH_RST_SET_LCH; -- ?? Should be delayed by 1 gate -- MACH_RST_DELAY: AR port map(D=>sMACH_RST_SET_LCH,CLK=>Clk,Q=>MACH_RST_SET_LCH_DLYD); -- Delay FORCE_DEAD_CY <= SW_SAR_RESTART and T4 and MATCH_SET_MACH_RST_LCH; -- AB3B6 -FDC_LCH: FLL port map(FORCE_DEAD_CY,T3,sFORCE_DEAD_CY_LCH); -- AB3L3 +FDC_LCH: entity FLL port map(FORCE_DEAD_CY,T3,sFORCE_DEAD_CY_LCH); -- AB3L3 FORCE_DEAD_CY_LCH <= sFORCE_DEAD_CY_LCH; EEC_LCH_Set <= T2 and (CL_SALS(0) and CL_SALS(1) and CL_SALS(2) and CL_SALS(3)); -- ?? additional NOT -EEC_LCH: FLL port map(EEC_LCH_Set,T1,sEND_OF_E_CY_LCH); -- AC1G4 ?? Reset input is unlabeled +EEC_LCH: entity FLL port map(EEC_LCH_Set,T1,sEND_OF_E_CY_LCH); -- AC1G4 ?? Reset input is unlabeled END_OF_E_CY_LCH <= sEND_OF_E_CY_LCH; END_OF_E_CYCLE <= sEND_OF_E_CY_LCH or INH_ROSAR_SET; -- AC1J7 @@ -221,18 +221,18 @@ MATCH_SET_MACH_RST_LCH <= ((SW_SAR_RESTART and sMATCH_LCH and not ALLOW_WRITE_DL FIJ_LCH_Set <= (MATCH_SET_MACH_RST_LCH and CLOCK_ON) or SET_IC_LCH; -- ?? *not* MATCH_SET_MACH_RST_LCH & *not* CLOCK_ON ?? FIJ_LCH_Reset <= MACH_RST_3 or (T1 and FORCE_IJ_PULSE); -FIJ_LCH: FLL port map(FIJ_LCH_Set,FIJ_LCH_Reset,sFORCE_IJ_REQ); -- AC1E6,AC1H6 +FIJ_LCH: entity FLL port map(FIJ_LCH_Set,FIJ_LCH_Reset,sFORCE_IJ_REQ); -- AC1E6,AC1H6 FORCE_IJ_REQ <= sFORCE_IJ_REQ; MACH_START_RST <= (sFORCE_IJ_REQ and not FORCE_IJ_REQ_LCH) or START_SW_RST or MACH_RST_6; -- AB3J5,AB3H3 CR_LCH_Set <= ANY_MACH_CHK and CHK_RESTART_SW; CR_LCH_Reset <= ANY_PRIORITY_LCH or sMACH_CHK_RST; -CR_LCH: FLL port map(CR_LCH_Set,CR_LCH_Reset,CHK_RESTT_LCH); -- AB3H4,AC1H6 +CR_LCH: entity FLL port map(CR_LCH_Set,CR_LCH_Reset,CHK_RESTT_LCH); -- AB3H4,AC1H6 CHK_RESTART_SW <= SW_CHK_RESTART; -- Diagnostic latch is not in the FMD but must have appeared later -- It is set on Sys Reset and reset by the YL / 0->DIAG function (Alt-CK=0000) -DIAG_FL: FLL port map(S=>MACH_RST_6,R=>DIAG_LATCH_RST,Q=>DIAG_LATCH); +DIAG_FL: entity FLL port map(S=>MACH_RST_6,R=>DIAG_LATCH_RST,Q=>DIAG_LATCH); sDIAGNOSTIC_SW <= SW_DIAGNOSTIC or DIAG_LATCH; DIAGNOSTIC_SW <= sDIAGNOSTIC_SW; @@ -258,7 +258,7 @@ CHK_RST_SW <= SW_CHK_RST; -- AB3F5 MR_LCH_Set <= FORCE_DEAD_CY or MACH_RST_6; MR_LCH_Reset <= HZ_DEST_RST or SW_ROAR_RST; -- ?? *not* SW_ROAR_RST -MR_LCH: FLL port map(MR_LCH_Set,MR_LCH_Reset,sMACH_RST_LCH); -- AB3F2,AB3J4 +MR_LCH: entity FLL port map(MR_LCH_Set,MR_LCH_Reset,sMACH_RST_LCH); -- AB3F2,AB3J4 MACH_RST_LCH <= sMACH_RST_LCH; GSWX_LCH_Set <= (SW_ROAR_RST and ALLOW_MAN_OPERATION) or @@ -267,7 +267,7 @@ GSWX_LCH_Set <= (SW_ROAR_RST and ALLOW_MAN_OPERATION) or (not ALLOW_WRITE_DLYD and ROAR_RESTT_SW_ORED and sMATCH) or (SW_ROAR_RESTT_STOR_BYPASS and CHK_RESTT_LCH); GSWX_LCH_Reset <= MACH_RST_SW or (T3 and GT_SW_TO_WX_LCH); -GSWX_LCH: FLL port map(GSWX_LCH_Set,GSWX_LCH_Reset,sGT_SWS_TO_WX_REG); -- AC1H5,AC1H7,AC1H4,AC1K5,AC1J7 +GSWX_LCH: entity FLL port map(GSWX_LCH_Set,GSWX_LCH_Reset,sGT_SWS_TO_WX_REG); -- AC1H5,AC1H7,AC1H4,AC1K5,AC1J7 GT_SWS_TO_WX_PWR <= not sMACH_RST_LCH and sGT_SWS_TO_WX_REG; -- AC1E7 @@ -301,7 +301,7 @@ ANDWX <= (WX_REG_BUS(0) xor not ABCD_SW_BUS(3)) and OEA1 and OEA2 and OEA3 and G M_LCH_Set <= ANDMN or ANDWX; M_LCH_Reset <= RST_MATCH or MACH_RST_SW; -M_LCH: FLL port map(M_LCH_Set,M_LCH_Reset,sMATCH_LCH); -- AC1L7,AC1L4 +M_LCH: entity FLL port map(M_LCH_Set,M_LCH_Reset,sMATCH_LCH); -- AC1L7,AC1L4 MATCH_LCH <= sMATCH_LCH; sMATCH <= sMATCH_LCH and not CLOCK_OFF; -- AC1H5 MATCH <= sMATCH; diff --git a/FMD2030_5-04C.vhd b/FMD2030_5-04C.vhd index 462c947..254d499 100644 --- a/FMD2030_5-04C.vhd +++ b/FMD2030_5-04C.vhd @@ -141,14 +141,14 @@ RST_COUNTER <= MACH_RST_PROT; -- BE3G5 CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (not sTIMER_UPDATE and SW_INTRP_TIMER); CTL_LCH_Reset <= CTRL_TRG and T3; -CTL_LCH: FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5 +CTL_LCH: entity FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5 N10MSPULSE <= not(N60_CY_TIMER_PULSE and not T3); -- 10ms monostable here CT_FF_Set <= CTRL_LCH and T4; -CT_FF: FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6 +CT_FF: entity FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6 BD_FF_Set <= not CTRL_LCH and T2 and N10MSPULSE and not CNTR_FULL; -BD_FF: FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6 +BD_FF: entity FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6 process(BIN_DRIVE,RST_COUNTER,CTRL_TRG) -- BE3G7,BE3F7 begin @@ -171,7 +171,7 @@ EXT_INT <= (F_REGISTER(0) or F_REGISTER(1) or F_REGISTER(2) or F_REGISTER(3) or F_REGISTER(4) or F_REGISTER(5) or F_REGISTER(6) or F_REGISTER(7)) and EXT_TRAP_MASK_ON; -- AC1G2 ?? Should this include EXT_TRAP_MASK_ON ? EI_LCH_Reset <= MACH_RST_SW or RESET_F_REG; EI_LCH_Set <= EXT_INT and T3; -- ?? Seems to be needed, not as per MDM -EI_LCH: FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2 +EI_LCH: entity FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2 -- F register - here it is held in True polarity, in the 2030 it is inverted C_EXT_INT <= "000000"; @@ -180,11 +180,11 @@ RESET_F_REG <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and not CK_SALS(3) and G F1A_LCH_Reset <= (L_REGISTER(1) and RESET_F_REG) or RECYCLE_RST; F1_LCH_Set <= F_REGISTER_1A and SW_CONS_INTRP; -F1A_LCH: FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2 +F1A_LCH: entity FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2 F07_LCH_Set <= SET_F_REG_0 & F1_LCH_Set & C_EXT_INT(2 to 7); F07_LCH_Reset <= (0 to 7 => RECYCLE_RST) or ((0 to 7 => RESET_F_REG) and ('1' & L_REGISTER(1 to 7))); -F07_LCH: FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2 +F07_LCH: entity FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2 -- H register H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or @@ -192,9 +192,9 @@ H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or GT_1050_TAGS <= not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and not CD_CTRL_REG(3); -- AB1B3 CD=0100 GT_1050_BUS <= not CD_CTRL_REG(0) and not CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3); -- AB1B3 CD=0001 CD_REG_2 <= CD_CTRL_REG(2); -- AB1B3 -H_LCH: PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3 +H_LCH: entity PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3 H_REG_BITS <= sH_REG_BITS; -HP_LCH: PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3 +HP_LCH: entity PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3 H_REG_P <= sH_REG_P; H_REG_6 <= sH_REG_BITS(6); -- AB1C6,AB1G2 H_REG_5_PWR <= sH_REG_BITS(5); -- AB1L2 diff --git a/FMD2030_5-04D.vhd b/FMD2030_5-04D.vhd index 535f738..0672cdd 100644 --- a/FMD2030_5-04D.vhd +++ b/FMD2030_5-04D.vhd @@ -115,7 +115,7 @@ RD_SEL <= MANUAL_RD_CALL or (sCPU_READ_PWR and T1) or sCHANNEL_RD_CALL; -- BE3D3 WR_SEL <= (T1 and sCPU_WRITE_PWR and ALLOW_WRITE_2) or MANUAL_WR_CALL or (SEL_RD_CALL_TO_STP or HSMPX_READ_CALL); -- BE3J5,BE3H5 N_MEM_SELECT <= not (not SELECT_CPU_BUMP and (RD_SEL or WR_SEL)); -- BE3H6 -- ?? Note TD not implemented (yet) -RW_LCH: FLL port map(RD_SEL,WR_SEL,RW_CTRL_STACK); -- BE3J5 +RW_LCH: entity FLL port map(RD_SEL,WR_SEL,RW_CTRL_STACK); -- BE3J5 sUSE_ALT_CU_DECODE <= not ANY_PRIORITY_PULSE and not sCPU_READ_PWR; -- AB3D2 USE_ALT_CU_DECODE <= sUSE_ALT_CU_DECODE; @@ -152,8 +152,8 @@ sGT_LOCAL_STG <= ((MEM_SEL and not ALLOW_WRITE) and MAN_STOR_OR_DISPLAY) or (T1 GT_LOCAL_STG <= sGT_LOCAL_STG; -LS_LCH: PH port map(not sMAIN_STORAGE_CP,sGT_LOCAL_STG,LOCAL_STORAGE_CP); -- AA1F4 -MS_LCH: PH port map(not sEARLY_LOCAL_STG,sGT_LOCAL_STG,MAIN_STORAGE); -- AA1F4 +LS_LCH: entity PH port map(not sMAIN_STORAGE_CP,sGT_LOCAL_STG,LOCAL_STORAGE_CP); -- AA1F4 +MS_LCH: entity PH port map(not sEARLY_LOCAL_STG,sGT_LOCAL_STG,MAIN_STORAGE); -- AA1F4 END FMD; diff --git a/FMD2030_5-05A.vhd b/FMD2030_5-05A.vhd index f76dd23..74af8ff 100644 --- a/FMD2030_5-05A.vhd +++ b/FMD2030_5-05A.vhd @@ -95,7 +95,7 @@ BEGIN N1401_MODE_SET <= W3_TO_MATCH and not ROS_SCAN; -- AC1C4 N1401_MODE_RESET <= T2 or GT_SW_MACH_RST; - MODE1401: FLL port map(N1401_MODE_SET,N1401_MODE_RESET,sN1401_MODE); -- AB2B2,AB1B3,AB2C2 + MODE1401: entity FLL port map(N1401_MODE_SET,N1401_MODE_RESET,sN1401_MODE); -- AB2B2,AB1B3,AB2C2 N1401_MODE <= sN1401_MODE; V67_EQUALS_00 <= not V_REG_6 and not V_REG_7; -- AA1H6 diff --git a/FMD2030_5-05D.vhd b/FMD2030_5-05D.vhd index 230dcb4..c00ed3c 100644 --- a/FMD2030_5-05D.vhd +++ b/FMD2030_5-05D.vhd @@ -119,7 +119,7 @@ WRITE_CALL_TO_MEM <= (MAN_WR_CALL or SEL_WR_CALL or START_WR) and not ROAR_RESTT USE_LOCAL_Set <= EARLY_LOCAL_STG and READ_CALL_TO_MEM; USE_LOCAL_Reset <= not EARLY_LOCAL_STG and READ_CALL_TO_MEM; -USE_LOCAL: FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2 +USE_LOCAL: entity FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2 USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM; USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2 @@ -143,38 +143,38 @@ TD1_680 <= TD1(34); -- 680ns TD1_700 <= TD1(35); -- 700ns nRD_OR_WR_SET1 <= not RD_OR_WR_SET1; -RD_OR_WR_RST1_FL: FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1); +RD_OR_WR_RST1_FL: entity FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1); RD_OR_WR_SET1_RESET <= RD_OR_WR_RST1 or MACH_RST_SW; -- The delay is to prevent a combinatorial loop: Delay_RD_OR_WR_SET1_RESET: AR port map (D=>RD_OR_WR_SET1_RESET, clk=>Clk, Q=>dRD_OR_WR_SET1_RESET); -RD_OR_WR_SET1_FL: FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1); +RD_OR_WR_SET1_FL: entity FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1); TD1IN <= not RD_OR_WR_RST1 and RD_OR_WR_SET1; -- READ CLOCK 0 READ_ECHO_1_SET <= TD1_150 and SET_READ_LCHS1; READ_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and RD_RST_CTRL1); -READ_ECHO_1_FL: FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns +READ_ECHO_1_FL: entity FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns -- READ CLOCK 4 DATA_READY1_SET <= TD1_560 and SET_READ_LCHS1; DATA_READY1_RESET <= MACH_RST_SW or (TD1_660 and RD_RST_CTRL1); -DATA_READY1_FL: FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns +DATA_READY1_FL: entity FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns DATA_READY_1 <= sDATA_READY_1; -- READ CLOCK 5 READ_RST_SET1 <= TD1_500 and SET_READ_LCHS1; READ_RST_RESET1 <= MACH_RST_SW or TD1_700; -READ_RST1_FL: FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns +READ_RST1_FL: entity FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns -- WRITE CLOCK 0 WRITE_ECHO_1_SET <= TD1_150 and not SET_READ_LCHS1; WRITE_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and WR_RST_CTRL1); -WRITE_ECHO_1_FL: FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns +WRITE_ECHO_1_FL: entity FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns -- WRITE CLOCK 4 SET_READ_LCHS1_RESET <= MACH_RST_SW or WRITE_CALL_TO_MEM; -- ?? -SET_READ_LCHS1_FL: FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL +SET_READ_LCHS1_FL: entity FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL -- WRITE CLOCK 5 WRITE_RST_SET1 <= TD1_500 and not SET_READ_LCHS1; WRITE_RST_RESET1 <= MACH_RST_SW or TD1_150; -- 150ns or 1050ns or 1500ns? -WRITE_RST1_FL: FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns?? +WRITE_RST1_FL: entity FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns?? -- Second 32K READ_ECHO_2 <= '0'; diff --git a/FMD2030_5-06A-B.vhd b/FMD2030_5-06A-B.vhd index 6139a41..2b67ca2 100644 --- a/FMD2030_5-06A-B.vhd +++ b/FMD2030_5-06A-B.vhd @@ -43,6 +43,8 @@ USE ieee.std_logic_unsigned.all; library work; use work.Gates_package.all; use work.Buses_package.all; +use work.PH; +use work.FLL; ENTITY ABALU IS port @@ -149,16 +151,16 @@ B_REG_PC <= EvenParity(B_REG); -- AB2J2 -- IMMED STAT REG SI_LCH_Set <= SERV_IN_SIG and not T_REQUEST; -SI_LCH: PH port map(SI_LCH_Set,T3,SERV_IN_LCHD); -- AB2D6 +SI_LCH: entity PH port map(SI_LCH_Set,T3,SERV_IN_LCHD); -- AB2D6 STI_LCH_Set <= STAT_IN_SIG and not T_REQUEST; -STI_LCH: PH port map(STI_LCH_Set,T3,STATUS_IN_LCHD); -- AB2D6 -OI_LCH: PH port map(OPNL_IN,T3,OPNL_IN_LCHD); -- AB2D6 -AI_LCH: PH port map(ADDR_IN,T3,ADDR_IN_LCHD); -- AB2D6 +STI_LCH: entity PH port map(STI_LCH_Set,T3,STATUS_IN_LCHD); -- AB2D6 +OI_LCH: entity PH port map(OPNL_IN,T3,OPNL_IN_LCHD); -- AB2D6 +AI_LCH: entity PH port map(ADDR_IN,T3,ADDR_IN_LCHD); -- AB2D6 Z0C1C0_LCH <= T4 or RECYCLE_RST; -Z0_LCH: PH port map(sZ_0,Z0C1C0_LCH,Z0_BUS_0); -- AB2D6 -C1_LCH: PH port map(P_CARRY(1),Z0C1C0_LCH,CARRY_1_LCHD); -- AB2D6 -C0_LCH: PH port map(P_CARRY(0),Z0C1C0_LCH,sCARRY_0_LATCHED); -- AB2D6 +Z0_LCH: entity PH port map(sZ_0,Z0C1C0_LCH,Z0_BUS_0); -- AB2D6 +C1_LCH: entity PH port map(P_CARRY(1),Z0C1C0_LCH,CARRY_1_LCHD); -- AB2D6 +C0_LCH: entity PH port map(P_CARRY(0),Z0C1C0_LCH,sCARRY_0_LATCHED); -- AB2D6 CARRY_0_LATCHED <= sCARRY_0_LATCHED; -- ALU INDICATORS @@ -171,9 +173,9 @@ INSERT_0_CARRY <= '1' when (CC="000") or (CC="010") or (CC="011") or (CC="100") PC7_LCH_Set <= (S_REG_3 and CARRY_S3 and P1) or (P1 and INSERT_CARRY); PC7_LCH_Reset <= MANUAL_STORE or T1 or RECYCLE_RST; -PC7_LCH: FLL port map(PC7_LCH_Set,PC7_LCH_Reset,P_CARRY_IN_7); -- AB2F3,AB2E4 +PC7_LCH: entity FLL port map(PC7_LCH_Set,PC7_LCH_Reset,P_CARRY_IN_7); -- AB2F3,AB2E4 NC7_LCH_Set <= (NOT_S3 and CARRY_S3 and P1) or (P1 and INSERT_0_CARRY) or RECYCLE_RST or MANUAL_STORE; -NC7_LCH: FLL port map(NC7_LCH_Set,T1,N_CARRY_IN_7); -- AB2F3,AB2E4 +NC7_LCH: entity FLL port map(NC7_LCH_Set,T1,N_CARRY_IN_7); -- AB2F3,AB2E4 -- ALU CHECK sALU_CHK <= '1' when (P_Z_ALU_BUS xor N_Z_ALU_BUS)/="11111111" or (P_SUMS(0) = N_SUMS(0)) or (P_SUMS(4) = N_SUMS(4)) or (P_CARRY(0) = N_CARRY(0)) else '0'; -- AB2D3,AB2D4,AB2E4 @@ -334,13 +336,13 @@ MACH_RST_2C <= sMACH_RST_2A; DIAG_TEST_BIT <= '1' when SALS.SALS_CK="1000" and SALS.SALS_AK='1' else '0'; -- AB3E7 EVEN_LCH_Set <= T2 and DIAG_TEST_BIT and not sALU_CHK_LCH; EVEN_LCH_Reset <= (T2 and sALU_CHK_LCH) or RST_LOAD or SYSTEM_RST_PRIORITY_LCH or RECYCLE_RST; -- ?? *not* SYSTEM_RST_PRIORITY_LCH ?? -EVEN_LCH: FLL port map(EVEN_LCH_Set,EVEN_LCH_Reset,EVEN); -- AB3E5,AB3G2 +EVEN_LCH: entity FLL port map(EVEN_LCH_Set,EVEN_LCH_Reset,EVEN); -- AB3E5,AB3G2 sODD <= not EVEN; ODD <= sODD; AC_LCH_Set <= EVEN and DIAG_TEST_BIT and T1; AC_LCH_Reset <= RECYCLE_RST or RST_LOAD or (ROS_SCAN and GT_SWS_TO_WX_PWR); -AC_LCH: FLL port map(AC_LCH_Set,AC_LCH_Reset,sALU_CHK_LCH); -- AG3G7,AB3G2 +AC_LCH: entity FLL port map(AC_LCH_Set,AC_LCH_Reset,sALU_CHK_LCH); -- AG3G7,AB3G2 ALU_CHK_LCH <= sALU_CHK_LCH; -- Debug diff --git a/FMD2030_5-06C-D.vhd b/FMD2030_5-06C-D.vhd index 516a542..dde8b0e 100644 --- a/FMD2030_5-06C-D.vhd +++ b/FMD2030_5-06C-D.vhd @@ -43,6 +43,7 @@ USE ieee.numeric_std.all; library work; use work.Gates_package.all; use work.Buses_package.all; +use work.FLL; ENTITY RREG_STG IS port @@ -255,10 +256,10 @@ BEGIN -- Fig 5-06C SX2_STOR_INPUT_DATA_Set <= SX2_RD_CYCLE and SEL_T3; SX2_STOR_INPUT_DATA_Reset <= (GT_DETECTORS_TO_HR and SEL_DATA_READY) or (not SEL_R_W_CTRL and not SX2_WR_CYCLE); -SX2_STOR_INPUT_DATA: FLL port map(SX2_STOR_INPUT_DATA_Set,SX2_STOR_INPUT_DATA_Reset,SX2_STOR); -- AE1G3,AE1L3 +SX2_STOR_INPUT_DATA: entity FLL port map(SX2_STOR_INPUT_DATA_Set,SX2_STOR_INPUT_DATA_Reset,SX2_STOR); -- AE1G3,AE1L3 SX1_STOR_INPUT_DATA_Set <= SX1_RD_CYCLE and SEL_T3; SX1_STOR_INPUT_DATA_Reset <= (GT_DETECTORS_TO_GR and SEL_DATA_READY) or (not SEL_R_W_CTRL and not SX1_WR_CYCLE); -SX1_STOR_INPUT_DATA: FLL port map(SX1_STOR_INPUT_DATA_Set,SX1_STOR_INPUT_DATA_Reset,SX1_STOR); -- AD2E4,AD2G4 +SX1_STOR_INPUT_DATA: entity FLL port map(SX1_STOR_INPUT_DATA_Set,SX1_STOR_INPUT_DATA_Reset,SX1_STOR); -- AD2E4,AD2G4 INPUT_CORRECTED_P_BIT <= (SX2_STOR and EVEN_HR_0_7_BITS) or (SX1_STOR and EVEN_GR_0_7_BITS) or DR_CORR_P_BIT; -- AD2G4,AA1E7 HRP <= not SX2_STOR and HR_REG_P_BIT and STORE_HR; -- AA1F7 @@ -290,7 +291,7 @@ ALLOW_PROTECT <= sALLOW_PROTECT; PROT_MEM_Set <= MN_REG_CHK_SMPLD or (T2 and MEM_WRAP and MAIN_STG); PROT_MEM_Reset <= MACH_RST_6 or (not ALLOW_WRITE and T4); -PROT_MEM: FLL port map(PROT_MEM_Set,PROT_MEM_Reset,PROTECT_MEMORY); -- AB3F5,AB3H6 +PROT_MEM: entity FLL port map(PROT_MEM_Set,PROT_MEM_Reset,PROTECT_MEMORY); -- AB3F5,AB3H6 -- If we have a protection violation, we must retain the location's value in R so that it can be written back, even if -- R contained a new value destined for that location @@ -315,10 +316,10 @@ R_MUX(8) <= (FORCE_Z_SET_R2 and N_Z_BUS(8)) or (GT_HSMPX_INTO_R_REG and HSMPX_BU -- Word Mark detection for 1401 usage DET0F <= '1' when (STORAGE_BUS(1 to 7) = "0001111") and (DATA_READY='1') else '0'; -- AA1B7 -GMWM: FLL port map(DET0F,CPU_SET_ALLOW_WR_LCH,GMWM_DETECTED); -- AA1F5 +GMWM: entity FLL port map(DET0F,CPU_SET_ALLOW_WR_LCH,GMWM_DETECTED); -- AA1F5 P_8F_DETECT_Set <= STORAGE_BUS(0) and MAIN_STG and N1401_MODE and DET0F; P_8F_DETECT_Reset <= MACH_RST_SW or GMWM_DETECTED; -P_8F_DETECT: FLL port map(P_8F_DETECT_Set,P_8F_DETECT_Reset,P_8F_DETECTED); -- AA1F5 +P_8F_DETECT: entity FLL port map(P_8F_DETECT_Set,P_8F_DETECT_Reset,P_8F_DETECTED); -- AA1F5 StorageOut.WriteData <= sSTORE_BITS; StorageOut.MainStorage <= USE_MAIN_MEM; diff --git a/FMD2030_5-07A2.vhd b/FMD2030_5-07A2.vhd index a5937b7..f1892ba 100644 --- a/FMD2030_5-07A2.vhd +++ b/FMD2030_5-07A2.vhd @@ -133,10 +133,10 @@ ALLW_A_REG_CHK_Set <= (P1 and USE_BASIC_CA_DECO and not GT_CA_TO_W_REG and CAX1X (CAX11X and not GT_CA_TO_W_REG and USE_BASIC_CA_DECO and P1) or -- AB3F3 (USE_BASIC_CA_DECO and CA1XXX and P1); -- AB3K5 ALLW_A_REG_CHK_Reset <= T1 or ROS_SCAN or sSUPPR_A_REG_CHK or ANY_PRIORITY_LCH; -ALLW_A_REG_CHK: FLL port map(ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,ALLOW_A_REG_CHK); -- AB3K5,AB3B6,AB3J4 +ALLW_A_REG_CHK: entity FLL port map(ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,ALLOW_A_REG_CHK); -- AB3K5,AB3B6,AB3J4 NOT_ALLOW_PC_SALS_Set <= (SET_IND_ROSAR and T4) or MACH_RST_6; -NOT_ALLOW_PC_SALS: FLL port map(NOT_ALLOW_PC_SALS_Set,not T3,N_ALLOW_PC_SALS); -- AB3F6,AB3D7,AB3E5 +NOT_ALLOW_PC_SALS: entity FLL port map(NOT_ALLOW_PC_SALS_Set,not T3,N_ALLOW_PC_SALS); -- AB3F6,AB3D7,AB3E5 sALLOW_PC_SALS <= not N_ALLOW_PC_SALS; ALLOW_PC_SALS <= sALLOW_PC_SALS; diff --git a/FMD2030_5-07B1.vhd b/FMD2030_5-07B1.vhd index 94f72ee..6c533ec 100644 --- a/FMD2030_5-07B1.vhd +++ b/FMD2030_5-07B1.vhd @@ -43,6 +43,7 @@ USE ieee.std_logic_unsigned.all; library work; use work.Gates_package.all; use work.Buses_package.all; +use work.PH; ENTITY SARSA IS port @@ -88,20 +89,20 @@ sMACH_RST_PROTECT <= MACH_RST_SW; -- AA3H3 MACH_RST_PROTECT <= sMACH_RST_PROTECT; LATCH_MN <= MACH_RESET_SET_LCH_DLY or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1D4 LATCH_MN_ST3 <= sMACH_RST_PROTECT or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1E4 -REG_M: PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN,sMN(0 to 7)); -- AA1D2 -REG_MP: PH port map(M_ASSM_BUS(8),LATCH_MN,M_P); -- AA1D2 -REG_N: PHV8 port map(N_ASSM_BUS(0 to 7),LATCH_MN,sMN(8 to 15) ); -- AA1D3 -REG_NP: PH port map(N_ASSM_BUS(8),LATCH_MN,N_P); -- AA1D3 -REG_MST3: PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN_ST3,MN_ST3(0 to 7)); -- AA1D5 -REG_MST3P: PH port map(M_ASSM_BUS(8),LATCH_MN_ST3,M_ST3_P); -- AA1D5 -REG_NST3: PHV8 port map(N_ASSM_BUS(0 TO 7),LATCH_MN_ST3,MN_ST3(8 to 15)); -- AA1D6 -REG_NST3P: PH port map(N_ASSM_BUS(8),LATCH_MN_ST3,N_ST3_P); -- AA1D6 +REG_M: entity PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN,sMN(0 to 7)); -- AA1D2 +REG_MP: entity PH port map(M_ASSM_BUS(8),LATCH_MN,M_P); -- AA1D2 +REG_N: entity PHV8 port map(N_ASSM_BUS(0 to 7),LATCH_MN,sMN(8 to 15) ); -- AA1D3 +REG_NP: entity PH port map(N_ASSM_BUS(8),LATCH_MN,N_P); -- AA1D3 +REG_MST3: entity PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN_ST3,MN_ST3(0 to 7)); -- AA1D5 +REG_MST3P: entity PH port map(M_ASSM_BUS(8),LATCH_MN_ST3,M_ST3_P); -- AA1D5 +REG_NST3: entity PHV8 port map(N_ASSM_BUS(0 TO 7),LATCH_MN_ST3,MN_ST3(8 to 15)); -- AA1D6 +REG_NST3P: entity PH port map(N_ASSM_BUS(8),LATCH_MN_ST3,N_ST3_P); -- AA1D6 STACK_ADDR_REG_SET <= CHNL_RD_CALL or (CPU_RD_PWR and T1) or GT_MAN_SET_MN or sMACH_RST_PROTECT; -- BE3H7 SA_REG_IN1 <= "111" & M_ASSM_BUS(0 to 4) when MAIN_STORAGE_CP='1' else "00000000"; -- PE3J6 SA_REG_IN2 <= XXH & XL & XH & N_ASSM_BUS(0 to 4) when MPX_CP='1' else "00000000"; -- PE3J6 SA_REG_IN <= SA_REG_IN1 or SA_REG_IN2; -- PE3J6 -REG_SA: PHV8 port map(SA_REG_IN,STACK_ADDR_REG_SET,SA_REG); -- PE3J6 +REG_SA: entity PHV8 port map(SA_REG_IN,STACK_ADDR_REG_SET,SA_REG); -- PE3J6 MN <= sMN; EARLY_M0 <= M_ASSM_BUS(0); diff --git a/FMD2030_5-07B2.vhd b/FMD2030_5-07B2.vhd index 006ad42..d4ceac9 100644 --- a/FMD2030_5-07B2.vhd +++ b/FMD2030_5-07B2.vhd @@ -99,7 +99,7 @@ CS_1XXX <= '1' when CS(0)='1' else '0'; GT_CS_OPT_Set <= SA and P1; GT_CS_OPT_Reset <= CTRL_REG_RST or T1; -- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5 -GT_CS_OPT: FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5 +GT_CS_OPT: entity FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5 GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5 BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)" sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)" diff --git a/FMD2030_5-08B.vhd b/FMD2030_5-08B.vhd index 8c592d2..1ca49ca 100644 --- a/FMD2030_5-08B.vhd +++ b/FMD2030_5-08B.vhd @@ -40,7 +40,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -USE work.Gates_package.all; +USE work.Gates_package.all; +use work.PH; entity QReg_STP is Port ( @@ -110,8 +111,8 @@ PROTECT_LOC_CPU_OR_MPX <= (not H_REG_5_PWR) and STP and (sSTACK_PC or not HDWR_S PROTECT_LOC_SEL_CHNL <= STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2 INH_STG_PROT_PH_D <= GT_T_REG_TO_MN or GT_CK_TO_MN; -INH_STG_PROT_PH: PH port map(INH_STG_PROT_PH_D,GT_LOCAL_STORAGE,INH_STG_PROT); -- AA1F4 -SEL_CPU_BUMP_PH: PH port map(FORCE_M_REG_123,GT_LOCAL_STORAGE,SEL_CPU_BUMP); -- AA1F4 +INH_STG_PROT_PH: entity PH port map(INH_STG_PROT_PH_D,GT_LOCAL_STORAGE,INH_STG_PROT); -- AA1F4 +SEL_CPU_BUMP_PH: entity PH port map(FORCE_M_REG_123,GT_LOCAL_STORAGE,SEL_CPU_BUMP); -- AA1F4 STACK_PC <= sSTACK_PC; MPX_CP <= not MAIN_STG_CP_1; -- BE3D3 BE3G4 diff --git a/FMD2030_5-08C.vhd b/FMD2030_5-08C.vhd index 78bd943..2b291f6 100644 --- a/FMD2030_5-08C.vhd +++ b/FMD2030_5-08C.vhd @@ -40,6 +40,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; +use work.PH; +use work.FLVL; entity MpxFOFB is Port ( MPX_ROS_LCH : in STD_LOGIC; diff --git a/FMD2030_5-08D.vhd b/FMD2030_5-08D.vhd index 3d01de9..25de232 100644 --- a/FMD2030_5-08D.vhd +++ b/FMD2030_5-08D.vhd @@ -41,7 +41,8 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE work.Gates_package.all; -USE work.Buses_package.all; +USE work.Buses_package.all; +USE work.FLL; entity MpxFA is Port ( BUS_O_REG : in STD_LOGIC_VECTOR (0 to 8); @@ -117,6 +118,7 @@ signal SetStartSelO, ResetStartSelO, StartSelO : STD_LOGIC; signal NO_1050_SEL_O : STD_LOGIC; signal SetSelReq, ResetSelReq, SetSelOInlk, SelOInlk : STD_LOGIC; signal SS_RECYCLE_RST : STD_LOGIC; +signal NOT_OPL_IN : STD_LOGIC; begin STATUS_IN <= sTAGS_IN.STA_IN; @@ -200,7 +202,8 @@ SEL_REQ: entity FLL port map (S=>SetSelReq, R=>ResetSelReq, Q=>sN1050_SEL_OUT); P_1050_SEL_OUT <= sN1050_SEL_OUT; SetSelOInlk <= (sTAGS_IN.ADR_IN and sTAGS_IN.OPL_IN) or (N1050_OP_IN and not N1050_CE_MODE); -- AA3B7 -SEL_O_INLK: entity FLL port map (S=>SetSelOInlk, R=>not sTAGS_IN.OPL_IN, Q=>SelOInlk); -- AA3C7 +NOT_OPL_IN <= not sTAGS_IN.OPL_IN; +SEL_O_INLK: entity FLL port map (S=>SetSelOInlk, R=>NOT_OPL_IN, Q=>SelOInlk); -- AA3C7 -- sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) or not LOAD_IND or SUPPR_CTRL_LCH; -- AA3C7 AA3E5 sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) and not LOAD_IND and SUPPR_CTRL_LCH; -- AA3C7 AA3E5 ?? AA3C7 shown as 'OR' SUPPR_O <= sSUPPR_O; diff --git a/FMD2030_5-09C.vhd b/FMD2030_5-09C.vhd index 091accd..803a219 100644 --- a/FMD2030_5-09C.vhd +++ b/FMD2030_5-09C.vhd @@ -42,6 +42,7 @@ USE ieee.std_logic_unsigned.all; library work; use work.Gates_package.all; use work.Buses_package.all; +use work.FLL; ENTITY n1050_TRANSLATE IS port @@ -132,11 +133,11 @@ DataRegSpecial <= '0'; -- Ignore for now XLATE_UC_SET <= UPPER_CASE_DECODE and X_TIME; -- AC3F2 XLATE_UC_RESET <= SET_LOWER_CASE or (X_TIME and LOWER_CASE_DECODE); -- AC3F2 -XLATE_UC_FL: FLL port map (S=>XLATE_UC_SET, R=>XLATE_UC_RESET, Q=>XLATE_UC); -- ????? +XLATE_UC_FL: entity FLL port map (S=>XLATE_UC_SET, R=>XLATE_UC_RESET, Q=>XLATE_UC); -- ????? RD_SHARE_REQ_SET <= not DataRegSpecial and not UPPER_CASE_DECODE and not LOWER_CASE_DECODE and sRD_OR_RD_INQ and Y_TIME; RD_SHARE_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH or (CE_RUN_MODE and CE_TI_DECODE); -RD_SHARE_REQ_FL: FLL port map(S=>RD_SHARE_REQ_SET, R=>RD_SHARE_REQ_RESET, Q=>sRD_SHARE_REQ_LCH); -- AC3F5 AC3C7 +RD_SHARE_REQ_FL: entity FLL port map(S=>RD_SHARE_REQ_SET, R=>RD_SHARE_REQ_RESET, Q=>sRD_SHARE_REQ_LCH); -- AC3F5 AC3C7 RD_SHARE_REQ_LCH <= sRD_SHARE_REQ_LCH; READ_SHARE_REQ <= sRD_SHARE_REQ_LCH and not Y_TIME; -- AC3E3 @@ -152,10 +153,10 @@ PCH_1_HOME <= PUNCH_1_CLUTCH_1050 or sREAD or sREAD_INQ; -- AC2G3 -- Prefix is 0x100111 i.e. 27 or 67 PREFIX_SET <= not DATA_REG_BUS(0) and DATA_REG_BUS(2) and not DATA_REG_BUS(3) and not DATA_REG_BUS(4) and DATA_REG_BUS(5) and DATA_REG_BUS(6) and DATA_REG_BUS(7) and Z_TIME; -- AC3B7 AC3F2 AC3D6 -PREFIX_FL: FLL port map(S=>PREFIX_SET,R=>Y_TIME,Q=>PREFIX); -- AC3F2 AC3G5 +PREFIX_FL: entity FLL port map(S=>PREFIX_SET,R=>Y_TIME,Q=>PREFIX); -- AC3F2 AC3G5 -- Block Shift prevents the shift mechanism from being triggered BLOCK_SHIFT_SET <= PREFIX and X_TIME; -BLOCK_SHIFT_FL: FLL port map(S=>BLOCK_SHIFT_SET,R=>W_TIME,Q=>BLOCK_SHIFT); -- AC3F2 AC3C6 +BLOCK_SHIFT_FL: entity FLL port map(S=>BLOCK_SHIFT_SET,R=>W_TIME,Q=>BLOCK_SHIFT); -- AC3F2 AC3C6 DataReg01xxxxxx <= not DATA_REG_BUS(0) and DATA_REG_BUS(1); -- AC3D5 AC3B4 DataRegLCA <= not DATA_REG_BUS(5) and DATA_REG_BUS(7) and DataReg01xxxxxx; -- 01xxx0x1 = 01xx0001 "/" 01xx0011 01xx1001 01xx1011 ".$,#" @@ -174,7 +175,7 @@ UC_CHARACTER <= sUC_CHARACTER; -- PRT_IN_UC remembers whether the printer is already in UC mode PRT_IN_UC_SET <= sUC_CHARACTER and Z_TIME and ALLOW_STROBE; PRT_IN_UC_RESET <= (sLC_CHARACTER and Z_TIME and ALLOW_STROBE) or SET_LOWER_CASE; -- AC3F4 -PRINT_IN_UC_FL: FLL port map(S=>PRT_IN_UC_SET,R=>PRT_IN_UC_RESET,Q=>PRT_IN_UC); -- ????? +PRINT_IN_UC_FL: entity FLL port map(S=>PRT_IN_UC_SET,R=>PRT_IN_UC_RESET,Q=>PRT_IN_UC); -- ????? WRITE_UC <= PRT_IN_UC; -- For now the SHIFT function is disabled as it is not required for ASCII output -- SET_SHIFT_LCH <= not ((PRT_IN_UC and sLC_CHARACTER and sWRITE_LCH) or (sUC_CHARACTER and sWRITE_LCH and not PRT_IN_UC)); -- AC2E5 AC3D4 @@ -182,7 +183,7 @@ SET_SHIFT_LCH <= '0'; WRITE_SET <= not RDR_ON_LCH and not PUNCH_1_CLUTCH_1050 and HOME_RDR_STT_LCH; -- AC2G7 WRITE_RESET <= CLOCK_STT_RST or RST_ATTACH; -WRITE_FL : FLL port map(S=>WRITE_SET,R=>WRITE_RESET,Q=>sWRITE_LCH); -- AC2J5 AC2H6 +WRITE_FL : entity FLL port map(S=>WRITE_SET,R=>WRITE_RESET,Q=>sWRITE_LCH); -- AC2J5 AC2H6 WRITE_LCH <= sWRITE_LCH; WRITE_LCH_RST <= sWRITE_LCH; WRITE_MODE <= WRITE_SET and not n1050_RST; -- AC2D7 diff --git a/FMD2030_5-10A.vhd b/FMD2030_5-10A.vhd index 3a932f9..5ba25c3 100644 --- a/FMD2030_5-10A.vhd +++ b/FMD2030_5-10A.vhd @@ -43,6 +43,7 @@ USE ieee.std_logic_unsigned.all; library work; use work.Gates_package.all; use work.Buses_package.all; +use work.FLL; ENTITY n1050_CLOCK IS port @@ -95,7 +96,7 @@ BEGIN CLK_START_SET <= (PUNCH_1_CLUTCH and not READ_CLK_INTLK_LCH and READ_OR_READ_INQ) or (RDR_1_CLUTCH and WRITE_LCH and not CRLF); CLK_START_RESET <= RST_ATTACH or sCLK_STT_RST; - CLK_START_FL : FLL port map(CLK_START_SET,CLK_START_RESET,CLK_START); -- AC2G6 AC2F6 + CLK_START_FL : entity FLL port map(CLK_START_SET,CLK_START_RESET,CLK_START); -- AC2G6 AC2F6 BIN_CNTR_P: process(OSC,RST_ATTACH) is begin @@ -157,7 +158,7 @@ BEGIN -- Z_FL : FLL port map(Z_SET,Z_RESET,sZ_TIME); -- AC2F5 Z_TIME <= sZ_TIME; - CLOCK1_FL : FLL port map(W_SET,X_RESET,CLOCK_1); -- ?? CLOCK_1 isn't defined in the diagrams + CLOCK1_FL : entity FLL port map(W_SET,X_RESET,CLOCK_1); -- ?? CLOCK_1 isn't defined in the diagrams -- This is a guess at CLOCK_1 being W_TIME OR X_TIME, but can't do that directly without possible glitches END FMD; diff --git a/FMD2030_5-10B.vhd b/FMD2030_5-10B.vhd index 961de93..063ba61 100644 --- a/FMD2030_5-10B.vhd +++ b/FMD2030_5-10B.vhd @@ -41,6 +41,7 @@ USE ieee.std_logic_unsigned.all; library work; use work.Gates_package.all; use work.Buses_package.all; +use work.FLL; ENTITY n1050_TAGS IS port @@ -160,11 +161,11 @@ signal sRESTORE : STD_LOGIC; BEGIN -- Fig 5-10B RD_CLK_INLK_SET <= RD_OR_RD_INQ and Y_TIME; -- AC3E3 -RD_CLK_INLK: FLL port map(RD_CLK_INLK_SET,RD_INLK_RST,sRD_CLK_INLK_LCH); -- AC3E3, AC3F2 +RD_CLK_INLK: entity FLL port map(RD_CLK_INLK_SET,RD_INLK_RST,sRD_CLK_INLK_LCH); -- AC3E3, AC3F2 RD_CLK_INLK_LCH <= sRD_CLK_INLK_LCH; n1050_RST_RESET <= not sRD_CLK_INLK_LCH and not WRITE_LCH_RST; -- AC2J5 n1050_RST_SET <= TAGS_OUT_BUS(7) and sTA_REG_SET; -- AC2K5 -n1050_RST : FLL port map(n1050_RST_SET, n1050_RST_RESET, s1050_RST_LCH); -- AC2K5 AC2E2 +n1050_RST : entity FLL port map(n1050_RST_SET, n1050_RST_RESET, s1050_RST_LCH); -- AC2K5 AC2E2 n1050_RST_LCH <= s1050_RST_LCH; CPU_LINES_TO_1050.n1050_RST_LCH <= s1050_RST_LCH; CPU_LINES_TO_1050.n1050_RESET <= ((((sRD_CLK_INLK_LCH and not PCH_1_CLUTCH) or (WRITE_LCH and Z_TIME)) and s1050_RST_LCH) or sRST_ATTACH) and TT3_POS_1050_OPER; -- AC2H4 AC2G3 AC2K3 AC2K6 @@ -178,24 +179,24 @@ CPU_LINES_TO_1050.RESTORE <= sRESTORE; RESTORE <= sRESTORE; SET_HOME_RDR_STT <= TAGS_OUT_BUS(0) and sTA_REG_SET; -HOME_RDR_STT_FL: FLL port map(SET_HOME_RDR_STT,TA_REG_RST,sHOME_RDR_START_LCH); -- AC2H3 AC2K4 +HOME_RDR_STT_FL: entity FLL port map(SET_HOME_RDR_STT,TA_REG_RST,sHOME_RDR_START_LCH); -- AC2H3 AC2K4 HOME_RDR_START_LCH <= sHOME_RDR_START_LCH; CPU_LINES_TO_1050.HOME_RDR_START <= sHOME_RDR_START_LCH and TT3_POS_1050_OPER and not sPROCEED_LCH; -- AC2L6 HOME_RDR_STOP <= TT3_POS_1050_OPER and not RUN; -- AC2K6 SET_PROCEED <= TAGS_OUT_BUS(3) and sTA_REG_SET; -PROCEED_FL: FLL port map(SET_PROCEED,TA_REG_RST,sPROCEED_LCH); -- AC2D6 AC2K7 +PROCEED_FL: entity FLL port map(SET_PROCEED,TA_REG_RST,sPROCEED_LCH); -- AC2D6 AC2K7 PROCEED_LCH <= sPROCEED_LCH; CPU_LINES_TO_1050.PROCEED <= sPROCEED_LCH and not RD_SHARE_REQ_LCH and not MICRO_SHARE_REQ; -- AC2K6 MICRO_SHARE_REQ <= (not SUPPRESS_OUT and sMICRO_SHARE_LCH) or (sPROCEED_LCH and sMICRO_SHARE_LCH); -- AC2K7 SET_MICRO_SHARE <= TAGS_OUT_BUS(2) and sTA_REG_SET; -MICRO_SHARE_FL: FLL port map(SET_MICRO_SHARE,TA_REG_RST,sMICRO_SHARE_LCH); -- AC2H3 AC2K4 +MICRO_SHARE_FL: entity FLL port map(SET_MICRO_SHARE,TA_REG_RST,sMICRO_SHARE_LCH); -- AC2H3 AC2K4 MICRO_SHARE_LCH <= sMICRO_SHARE_LCH; SET_RDR_2 <= TAGS_OUT_BUS(1) and sTA_REG_SET; -RDR_2_FL: FLL port map(SET_RDR_2,TA_REG_RST,sRDR_ON_LCH); -- AC2H3 AC2K4 +RDR_2_FL: entity FLL port map(SET_RDR_2,TA_REG_RST,sRDR_ON_LCH); -- AC2H3 AC2K4 RDR_ON_LCH <= sRDR_ON_LCH; CPU_LINES_TO_1050.RDR_2_HOLD <= ((sRDR_ON_LCH or not RD_SHARE_REQ) and TT3_POS_1050_OPER) -- AC2J5 AC2K6 @@ -219,19 +220,19 @@ n1050_SEL_IN <= not P_1050_SEL_OUT or (n1050_CE_MODE and not sn1050_OP_IN) or (C SET_SEL_O_DET <= T1 and CPU_SEL_O_OR_SEL_IN; RESET_SEL_O_DET <= not CPU_SEL_O_OR_SEL_IN or sRST_ATTACH; -SEL_O_DET_FL: FLL port map(SET_SEL_O_DET,RESET_SEL_O_DET,SEL_O_DET); -- AC3E6 +SEL_O_DET_FL: entity FLL port map(SET_SEL_O_DET,RESET_SEL_O_DET,SEL_O_DET); -- AC3E6 SET_SEL_O_DLY <= T3 and SEL_O_DET and not sn1050_OP_IN; RESET_SEL_O_DLY <= sRST_ATTACH or not CPU_SEL_O_OR_SEL_IN; -SEL_O_DLY_FL: FLL port map(SET_SEL_O_DLY,RESET_SEL_O_DLY,SEL_O_DLY); -- AC3E6 +SEL_O_DLY_FL: entity FLL port map(SET_SEL_O_DLY,RESET_SEL_O_DLY,SEL_O_DLY); -- AC3E6 SET_1050_OP_IN <= (CPU_SEL_O_OR_SEL_IN and PREPARE_TO_SHARE) or (n1050_CE_MODE and PREPARE_TO_SHARE); RESET_1050_OP_IN <= MPX_LCH_OFF or sRST_ATTACH; -- ?? -n1050_OP_IN_FL: FLL port map(SET_1050_OP_IN,RESET_1050_OP_IN,sn1050_OP_IN); +n1050_OP_IN_FL: entity FLL port map(SET_1050_OP_IN,RESET_1050_OP_IN,sn1050_OP_IN); n1050_OP_IN <= sn1050_OP_IN; SET_1050_EXIT_SHARE_REQ <= MPX_OPN_LCH_GT and not CK_SAL_P_BIT; -- AC3C7 -n1050_EXIT_SHARE_REQ_FL : FLL port map(SET_1050_EXIT_SHARE_REQ,T1,n1050_EXIT_SHARE_REQ); -- AC3C6 AC3E4 +n1050_EXIT_SHARE_REQ_FL : entity FLL port map(SET_1050_EXIT_SHARE_REQ,T1,n1050_EXIT_SHARE_REQ); -- AC3C6 AC3E4 SHARE_REQ_RST <= (n1050_EXIT_SHARE_REQ and not n1050_CE_MODE and T4) or EXIT_MPLX_SHARE; -- AC3E4 MPX_LCH_OFF <= EXIT_MPLX_SHARE or (n1050_EXIT_SHARE_REQ and not n1050_CE_MODE and T4); -- AC3E4 @@ -246,7 +247,7 @@ CPU_REQUEST_IN <= sCPU_REQUEST_IN; SET_PREPARE_TO_SHARE <= (not CPU_SEL_O_OR_SEL_IN and n1050_CE_MODE and not ADDR_OUT and sCPU_REQUEST_IN) or (sCPU_REQUEST_IN and CE_SEL_O); -- AC3C7 AC3E2 RESET_PREPARE_TO_SHARE <= not sCPU_REQUEST_IN or sRST_ATTACH; -PREPARE_TO_SHARE_FL: FLL port map(SET_PREPARE_TO_SHARE,RESET_PREPARE_TO_SHARE,PREPARE_TO_SHARE); -- AC3E6 +PREPARE_TO_SHARE_FL: entity FLL port map(SET_PREPARE_TO_SHARE,RESET_PREPARE_TO_SHARE,PREPARE_TO_SHARE); -- AC3E6 n1050_REQ_IN <= sCPU_REQUEST_IN and not n1050_CE_MODE; @@ -255,7 +256,7 @@ SS20_IN <= TT3_POS_1050_OPER and REQUEST_KEY; -- AC3D6 SS20_SS: SS port map(Clock1ms,20,SS20_IN,SS20); -- 20ms single-shot AC3G6 SET_ATTN_INTLK <= RESET_ATTN or sTT6_POS_ATTN; RESET_ATTN_INTLK <= SS20 and REQUEST_KEY; -- AC3B6 AC3C7 - Typo, AC3C7 should be N? -ATTN_INTLK_FL: FLL port map(SET_ATTN_INTLK,RESET_ATTN_INTLK,ATTN_INTLK); -- AC3C6 AC3D6 - ?? Not sure about this +ATTN_INTLK_FL: entity FLL port map(SET_ATTN_INTLK,RESET_ATTN_INTLK,ATTN_INTLK); -- AC3C6 AC3D6 - ?? Not sure about this SET_ATTN <= ATTN_INTLK and RESET_ATTN_INTLK; -- ATTN_FL: FLL port map(SET_ATTN,RESET_ATTN,sTT6_POS_ATTN); -- AC3C6 AC3C7 diff --git a/FMD2030_5-10C.vhd b/FMD2030_5-10C.vhd index b1c6f70..38b8d48 100644 --- a/FMD2030_5-10C.vhd +++ b/FMD2030_5-10C.vhd @@ -42,6 +42,7 @@ USE ieee.numeric_std.all; library work; use work.Gates_package.all; use work.Buses_package.all; +use work.FLL; ENTITY n1050_DATA IS port @@ -240,6 +241,7 @@ signal NOT_OPER_RESET : STD_LOGIC; signal NOT_OPER : STD_LOGIC := '0'; signal RDY_SHARE_SET, RDY_SHARE_RESET, sRDY_SHARE : STD_LOGIC; signal CancelCode : STD_LOGIC; +signal NOT_n1050_OPER : STD_LOGIC; BEGIN -- Fig 5-10C @@ -326,22 +328,22 @@ GT_WRITE_REG <= sGT_WRITE_REG; -- AC2M4 AC2H6 TE_LCH_RESET <= sSET_LOWER_CASE or sGT_WRITE_REG; -TE_LCH_FL: FLL port map(S=>TE_LCH_SET,R=>TE_LCH_RESET,Q=>sTE_LCH); -- AC2B6 +TE_LCH_FL: entity FLL port map(S=>TE_LCH_SET,R=>TE_LCH_RESET,Q=>sTE_LCH); -- AC2B6 TE_LCH <= sTE_LCH; WR_SHARE_REQ_SET <= not n1050_RST_LCH and W_TIME and WR_LCH and not sTE_LCH; WR_SHARE_REQ_RESET <= RST_ATTACH or SHARE_REQ_RST; -WR_SHARE_REQ_FL: FLL port map(S=>WR_SHARE_REQ_SET,R=>WR_SHARE_REQ_RESET,Q=>sWR_SHARE_REQ); -- AC2K5 AC2D6 +WR_SHARE_REQ_FL: entity FLL port map(S=>WR_SHARE_REQ_SET,R=>WR_SHARE_REQ_RESET,Q=>sWR_SHARE_REQ); -- AC2K5 AC2D6 WR_SHARE_REQ <= sWR_SHARE_REQ; ALLOW_STROBE_SET <= RDR_1_CLUTCH and Y_TIME and sTE_LCH; ALLOW_STROBE_RESET <= sSET_LOWER_CASE or (Y_TIME and not RDR_1_CLUTCH) or X_TIME; -ALLOW_STROBE_FL: FLL port map(S=>ALLOW_STROBE_SET,R=>ALLOW_STROBE_RESET,Q=>sALLOW_STROBE); -- AC2B6 +ALLOW_STROBE_FL: entity FLL port map(S=>ALLOW_STROBE_SET,R=>ALLOW_STROBE_RESET,Q=>sALLOW_STROBE); -- AC2B6 ALLOW_STROBE <= sALLOW_STROBE; SHIFT_SET <= (n1050_CE_MODE and SET_SHIFT_LCH) or (SET_SHIFT_LCH and sTE_LCH and Y_TIME); SHIFT_RESET <= X_TIME or sSET_LOWER_CASE; -SHIFT_FL: FLL port map(S=>SHIFT_SET,R=>SHIFT_RESET,Q=>sSHIFT); -- AC2B6 +SHIFT_FL: entity FLL port map(S=>SHIFT_SET,R=>SHIFT_RESET,Q=>sSHIFT); -- AC2B6 FORCE_SHIFT_CHAR <= (UC_CHARACTER and Z_TIME and sSHIFT) or (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2C6 FORCE_LC_SHIFT <= (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2D6 ?? not? @@ -359,18 +361,19 @@ INTRV_REQ_SET <= (not n1050_OPER and READ_INQ and not RD_SHARE_REQ_LCH) INTRV_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH; -- AC2H5 AC2H3 -INTRV_REQ_FL: FLL port map(S=>INTRV_REQ_SET,R=>INTRV_REQ_RESET,Q=>sINTRV_REQ); -- AC2G6 AC2H3 +INTRV_REQ_FL: entity FLL port map(S=>INTRV_REQ_SET,R=>INTRV_REQ_RESET,Q=>sINTRV_REQ); -- AC2G6 AC2H3 TT5_POS_INTRV_REQ <= sINTRV_REQ; n1050_INTRV_REQ_RESET <= n1050_CE_MODE or (Z_BUS(0) and GT_1050_TAGS_OUT) or (GT_1050_TAGS_OUT and Z_BUS(3)) or RST_ATTACH or sRDY_SHARE; -n1050_INTRV_REQ_FL: FLL port map(S=>sINTRV_REQ,R=>n1050_INTRV_REQ_RESET,Q=>n1050_INTRV_REQ); -- AC2K3 AC2H4 +n1050_INTRV_REQ_FL: entity FLL port map(S=>sINTRV_REQ,R=>n1050_INTRV_REQ_RESET,Q=>n1050_INTRV_REQ); -- AC2K3 AC2H4 NOT_OPER_RESET <= RUN or sRDY_SHARE; -NOT_OPER_FL: FLL port map(S=>not n1050_OPER,R=>NOT_OPER_RESET,Q=>NOT_OPER); -- AC2G5 ?? Set input inverted +NOT_n1050_OPER <= not n1050_OPER; +NOT_OPER_FL: entity FLL port map(S=>NOT_n1050_OPER,R=>NOT_OPER_RESET,Q=>NOT_OPER); -- AC2G5 ?? Set input inverted RDY_SHARE_SET <= not sINTRV_REQ and TT_BUS(3) and NOT_OPER; -- AC2J7 RDY_SHARE_RESET <= INTRV_REQ_RESET or RUN or TA_REG_POS_6_ATTN_RST; -RDY_SHARE_FL: FLL port map(S=>RDY_SHARE_SET,R=>RDY_SHARE_RESET,Q=>sRDY_SHARE); -- AC2F6 AC2E5 +RDY_SHARE_FL: entity FLL port map(S=>RDY_SHARE_SET,R=>RDY_SHARE_RESET,Q=>sRDY_SHARE); -- AC2F6 AC2E5 READY_SHARE <= sRDY_SHARE; with DEBUG.Selection select diff --git a/Gates2030.vhd b/Gates2030.vhd index 44f1a81..bb2a744 100644 --- a/Gates2030.vhd +++ b/Gates2030.vhd @@ -43,7 +43,7 @@ USE ieee.std_logic_1164.all; use ieee.numeric_std.all; package Gates_package is -component PH is port(D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end component; +-- component PH is port(D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end component; component PHV4 is port(D : in STD_LOGIC_VECTOR(0 to 3); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 3)); end component; component PHV5 is port(D : in STD_LOGIC_VECTOR(0 to 4); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 4)); end component; component PHV8 is port(D : in STD_LOGIC_VECTOR(0 to 7); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 7)); end component; @@ -53,7 +53,7 @@ component PHR is port(D,L,R: in STD_LOGIC; signal Q:out STD_LOGIC); end componen component PHRV is port(D : in STD_LOGIC_VECTOR; L,R: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end component; component PHSR is port(D,L,S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component; component FLE is port(S,R,clock: in STD_LOGIC; signal Q:out STD_LOGIC); end component; -component FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component; +-- component FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component; component FLV is port(S,R: in STD_LOGIC_VECTOR; clock: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end component; component FLVL is port(S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end component; --component FLAO is port( S1,S2,S3,R1,R2: in STD_LOGIC; signal Q:out STD_LOGIC); end component; @@ -67,11 +67,12 @@ component DelayRisingEdge is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); component XilinxIOVector is port( I : in STD_LOGIC_VECTOR; T : in STD_LOGIC; O : out STD_LOGIC_VECTOR; IO : inout STD_LOGIC_VECTOR); end component; end Gates_package; + +-- FL is no longer an edge-triggered SR flip-flop LIBRARY ieee; USE ieee.std_logic_1164.all; entity FLE is port(S,R,clock: in STD_LOGIC; signal Q:out STD_LOGIC); end; --- FL is no longer an edge-triggered SR flip-flop architecture slt of FLE is begin process (S,R) @@ -84,61 +85,38 @@ end if; end process; end slt; -LIBRARY ieee; -USE ieee.std_logic_1164.all; -entity FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end; -- FLL is a level-triggered SR flip-flop -architecture slt of FLL is -begin -process(S,R) -begin -if (S='1') then -- Set takes priority - Q<='1' after 1ns; -elsif (R='1') then - Q<='0' after 1ns; -end if; -end process; -end slt; +--LIBRARY ieee; +--USE ieee.std_logic_1164.all; +--entity FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end; +-- +--architecture slt of FLL is +--begin +--process(S,R) +--begin +--if (S='1') then -- Set takes priority +-- Q<='1' after 1ns; +--elsif (R='1') then +-- Q<='0' after 1ns; +--end if; +--end process; +--end slt; -package body Gates_package is --- Variable width AND-OR multiplexor component -function mux(sel : in STD_LOGIC; D : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -alias D2:STD_LOGIC_VECTOR(1 to D'LENGTH) is D; -variable Q : STD_LOGIC_VECTOR(1 to D'LENGTH); -begin - if (sel = '1') then - Q := D; - else - Q := (others=>'0'); - end if; -return Q; -end function mux; -function EvenParity(v : in STD_LOGIC_VECTOR) return STD_LOGIC is -variable p : STD_LOGIC; -begin - p := '1'; - for m in v'range loop - p := p xor v(m); - end loop; - return p; -end; - -end Gates_package; -- Simple PH (polarity hold) latch -LIBRARY ieee; -USE ieee.std_logic_1164.all; -entity PH is port( D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end; - -architecture slt of PH is -begin -process(L,D) -begin -if (L='1') then - Q <= D; -end if; -end process; -end slt; +--LIBRARY ieee; +--USE ieee.std_logic_1164.all; +--entity PH is port( D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end; +-- +--architecture slt of PH is +--begin +--process(L,D) +--begin +--if (L='1') then +-- Q <= D; +--end if; +--end process; +--end slt; -- Simple PH (polarity hold) latch, 4 bit STD_LOGIC_VECTOR version LIBRARY ieee; @@ -312,25 +290,25 @@ end if; end process; end slt; -LIBRARY ieee; -USE ieee.std_logic_1164.all; -entity FLVL is port( S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end; - -architecture slt of FLVL is -alias S1 : STD_LOGIC_VECTOR(Q'range) is S; -alias R1 : STD_LOGIC_VECTOR(Q'range) is R; -begin -process (S1,R1) -begin -for i in Q'range loop -if (S1(i)='1') then -- Set takes priority - Q(i)<='1'; -elsif (R1(i)='1') then - Q(i)<='0'; -end if; -end loop; -end process; -end slt; +--LIBRARY ieee; +--USE ieee.std_logic_1164.all; +--entity FLVL is port( S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end; +-- +--architecture slt of FLVL is +--alias S1 : STD_LOGIC_VECTOR(Q'range) is S; +--alias R1 : STD_LOGIC_VECTOR(Q'range) is R; +--begin +--process (S1,R1) +--begin +--for i in Q'range loop +--if (S1(i)='1') then -- Set takes priority +-- Q(i)<='1'; +--elsif (R1(i)='1') then +-- Q(i)<='0'; +--end if; +--end loop; +--end process; +--end slt; -- Simple 1 cycle delay from line driver (AR) LIBRARY ieee; @@ -454,4 +432,31 @@ word_generator: for b in 0 to 8 generate begin U1: IOBUF port map (I => I(b), T => T, O => O(b), IO => IO(b)); end generate; -end slt; \ No newline at end of file +end slt; + +package body Gates_package is + +-- Variable width AND-OR multiplexor component +function mux(sel : in STD_LOGIC; D : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is +alias D2:STD_LOGIC_VECTOR(1 to D'LENGTH) is D; +variable Q : STD_LOGIC_VECTOR(1 to D'LENGTH); +begin + if (sel = '1') then + Q := D; + else + Q := (others=>'0'); + end if; +return Q; +end function mux; + +function EvenParity(v : in STD_LOGIC_VECTOR) return STD_LOGIC is +variable p : STD_LOGIC; +begin + p := '1'; + for m in v'range loop + p := p xor v(m); + end loop; + return p; +end; + +end Gates_package; diff --git a/PH.vhd b/PH.vhd new file mode 100644 index 0000000..49ee076 --- /dev/null +++ b/PH.vhd @@ -0,0 +1,36 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:34:05 06/17/2015 +-- Design Name: +-- Module Name: PH - slt +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Simple PH (polarity hold) latch + +entity PH is port( D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end; + +architecture slt of PH is +begin +process(L,D) +begin +if (L='1') then + Q <= D; +end if; +end process; +end slt; +