diff --git a/FMD2030_5-01A-B.vhd b/FMD2030_5-01A-B.vhd
index 56d5fc4..915aee2 100644
--- a/FMD2030_5-01A-B.vhd
+++ b/FMD2030_5-01A-B.vhd
@@ -173,24 +173,24 @@ BEGIN
 -- Fig 5-01A
 -- ROS Indicator register
 ROSAR_IND_LATCH_Set <= (ANY_MACH_CHK and CHK_OR_DIAG_STOP_SW) or EARLY_ROAR_STOP;
-ROSAR_IND_LATCH: entity FLL port map(ROSAR_IND_LATCH_Set,MACH_START_RST,FL_ROSAR_IND); -- AA3G4,AA3H4
+ROSAR_IND_LATCH: entity work.FLL port map(ROSAR_IND_LATCH_Set,MACH_START_RST,FL_ROSAR_IND); -- AA3G4,AA3H4
 sSET_IND_ROSAR <= (not ALU_CHK or not CHK_OR_DIAG_STOP_SW) and not FL_ROSAR_IND; -- AA3H4
 -- sSET_IND_ROSAR <= '1'; -- Debug
 SET_IND_ROSAR <= sSET_IND_ROSAR;
 SET_IND <= (T4 and sSET_IND_ROSAR) or MACH_RST_SET_LCH; -- AA3J4
 
-WINDP: entity PH port map(W_P,SET_IND,W_IND_P_X); -- AA3J2
+WINDP: entity work.PH port map(W_P,SET_IND,W_IND_P_X); -- AA3J2
 W_IND_P <= W_IND_P_X or TEST_LAMP;
-XINDP: entity PH port map(X_P,SET_IND,X_IND_P_X); -- AA3J3
+XINDP: entity work.PH port map(X_P,SET_IND,X_IND_P_X); -- AA3J3
 X_IND_P <= X_IND_P_X or TEST_LAMP;
-WXIND: entity PHV13 port map(sWX,SET_IND,WX_IND_X); -- AA3J2,AA3J3
+WXIND: entity work.PHV13 port map(sWX,SET_IND,WX_IND_X); -- AA3J2,AA3J3
 WX_IND <= WX_IND_X or (WX_IND'range=>TEST_LAMP);
 
 -- SALS parity checking
 -- ?? I have added a latch (FL) on PA to hold it at T4, as are W_IND_P and X_IND_P
 -- This keeps WX_CHK valid during T1, T2 and T3 - it is checked during T2 of the following cycle
 -- Without this, spurious ROS_ADDR checks are generated  because PA is not always valid at the next T2
-PA_PH: entity PH port map(SALS.SALS_PA,T4,PA_LCH);
+PA_PH: entity work.PH port map(SALS.SALS_PA,T4,PA_LCH);
 WX_CHK <= not(PA_LCH xor W_IND_P_X xor X_IND_P_X); -- AA2J4 ?? Inverted ??
 sSAL_PC <= not EvenParity(USE_BASIC_CA_DECODER & SALS.SALS_AK & SALS.SALS_PK & SALS.SALS_CH & SALS.SALS_CL & 
 		SALS.SALS_CM & SALS.SALS_CU & SALS.SALS_CA & SALS.SALS_CB & SALS.SALS_CK & SALS.SALS_PA & SALS.SALS_PS)
@@ -242,26 +242,26 @@ SET_W2A <= not ANY_PRIORITY_PULSE_PWR or not ALU_CHK_LCH or not CHK_SW_PROC_SW;
 SET_W2B <= sGT_BU_ROSAR_TO_WX_REG or not NORMAL_ENTRY; -- AA2F2
 SET_W2 <= SET_W2A and SET_W2B; -- AA2H5,AA2F2 Wired-AND
 SET_W_REG <= ((GT_CA_TO_W_REG or GT_CK_TO_W_REG or SET_W2) and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ??
-REG_W: entity PHV5 port map(W_ASSM(3 to 7),SET_W_REG,sWX(0 to 4)); -- AA2D2
-REG_WP: entity PH port map(W_ASSM(8),SET_W_REG,W_P); -- AA2D2
+REG_W: entity work.PHV5 port map(W_ASSM(3 to 7),SET_W_REG,sWX(0 to 4)); -- AA2D2
+REG_WP: entity work.PH port map(W_ASSM(8),SET_W_REG,W_P); -- AA2D2
 
 -- X_LATCH: 
 SET_X_REG <= (not INH_ROSAR_SET and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ??
-REG_X: entity PHV8 port map(X_ASSM(0 to 7),SET_X_REG,sWX(5 to 12)); -- AA2D3
-REG_XP: entity PH port map(X_ASSM(8),SET_X_REG,X_P); -- AA2D3
+REG_X: entity work.PHV8 port map(X_ASSM(0 to 7),SET_X_REG,sWX(5 to 12)); -- AA2D3
+REG_XP: entity work.PH port map(X_ASSM(8),SET_X_REG,X_P); -- AA2D3
 
 WX <= sWX;
 
 -- Backup ROSAR regs
 SET_F <= (MPX_SHARE_PULSE and T4) or MACH_RST_4; -- AA3G3
 SET_FW <= SET_F;
-FWX_LCH: entity PHV13 port map(sWX,SET_F,FWX); -- AA3H2,AA3H3
-FWP_LCH: entity PH port map(W_P,SET_F,FW_P); -- AA3H2
-FXP_LCH: entity PH port map(X_P,SET_F,FX_P); -- AA3H3
+FWX_LCH: entity work.PHV13 port map(sWX,SET_F,FWX); -- AA3H2,AA3H3
+FWP_LCH: entity work.PH port map(W_P,SET_F,FW_P); -- AA3H2
+FXP_LCH: entity work.PH port map(X_P,SET_F,FX_P); -- AA3H3
 SET_G <= (SX_CHAIN_PULSE and T4) or MACH_RST_5; -- AA3K2
-GWX_LCH: entity PHV13 port map(sWX,SET_G,GWX); -- AA2K5,AA2L2
-GWP_LCH: entity PH port map(W_P,SET_G,GW_P); -- AA2K5
-GXP_LCH: entity PH port map(X_P,SET_G,GX_P); -- AA2L2
+GWX_LCH: entity work.PHV13 port map(sWX,SET_G,GWX); -- AA2K5,AA2L2
+GWP_LCH: entity work.PH port map(W_P,SET_G,GW_P); -- AA2K5
+GXP_LCH: entity work.PH port map(X_P,SET_G,GX_P); -- AA2L2
 
 -- CROS triggering
 
diff --git a/FMD2030_5-01C-D.vhd b/FMD2030_5-01C-D.vhd
index 9c508b4..84a74af 100644
--- a/FMD2030_5-01C-D.vhd
+++ b/FMD2030_5-01C-D.vhd
@@ -127,39 +127,39 @@ CD_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST);
 CD_LCH: FLVL port map(CD_LCH_Set,CD_LCH_Reset,sCTRL.CTRL_CD); -- AA2C6
 
 STRAIGHT_LCH_Set <= sCTRL_REG_RST or (SET_CTRL_REG and not SALS_CF(0));
-STRAIGHT_LCH: entity FLL port map(STRAIGHT_LCH_Set, T1, sCTRL.STRAIGHT);
+STRAIGHT_LCH: entity work.FLL port map(STRAIGHT_LCH_Set, T1, sCTRL.STRAIGHT);
 CROSSED_LCH_Set <= SET_CTRL_REG and SALS_CF(0);
-CROSSED_LCH: entity FLL port map(CROSSED_LCH_Set, AUX_CTRL_REG_RST, sCTRL.CROSSED);
+CROSSED_LCH: entity work.FLL port map(CROSSED_LCH_Set, AUX_CTRL_REG_RST, sCTRL.CROSSED);
 
 CC2_LCH_Set <= SET_CTRL_REG and SALS_CC(2);
 CC2_LCH_Reset <= T1 or sCTRL_REG_RST;
-CC2_LCH: entity FLL port map(CC2_LCH_Set, CC2_LCH_Reset, sCTRL.CTRL_CC(2));
+CC2_LCH: entity work.FLL port map(CC2_LCH_Set, CC2_LCH_Reset, sCTRL.CTRL_CC(2));
 GTAHI_LCH_Set <= SET_CTRL_REG and SALS_CF(1);
 GTAHI_LCH_Reset <= T1 or sCTRL_REG_RST;
-GTAHI_LCH: entity FLL port map(GTAHI_LCH_Set, GTAHI_LCH_Reset, sCTRL.GT_A_REG_HI);
+GTAHI_LCH: entity work.FLL port map(GTAHI_LCH_Set, GTAHI_LCH_Reset, sCTRL.GT_A_REG_HI);
 GTALO_LCH_Set <= SET_CTRL_REG and SALS_CF(2);
 GTALO_LCH_Reset <= T1 or sCTRL_REG_RST;
-GTALO_LCH: entity FLL port map(GTALO_LCH_Set, GTALO_LCH_Reset, sCTRL.GT_A_REG_LO);
+GTALO_LCH: entity work.FLL port map(GTALO_LCH_Set, GTALO_LCH_Reset, sCTRL.GT_A_REG_LO);
 COMPCY_LCH_Set <= SET_CTRL_REG and COMPUTE;
 COMPCY_LCH_Reset <= T1 or sCTRL_REG_RST;
-COMPCY_LCH: entity FLL port map(COMPCY_LCH_Set, COMPCY_LCH_Reset, sCTRL.COMPUTE_CY_LCH);
+COMPCY_LCH: entity work.FLL port map(COMPCY_LCH_Set, COMPCY_LCH_Reset, sCTRL.COMPUTE_CY_LCH);
 
 CG0_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(0));
 CG_Reset <= T1 or (MACH_RST_SW or ANY_PRIORITY_LCH); -- ?? Required to prevent simultaneous Set & Reset of CG by MANUAL_STORE
-CG0: entity FLL port map(CG0_Set, CG_Reset, sCTRL.CTRL_CG(0)); sCTRL.GT_B_REG_HI <= sCTRL.CTRL_CG(0);
+CG0: entity work.FLL port map(CG0_Set, CG_Reset, sCTRL.CTRL_CG(0)); sCTRL.GT_B_REG_HI <= sCTRL.CTRL_CG(0);
 CG1_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(1));
-CG1: entity FLL port map(CG1_Set, CG_Reset, sCTRL.CTRL_CG(1)); sCTRL.GT_B_REG_LO <= sCTRL.CTRL_CG(1);
+CG1: entity work.FLL port map(CG1_Set, CG_Reset, sCTRL.CTRL_CG(1)); sCTRL.GT_B_REG_LO <= sCTRL.CTRL_CG(1);
 
 CV_LCH_Set <= SALS_CV and (0 to 1 => SET_CTRL_REG);
 CV_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST);
-CV_LCH: entity FLVL port map(CV_LCH_Set,CV_LCH_Reset,sCTRL.CTRL_CV); -- AA2D6
+CV_LCH: entity work.FLVL port map(CV_LCH_Set,CV_LCH_Reset,sCTRL.CTRL_CV); -- AA2D6
 CC01_LCH_Set <= SALS_CC(0 to 1) and (0 to 1 => SET_CTRL_REG);
 CC01_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST);
-CC01_LCH: entity FLVL port map(CC01_LCH_Set,CC01_LCH_Reset,sCTRL.CTRL_CC(0 to 1)); -- AA2D6
+CC01_LCH: entity work.FLVL port map(CC01_LCH_Set,CC01_LCH_Reset,sCTRL.CTRL_CC(0 to 1)); -- AA2D6
 
 CS_LCH_Set <= SALS_CS and (0 to 3 => SET_CTRL_REG);
 CS_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST);
-CS_LCH: entity FLVL port map(CS_LCH_Set,CS_LCH_Reset,sCTRL.CTRL_CS); -- AA2D7
+CS_LCH: entity work.FLVL port map(CS_LCH_Set,CS_LCH_Reset,sCTRL.CTRL_CS); -- AA2D7
 CTRL <= sCTRL;
 
 CK_SAL_P_BIT_TO_MPX <= SALS_PK and not MACH_RST_MPX;
diff --git a/FMD2030_5-02A-B.vhd b/FMD2030_5-02A-B.vhd
index 67055f9..d3a1207 100644
--- a/FMD2030_5-02A-B.vhd
+++ b/FMD2030_5-02A-B.vhd
@@ -212,17 +212,17 @@ USE_CA_BASIC_DECODER <= sUSE_CA_BASIC_DECODER;
 
 REST0_LCH_Set <= T2 and sGT_GWX_TO_WX_REG;
 REST0_LCH_Reset <= MACH_RST_SW or T1;
-REST0_LCH: entity FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0
+REST0_LCH: entity work.FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0
 SXREST_LCH_Set <= T4 and RESTORE_0;
 SXREST_LCH_Reset <= MACH_RST_SW or T3;
-SXREST_LCH: entity FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1
+SXREST_LCH: entity work.FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1
 MPXROS_LCH_Set <= T2 and sGT_FWX_TO_WX_REG;
 MPXROS_LCH_Reset <= MACH_RST_SW or T1;
-MPXROS_LCH: entity FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2
+MPXROS_LCH: entity work.FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2
 MPX_ROS_LCH <= sMPX_ROS_LCH;
 MPXREST_LCH_Set <= T4 and sMPX_ROS_LCH;
 MPXREST_LCH_Reset <= MACH_RST_SW or T3;
-MPXREST_LCH: entity FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3
+MPXREST_LCH: entity work.FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3
 
 X6_DATA <= X6_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
 X7_DATA <= X7_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
@@ -231,11 +231,11 @@ GT_MPX_LCH <= (MPX_SHARE_PULSE and T1) or MACH_RST_SW; -- AA3L4,AA3E3
 GT_SX_LCH <= (SX_CHAIN_PULSE and T1) or MACH_RST_SW; -- AA3F3,AA3L6
 
 -- ASCII latch plus X6,X7 storage for 
-ASC_LCH: entity PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3
-M7_LCH: entity PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3
-S7_LCH: entity PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3
-M6_LCH: entity PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3
-S6_LCH: entity PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3
+ASC_LCH: entity work.PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3
+M7_LCH: entity work.PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3
+S7_LCH: entity work.PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3
+M6_LCH: entity work.PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3
+S6_LCH: entity work.PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3
 
 STORED_X6 <= (SX_CH_ROAR_RESTORE and SX_CH_X6) or (MPX_CH_ROAR_RESTORE and MPX_CH_X6); -- AA3K6
 STORED_X7 <= (SX_CH_ROAR_RESTORE and SX_CH_X7) or (MPX_CH_ROAR_RESTORE and MPX_CH_X7); -- AA3K6
diff --git a/FMD2030_5-03A.vhd b/FMD2030_5-03A.vhd
index d40d367..790d64a 100644
--- a/FMD2030_5-03A.vhd
+++ b/FMD2030_5-03A.vhd
@@ -164,17 +164,17 @@ SUPPR_MACH_CHK_TRAP <= sSUPPR_MACH_CHK_TRAP; -- ??
 -- SUPPR_MACH_CHK_TRAP <= not RECYCLE_RST; -- ??
 sANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE; -- AB3D7
 ANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE_2;
-ANY_PRIORITY: entity PH port map(sANY_PRIORITY_PULSE_2,T1,sANY_PRIORITY_LCH); -- AB3D7,AB3J2
+ANY_PRIORITY: entity work.PH port map(sANY_PRIORITY_PULSE_2,T1,sANY_PRIORITY_LCH); -- AB3D7,AB3J2
 ANY_PRIORITY_LCH <= sANY_PRIORITY_LCH;
-S1_DLYD: entity PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2
-WX_SABC: entity PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2
+S1_DLYD: entity work.PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2
+WX_SABC: entity work.PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2
 GT_SW_TO_WX_LCH <= sGT_SW_TO_WX_LCH;
 CD0101 <= '1' when SALS_CDREG="0101" else '0';
 PRIOR_RST_Latch <= T4 or MACH_RST_SW;
-PRIOR_RST_CTRL_PH: entity PHR port map(D=>CD0101,L=>PRIOR_RST_Latch,R=>sANY_PRIORITY_PULSE,Q=>PRIOR_RST_CTRL); -- AB3J2
+PRIOR_RST_CTRL_PH: entity work.PHR port map(D=>CD0101,L=>PRIOR_RST_Latch,R=>sANY_PRIORITY_PULSE,Q=>PRIOR_RST_CTRL); -- AB3J2
 MEMP_LCH_Set <= sDATA_READY and ALLOW_PROTECT and PROT_LOC_CPU_OR_MPX;
 MEMP_LCH_Reset <= READ_CALL or RECYCLE_RST;
-STG_PROT_REQ: entity FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7
+STG_PROT_REQ: entity work.FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7
 MEM_PROTECT_REQ <= sMEM_PROTECT_REQ;
 
 sHZ_DEST_RST <= (P4 and sGT_SW_TO_WX_LCH) or (T3 and PRIOR_RST_CTRL); -- AB3K5,AB3J4
@@ -186,7 +186,7 @@ DATA_READY <= sDATA_READY;
 
 PRI_LCH_Set <= (T1 and DIAGNOSTIC_SW) or MACH_RST_LCH or (not HARD_STOP_LCH and T3 and sANY_PRIORITY_LCH);
 PRI_LCH_Reset <= sHZ_DEST_RST or sGT_SW_MACH_RST;
-PRIORITY: entity FLL port map(S=>PRI_LCH_Set,R=>PRI_LCH_Reset,Q=>PRIORITY_LCH); -- AB3J4,AB3L4
+PRIORITY: entity work.FLL port map(S=>PRI_LCH_Set,R=>PRI_LCH_Reset,Q=>PRIORITY_LCH); -- AB3J4,AB3L4
 
 -- Priority stack register - all inputs are inverted AB3L2
 PRIORITY_STACK_IN(0) <= GT_SWS_TO_WX_PWR;
@@ -199,7 +199,7 @@ PRIORITY_STACK_IN(6) <= STOP_REQ;
 PRIORITY_STACK_IN(7) <= SUPPR_A_REG_CHK and not H_REG_5_PWR and SEL_ROS_REQ;
 PRIORITY_STACK_IN(8) <= FT_3_MPX_SHARE_REQ and not H_REG_6 and not H_REG_5_PWR;
 PRISTK_LCH_Latch <= MACH_RST_6 or (not ALLOW_WRITE and T3) or (P4 and GT_SWS_TO_WX_PWR);
-PRISTK_LCH: entity PHV9 port map(    D => PRIORITY_STACK_IN,
+PRISTK_LCH: entity work.PHV9 port map(    D => PRIORITY_STACK_IN,
         L => PRISTK_LCH_Latch,
 		  Q => PRIORITY_STACK_OUT);
 sGT_SWS_TO_WX_LCH <= PRIORITY_STACK_OUT(0);
@@ -234,7 +234,7 @@ SX_CHAIN_PULSE_1 <= SX_CHAIN_PULSE;
 sMPX_SHARE_PULSE <= not SX_CHAIN_PULSE and not STOP_PULSE and not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and MPX_SHARE_REQ_LCH and not (H(5) or H(6)); -- ??
 MPX_SHARE_PULSE <= sMPX_SHARE_PULSE;
 
-SRP_LCH: entity FLL port map(MACH_RST_SW,T4,sSYS_RST_PRIORITY_LCH); -- AB3L3
+SRP_LCH: entity work.FLL port map(MACH_RST_SW,T4,sSYS_RST_PRIORITY_LCH); -- AB3L3
 SYS_RST_PRIORITY_LCH <= sSYS_RST_PRIORITY_LCH;
 
 sANY_PRIORITY_PULSE <= sMPX_SHARE_PULSE or SX_CHAIN_PULSE or STOP_PULSE or PROTECT_PULSE or HI_PRIORITY or sSYS_RST_PRIORITY_LCH; -- AB3K4 ??
diff --git a/FMD2030_5-03B.vhd b/FMD2030_5-03B.vhd
index 7b8b826..6791edb 100644
--- a/FMD2030_5-03B.vhd
+++ b/FMD2030_5-03B.vhd
@@ -117,12 +117,12 @@ CHECK_MPX_WRAP <= H_REG_6 and not H_REG_5_PWR; -- AB2L4
 CARRY_OUT <= CARRY_OUT_TRUE or CARRY_OUT_COMP; -- AB2L3
 
 UWRAP_LCH_Reset <= RECYCLE_RST or RESET_WRAP;
-UWRAP_LCH: entity PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4
-IWRAP_LCH: entity PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4
+UWRAP_LCH: entity work.PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4
+IWRAP_LCH: entity work.PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4
 I_WRAPPED_CPU <= sI_WRAPPED_CPU;
-UMPX_LCH: entity PHR port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,R=>RECYCLE_RST,Q=>sU_WRAPPED_MPX); -- AB2M4 ?? Doesn't have reset in FMD - causes Diag failure
+UMPX_LCH: entity work.PHR port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,R=>RECYCLE_RST,Q=>sU_WRAPPED_MPX); -- AB2M4 ?? Doesn't have reset in FMD - causes Diag failure
 U_WRAPPED_MPX <= sU_WRAPPED_MPX;
-WBUFF_LCH: entity PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ??
+WBUFF_LCH: entity work.PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ??
 
 WRAP64 <= (not H_REG_6 and GT_V_TO_N_REG and U_WRAP_CPU) or
 	(GT_J_TO_N_REG and not H_REG_6 and sI_WRAPPED_CPU) or
@@ -137,7 +137,7 @@ MEM_WRAP <= sMEM_WRAP;
 
 MWR_LCH_Set <= MAIN_STORAGE and T2 and (sMEM_WRAP and not ALLOW_WRITE);	-- ?? ALLOW_WRITE use unclear - dot logic
 MWR_LCH_Reset <= READ_CALL or RECYCLE_RST;
-MWR_LCH: entity FLL port map(MWR_LCH_Set,MWR_LCH_Reset,sMEM_WRAP_REQ);
+MWR_LCH: entity work.FLL port map(MWR_LCH_Set,MWR_LCH_Reset,sMEM_WRAP_REQ);
 MEM_WRAP_REQ <= sMEM_WRAP_REQ;
 SEL_DATA_READY <= (DATA_READY_1 or DATA_READY_2) and not sMEM_WRAP_REQ;
 
diff --git a/FMD2030_5-03C.vhd b/FMD2030_5-03C.vhd
index 3f5c596..29621f7 100644
--- a/FMD2030_5-03C.vhd
+++ b/FMD2030_5-03C.vhd
@@ -180,46 +180,46 @@ signal CSC_LCH_Set,SSR_LCH_Set,SSR_LCH_Reset,ECS_LCH_Set,ECS_LCH_Reset,LKI_LCH_S
 BEGIN
 -- Fig 5-03C
 -- STT RST INLK
-SRI_LCH: entity FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output
+SRI_LCH: entity work.FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output
 -- STT RST
 SSR_LCH_Set <= ALLOW_MAN_OPER and STT_RST_INLK and not SW_START;
 SSR_LCH_Reset <= T2 or MACH_RST_SW;
-SSR_LCH: entity FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7
+SSR_LCH: entity work.FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7
 START_SW_RST <= sSTART_SW_RST;
 -- CLK STT CTRL
 CSC_LCH_Set <= sCLOCK_RST or sE_CY_STOP_SAMPLE;
-CSC_LCH: entity FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5
+CSC_LCH: entity work.FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5
 -- E CY STOP SAMPLE
 ECS_LCH_Set <= SET_IC_START or (FT3_MPX_SHARE_REQ and M_CONV_OSC and PROC_STOP_LOOP_ACTIVE) or
 	(M_CONV_OSC and PROC_STOP_LOOP_ACTIVE and SEL_ROS_REQ) or
 	(not SW_START and M_CONV_OSC and not CLK_STT_CTRL); -- "not CLK_STT_CTRL" ?? is CLK_STT_CTRL meant to be inverted?
 ECS_LCH_Reset <= MACH_RST_SW or T4;
-ECS_LCH: entity FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7
+ECS_LCH: entity work.FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7
 E_CY_STOP_SAMPLE <= sE_CY_STOP_SAMPLE;	
 -- LOAD KEY INLK
 LKI_LCH_Set <= (not SW_LOAD and MACH_RST_3) or LOAD_KEY;
-LKI_LCH: entity FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output
+LKI_LCH: entity work.FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output
 LOAD_KEY_INLK <= sLOAD_KEY_INLK;
 -- LOAD KEY
 LK_LCH_Set <= not sLOAD_KEY_SW and sLOAD_KEY_INLK;
 LK_LCH_Reset <= T4 or sCLOCK_RST;
-LK_LCH: entity FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7
+LK_LCH: entity work.FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7
 sLOAD_KEY_SW <= SW_LOAD;
 LOAD_KEY_SW <= sLOAD_KEY_SW;
 -- SET IC INLK
 SI_LCH_Set <= (CLOCK_ON and SW_SET_IC) or MACH_RST_3 or sSET_IC_ALLOWED; -- MACH_RST_3 inverted??
 SI_LCH_Reset <= not SW_SET_IC; -- FMD is missing invert on switch output??
-SI_LCH: entity FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7
+SI_LCH: entity work.FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7
 -- SET IC
 SIA_LCH_Set <= ALLOW_MAN_OPER and not SET_IC_INLK and SW_SET_IC;
 SIA_LCH_Reset <= T2 or MACH_RST_SW;
-SIA_LCH: entity FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7
+SIA_LCH: entity work.FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7
 SET_IC_ALLOWED <= sSET_IC_ALLOWED;
 SET_IC_START <= not FORCE_IJ_REQ_LCH and M_CONV_OSC and sSET_IC_ALLOWED; -- AC1D6
 -- PROCESS STOP
 PS_LCH_Set <= sSET_IC_ALLOWED or SW_STOP or (SAR_DLYD_STOP_SW and MATCH) or (INSTRUCTION_STEP_SW and T4);
 PS_LCH_Reset <= sSTART_SW_RST or '0'; -- ?? What is second reset input?
-PS_LCH: entity FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5
+PS_LCH: entity work.FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5
 DEBUG <= PROCESS_STOP; -- ?? DEBUG ??
 -- PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed??
 PROC_STOP_LOOP_ACTIVE <= ((USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed?? and inverter on AA2G5 removed??
@@ -228,7 +228,7 @@ STOP_REQ <= PROCESS_STOP and not S_REG_1_DLYD and not INTERRUPT and END_OF_E_CY_
 -- CF STOP
 CF100T4 <= SALS.SALS_CF(0) and not SALS.SALS_CF(1) and not SALS.SALS_CF(2) and T4; -- AA2G5
 CFS_LCH_Reset <= (not CF100T4 and T4) or (not FORCE_IJ_REQ and not sROS_SCAN and not SW_PROC) or MACH_START_RST; -- AC1G5 AC1K6 AC1M5 AC1F2 ?? SW_INH_CF_STOP instead of SW_PROC ??
-CFS_LCH: entity FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5
+CFS_LCH: entity work.FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5
 sROS_SCAN <= SW_SCAN;
 ROS_SCAN <= sROS_SCAN;
 ROS_CTRL_PROC_SW <= SW_PROC;
@@ -240,7 +240,7 @@ INSTRUCTION_STEP_SW <= SW_INSTRUCTION_STEP;
 sRST_LOAD <= GT_CK_DECODE and SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3); -- AB3F7
 RST_LOAD <= sRST_LOAD;
 sRST_SEL_CHNL_DIAG_LCHS <= MACH_RST_3 or sRST_LOAD; -- AC1F5,AC1H6
-LOAD_REQ_FL: entity FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5
+LOAD_REQ_FL: entity work.FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5
 RST_SEL_CHNL_DIAG_LCHS <= sRST_SEL_CHNL_DIAG_LCHS;
 LOAD_IND <= sLOAD_IND;
 LOAD_REQ <= sLOAD_IND;
@@ -249,7 +249,7 @@ FT_4_LD_IND <= sLOAD_IND;
 -- CLOCK START
 CS_LCH_Set <= (LOAD_KEY and P_CONV_OSC) or (P_CONV_OSC and sE_CY_STOP_SAMPLE and not MAN_OPERATION);
 CS_LCH_Reset <= sCLOCK_RST or sCLOCK_STOP;
-CS_LCH: entity FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6
+CS_LCH: entity work.FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6
 CLOCK_START_LCH <= sCLOCK_START_LCH;
 
 sSEL_CHNL_CPU_CLOCK_STOP <= not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and T4) and
@@ -262,13 +262,13 @@ CLOCK_START <= sCLOCK_START;
 -- 2ND ERR STP
 N2E_LCH_Set <= MACH_CHK_PULSE and P1;
 N2E_LCH_Reset <= MACH_CHK_RST or HZ_DEST_RST;
-N2E_LCH: entity FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4
+N2E_LCH: entity work.FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4
 N2ND_ERROR_STOP <= sN2ND_ERROR_STOP;
 --PWR OFF
 sPWR_OFF_SW <= SW_PWR_OFF;
 PWR_OFF_SW <= sPWR_OFF_SW;
 PO_LCH_Set <= sPWR_OFF_SW and T3 and not ALLOW_WRITE;
-PO_LCH: entity FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4
+PO_LCH: entity work.FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4
 -- HARD STOP
 HS_MACH_CHK <= (sN2ND_ERROR_STOP and T4 and FIRST_MACH_CHK) or (CHK_OR_DIAG_STOP_SW and ANY_MACH_CHK); -- AB3F4
 sEARLY_ROAR_STOP <= MATCH_LCH and EARLY_ROAR_STOP_SW; -- AC1K5
@@ -282,7 +282,7 @@ HS_MATCH <= (SAR_STOP_SW and MATCH_LCH and T4) or (ROAR_STOP_SW and T4 and MATCH
 HS_INSTR <= T4 and INSTRUCTION_STEP_SW and ANY_PRIORITY_PULSE_PWR and sROS_SCAN; -- AB3H2
 
 HS_LCH_Set <= HS_MACH_CHK or sEARLY_ROAR_STOP or HS_ALU_CHK or HS_DIAG or HS_MATCH or HS_INSTR;
-HS_LCH: entity FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6
+HS_LCH: entity work.FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6
 HARD_STOP_LCH <= sHARD_STOP_LCH;
 
 sCLOCK_RST <= MACH_RST_3 or (sHARD_STOP_LCH and M_CONV_OSC_2) or (M_CONV_OSC_2 and not GT_J_REG_TO_A_BUS and CF_STOP); -- AC1F6,AC1G5
diff --git a/FMD2030_5-03D.vhd b/FMD2030_5-03D.vhd
index eb2b090..7ca9398 100644
--- a/FMD2030_5-03D.vhd
+++ b/FMD2030_5-03D.vhd
@@ -136,25 +136,25 @@ sALLOW_MAN_OPERATION <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CLOCK
 ALLOW_MAN_OPERATION <= sALLOW_MAN_OPERATION;
 UMD_LCH_Set <= (sALLOW_MAN_OPERATION and SW_DSPLY) or (sALLOW_MAN_OPERATION and SW_STORE);
 UMD_LCH_Reset <= E_CY_STOP_SMPL or sMACH_RST_3;
-UMD_LCH: entity FLL port map(UMD_LCH_Set,UMD_LCH_Reset, sUSE_MANUAL_DECODER); -- AC1G4
+UMD_LCH: entity work.FLL port map(UMD_LCH_Set,UMD_LCH_Reset, sUSE_MANUAL_DECODER); -- AC1G4
 USE_MANUAL_DECODER <= sUSE_MANUAL_DECODER;		
 USE_MAN_DECODER_PWR <= not E_CY_STOP_SMPL and sUSE_MANUAL_DECODER; -- AC1J4
 
 -- MAN DSPLY
 AC1D4 <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CONV_OSC); -- AC1G2,AC1D4 -- Inverter removed ??
 MD_LCH_Set <= CLOCK_OFF and SW_DSPLY and AC1D4;
-MD_LCH: entity FLL port map(MD_LCH_Set,not SW_DSPLY,sMANUAL_DISPLAY); -- AC1G4 - FMD missing invert on Reset input ??
+MD_LCH: entity work.FLL port map(MD_LCH_Set,not SW_DSPLY,sMANUAL_DISPLAY); -- AC1G4 - FMD missing invert on Reset input ??
 MANUAL_DISPLAY <= sMANUAL_DISPLAY;
 
 -- MAN STORE R
 sSTORE_S_REG_RST <= not CLOCK_ON and SW_STORE; -- AC1J6
 STORE_S_REG_RST <= sSTORE_S_REG_RST;
 MS_LCH_Set <= AC1D4 and sSTORE_S_REG_RST;
-MS_LCH: entity FLL port map(MS_LCH_Set,not SW_STORE,sMAN_STORE); -- AC1E5
+MS_LCH: entity work.FLL port map(MS_LCH_Set,not SW_STORE,sMAN_STORE); -- AC1E5
 MAN_STORE <= sMAN_STORE;
 -- MAN_STORE_PWR <= sMAN_STORE; -- AC1F3 -- Need to delay this a bit
-MAN_STORE_DELAY: entity AR port map(sMAN_STORE,Clk,sMAN_STORE2); -- AC1F3
-MAN_STORE2_DELAY: entity AR port map(sMAN_STORE2,Clk,MAN_STORE_PWR); -- AC1F3
+MAN_STORE_DELAY: entity work.AR port map(sMAN_STORE,Clk,sMAN_STORE2); -- AC1F3
+MAN_STORE2_DELAY: entity work.AR port map(sMAN_STORE2,Clk,MAN_STORE_PWR); -- AC1F3
 sMAN_STOR_OR_DSPLY <= sMANUAL_DISPLAY or sMAN_STORE; -- AC1J2,AC1F3
 MAN_STOR_OR_DSPLY <= sMAN_STOR_OR_DSPLY;
 
@@ -181,22 +181,22 @@ CPU_SET_ALLOW_WR_LCH <= sCPU_SET_ALLOW_WR_LCH;
 -- ALLOW WR
 AW_LCH_Set <= sCPU_SET_ALLOW_WR_LCH or SEL_AUX_RD_CALL;
 AW_LCH_Reset <= sMACH_RST_3 or SEL_WR_CALL or MAN_WR_CALL or (ROAR_RESTT_STOR_BYPASS and RECYCLE_RST) or (CPU_WR_PWR and T2);
-ALLOW_WRITE_LCH: entity FLL port map(AW_LCH_Set,AW_LCH_Reset,sALLOW_WRITE); -- AA1J2,AA1F6,AA1H3
+ALLOW_WRITE_LCH: entity work.FLL port map(AW_LCH_Set,AW_LCH_Reset,sALLOW_WRITE); -- AA1J2,AA1F6,AA1H3
 ALLOW_WRITE <= sALLOW_WRITE;	
-DELAY_ALLOW_WR : entity AR port map (D=>sALLOW_WRITE,clk=>Clk,Q=>sALLOW_WR); -- AA1H2,AA1J7
+DELAY_ALLOW_WR : entity work.AR port map (D=>sALLOW_WRITE,clk=>Clk,Q=>sALLOW_WR); -- AA1H2,AA1J7
 ALLOW_WR_DLYD <= sALLOW_WR;
 
 -- MAN WR CALL
 MW_LCH_Set <= (sALLOW_WR and LOAD_KEY_INLK) or (sALLOW_WR and sSYSTEM_RST_SW) or (sALLOW_WR and POWER_OFF_SW) or (sMAN_STOR_OR_DSPLY and READ_ECHO);
 MW_LCH_Reset <= CLOCK_ON or MAN_WR_CALL_RST;
-MW_LCH: entity FLL port map(MW_LCH_Set,MW_LCH_Reset,MAN_WR_CALL); -- AC1J2,AC1F4,AC1H5
+MW_LCH: entity work.FLL port map(MW_LCH_Set,MW_LCH_Reset,MAN_WR_CALL); -- AC1J2,AC1F4,AC1H5
 
 -- MAN RD INLK
-MAN_RD_INLK_FL: entity FLL port map(MAN_RD_CALL_LCH,not sMAN_STOR_OR_DSPLY,MAN_RD_INLK); -- AC1F4
+MAN_RD_INLK_FL: entity work.FLL port map(MAN_RD_CALL_LCH,not sMAN_STOR_OR_DSPLY,MAN_RD_INLK); -- AC1F4
 -- MAN RD CALL
 MRC_LCH_Set <= sSTG_MEM_SEL and not MAN_RD_INLK and sMAN_STOR_OR_DSPLY;
 MRC_LCH_Reset <= not sMAN_STOR_OR_DSPLY or READ_ECHO;
-MAN_RD_CALL_FL: entity FLL port map(MRC_LCH_Set,MRC_LCH_Reset,MAN_RD_CALL_LCH); -- AC1J2,AC1E2
+MAN_RD_CALL_FL: entity work.FLL port map(MRC_LCH_Set,MRC_LCH_Reset,MAN_RD_CALL_LCH); -- AC1J2,AC1E2
 sMAN_RD_CALL <= MAN_RD_CALL_LCH and not sALLOW_WR; -- AC1J2
 MAN_RD_CALL <= sMAN_RD_CALL;
 
@@ -212,7 +212,7 @@ MANUAL_OPERATION <= sMAN_RD_CALL or MAN_WR_CALL or MAN_WR_CALL_RST or READ_ECHO;
 -- STORE R
 SR_LCH_Set <= MAN_WR_CALL or (T1 and USE_R);
 SR_LCH_Reset <= SEL_T1 or (T1 and not CU_SALS(0) and CU_SALS(1));
-SR_LCH: entity FLL port map(SR_LCH_Set,SR_LCH_Reset,sSTORE_R); -- 06C
+SR_LCH: entity work.FLL port map(SR_LCH_Set,SR_LCH_Reset,sSTORE_R); -- 06C
 STORE_R <= sSTORE_R;
 MAN_WRITE_CALL <= not READ_ECHO and MAN_WR_CALL and sSTORE_R; -- AC1G3
 
diff --git a/FMD2030_5-04A-B.vhd b/FMD2030_5-04A-B.vhd
index 8932089..e1dcbc6 100644
--- a/FMD2030_5-04A-B.vhd
+++ b/FMD2030_5-04A-B.vhd
@@ -176,7 +176,7 @@ BEGIN
 -- Fig 5-04A
 NW_LCH_Set <= N_CTRL_N and XOR_OR_OR and T2;
 NW_LCH_Reset <= not S_REG_7_BIT or sRECYCLE_RST;
-NW_LCH: entity FLL port map(NW_LCH_Set,NW_LCH_Reset,NWAIT); --AC1E6,AC1F6
+NW_LCH: entity work.FLL port map(NW_LCH_Set,NW_LCH_Reset,NWAIT); --AC1E6,AC1F6
 sCLOCK_OUT <= (not NWAIT and CLOCK_ON) or MAN_STOR_OR_DSPLY; -- AC1G6
 CLOCK_OUT <= sCLOCK_OUT;
 CHNL_TO_METER <= not HARD_STOP_LCH and (MPX_METERING_IN or METER_IN_SX1 or METER_IN_SX2); -- AC1K4,AC1F2 ??
@@ -203,16 +203,16 @@ IND_SEL_CHNL <= H_REG_5_PWR or sLAMP_TEST;
 TEST <= (not ROS_CTRL_PROC_SW) or (not RATE_SW_PROC_SW) or (not SW_ADDR_COMP_PROC) or (not ODD) or (not sCHK_SW_PROCESS_SW) or INTRODUCE_ALU_CHK; -- AC1C4,AC1K5,AC1D4,AC1K5 ??
 
 MRS_LCH_Reset <= not LOAD_KEY_SW and not SYSTEM_RESET_SW;
-MRS_LCH: entity FLL port map(MACH_RST_SW,MRS_LCH_Reset,sMACH_RST_SET_LCH); -- AA2H5,AA2F5
+MRS_LCH: entity work.FLL port map(MACH_RST_SW,MRS_LCH_Reset,sMACH_RST_SET_LCH); -- AA2H5,AA2F5
 MACH_RST_SET_LCH <= sMACH_RST_SET_LCH;
 MACH_RST_SET_LCH_DLYD <= sMACH_RST_SET_LCH; -- ?? Should be delayed by 1 gate
 -- MACH_RST_DELAY: AR port map(D=>sMACH_RST_SET_LCH,CLK=>Clk,Q=>MACH_RST_SET_LCH_DLYD); -- Delay
 FORCE_DEAD_CY <= SW_SAR_RESTART and T4 and MATCH_SET_MACH_RST_LCH; -- AB3B6
-FDC_LCH: entity FLL port map(FORCE_DEAD_CY,T3,sFORCE_DEAD_CY_LCH); -- AB3L3
+FDC_LCH: entity work.FLL port map(FORCE_DEAD_CY,T3,sFORCE_DEAD_CY_LCH); -- AB3L3
 FORCE_DEAD_CY_LCH <= sFORCE_DEAD_CY_LCH;
 
 EEC_LCH_Set <= T2 and (CL_SALS(0) and CL_SALS(1) and CL_SALS(2) and CL_SALS(3)); -- ?? additional NOT
-EEC_LCH: entity FLL port map(EEC_LCH_Set,T1,sEND_OF_E_CY_LCH); -- AC1G4 ?? Reset input is unlabeled
+EEC_LCH: entity work.FLL port map(EEC_LCH_Set,T1,sEND_OF_E_CY_LCH); -- AC1G4 ?? Reset input is unlabeled
 END_OF_E_CY_LCH <= sEND_OF_E_CY_LCH;
 END_OF_E_CYCLE <= sEND_OF_E_CY_LCH or INH_ROSAR_SET; -- AC1J7
 
@@ -221,18 +221,18 @@ MATCH_SET_MACH_RST_LCH <= ((SW_SAR_RESTART and sMATCH_LCH and not ALLOW_WRITE_DL
 
 FIJ_LCH_Set <= (MATCH_SET_MACH_RST_LCH and CLOCK_ON) or SET_IC_LCH; -- ?? *not* MATCH_SET_MACH_RST_LCH & *not* CLOCK_ON ??
 FIJ_LCH_Reset <= MACH_RST_3 or (T1 and FORCE_IJ_PULSE);
-FIJ_LCH: entity FLL port map(FIJ_LCH_Set,FIJ_LCH_Reset,sFORCE_IJ_REQ); -- AC1E6,AC1H6
+FIJ_LCH: entity work.FLL port map(FIJ_LCH_Set,FIJ_LCH_Reset,sFORCE_IJ_REQ); -- AC1E6,AC1H6
 FORCE_IJ_REQ <= sFORCE_IJ_REQ;
 MACH_START_RST <= (sFORCE_IJ_REQ and not FORCE_IJ_REQ_LCH) or START_SW_RST or MACH_RST_6; -- AB3J5,AB3H3
 
 CR_LCH_Set <= ANY_MACH_CHK and CHK_RESTART_SW;
 CR_LCH_Reset <= ANY_PRIORITY_LCH or sMACH_CHK_RST;
-CR_LCH: entity FLL port map(CR_LCH_Set,CR_LCH_Reset,CHK_RESTT_LCH); -- AB3H4,AC1H6
+CR_LCH: entity work.FLL port map(CR_LCH_Set,CR_LCH_Reset,CHK_RESTT_LCH); -- AB3H4,AC1H6
 
 CHK_RESTART_SW <= SW_CHK_RESTART;
 -- Diagnostic latch is not in the FMD but must have appeared later
 -- It is set on Sys Reset and reset by the YL / 0->DIAG function (Alt-CK=0000)
-DIAG_FL: entity FLL port map(S=>MACH_RST_6,R=>DIAG_LATCH_RST,Q=>DIAG_LATCH);
+DIAG_FL: entity work.FLL port map(S=>MACH_RST_6,R=>DIAG_LATCH_RST,Q=>DIAG_LATCH);
 
 sDIAGNOSTIC_SW <= SW_DIAGNOSTIC or DIAG_LATCH;
 DIAGNOSTIC_SW <= sDIAGNOSTIC_SW;
@@ -258,7 +258,7 @@ CHK_RST_SW <= SW_CHK_RST; -- AB3F5
 
 MR_LCH_Set <= FORCE_DEAD_CY or MACH_RST_6;
 MR_LCH_Reset <= HZ_DEST_RST or SW_ROAR_RST; -- ?? *not* SW_ROAR_RST
-MR_LCH: entity FLL port map(MR_LCH_Set,MR_LCH_Reset,sMACH_RST_LCH); -- AB3F2,AB3J4
+MR_LCH: entity work.FLL port map(MR_LCH_Set,MR_LCH_Reset,sMACH_RST_LCH); -- AB3F2,AB3J4
 MACH_RST_LCH <= sMACH_RST_LCH;
 
 GSWX_LCH_Set <= (SW_ROAR_RST and ALLOW_MAN_OPERATION) or
@@ -267,7 +267,7 @@ GSWX_LCH_Set <= (SW_ROAR_RST and ALLOW_MAN_OPERATION) or
 	(not ALLOW_WRITE_DLYD and ROAR_RESTT_SW_ORED and sMATCH) or
 	(SW_ROAR_RESTT_STOR_BYPASS and CHK_RESTT_LCH);
 GSWX_LCH_Reset <= MACH_RST_SW or (T3 and GT_SW_TO_WX_LCH);
-GSWX_LCH: entity FLL port map(GSWX_LCH_Set,GSWX_LCH_Reset,sGT_SWS_TO_WX_REG); -- AC1H5,AC1H7,AC1H4,AC1K5,AC1J7
+GSWX_LCH: entity work.FLL port map(GSWX_LCH_Set,GSWX_LCH_Reset,sGT_SWS_TO_WX_REG); -- AC1H5,AC1H7,AC1H4,AC1K5,AC1J7
 
 GT_SWS_TO_WX_PWR <= not sMACH_RST_LCH and sGT_SWS_TO_WX_REG; -- AC1E7
 
@@ -301,7 +301,7 @@ ANDWX <= (WX_REG_BUS(0) xor not ABCD_SW_BUS(3)) and OEA1 and OEA2 and OEA3 and G
 
 M_LCH_Set <= ANDMN or ANDWX;
 M_LCH_Reset <= RST_MATCH or MACH_RST_SW;
-M_LCH: entity FLL port map(M_LCH_Set,M_LCH_Reset,sMATCH_LCH); -- AC1L7,AC1L4
+M_LCH: entity work.FLL port map(M_LCH_Set,M_LCH_Reset,sMATCH_LCH); -- AC1L7,AC1L4
 MATCH_LCH <= sMATCH_LCH;
 sMATCH <= sMATCH_LCH and not CLOCK_OFF; -- AC1H5
 MATCH <= sMATCH;
diff --git a/FMD2030_5-04C.vhd b/FMD2030_5-04C.vhd
index 254d499..c12ce74 100644
--- a/FMD2030_5-04C.vhd
+++ b/FMD2030_5-04C.vhd
@@ -89,7 +89,9 @@ ENTITY ManualDataCFH IS
 		GT_1050_BUS : OUT STD_LOGIC; -- 10C
 		CD_REG_2 : OUT STD_LOGIC; -- 05C
 		-- E switch
-		E_SW : IN E_SW_BUS_Type;
+		E_SW : IN E_SW_BUS_Type;
+		
+		DEBUG : INOUT DEBUG_BUS;
 		        
 		-- Clocks
 		T1,T2,T3,T4 : IN STD_LOGIC;
@@ -140,15 +142,16 @@ UV_SEL <= '1' when (E_SW.U_SEL='1' or E_SW.V_SEL='1') and USE_MAN_DECODER_PWR='1
 RST_COUNTER <= MACH_RST_PROT; -- BE3G5
 
 CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (not sTIMER_UPDATE and SW_INTRP_TIMER);
+-- CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (sTIMER_UPDATE and SW_INTRP_TIMER);
 CTL_LCH_Reset <= CTRL_TRG and T3;
-CTL_LCH: entity FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5
+CTL_LCH: entity work.FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5
 
 N10MSPULSE <= not(N60_CY_TIMER_PULSE and not T3); -- 10ms monostable here
 
 CT_FF_Set <= CTRL_LCH and T4;
-CT_FF: entity FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6
-BD_FF_Set <= not CTRL_LCH and T2 and N10MSPULSE and not CNTR_FULL;
-BD_FF: entity FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6
+CT_FF: entity work.FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6
+BD_FF_Set <= not CTRL_LCH and T3 and N10MSPULSE and not CNTR_FULL; -- Not T2 as per MDM (refer FETOM)
+BD_FF: entity work.FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6
 
 process(BIN_DRIVE,RST_COUNTER,CTRL_TRG) -- BE3G7,BE3F7
 	begin
@@ -163,15 +166,16 @@ process(BIN_DRIVE,RST_COUNTER,CTRL_TRG) -- BE3G7,BE3F7
 CNTR_FULL <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6
 
 -- Interrupt generation
-sTIMER_UPDATE <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6,BE3G5
-TIMER_UPDATE <= sTIMER_UPDATE;
--- TIMER_UPDATE_OR_EXT_INT <= sTIMER_UPDATE or EXT_INT; -- AC1D5
-TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporarily prevent Timer
+sTIMER_UPDATE <= C_BINARY_CNTR(4) or C_BINARY_CNTR(5) or C_BINARY_CNTR(6) or C_BINARY_CNTR(7); -- BE3G6,BE3G5
+TIMER_UPDATE <= sTIMER_UPDATE and EXT_TRAP_MASK_ON; -- Modified to include EXT_TRAP_MASK_ON for timer as well
+-- TIMER_UPDATE <= sTIMER_UPDATE;
+TIMER_UPDATE_OR_EXT_INT <= (sTIMER_UPDATE and EXT_TRAP_MASK_ON) or EXT_INT; -- AC1D5 Modified to include EXT_TRAP_MASK_ON for timer as well
+-- TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporarily prevent Timer
 EXT_INT <= (F_REGISTER(0) or F_REGISTER(1) or F_REGISTER(2) or F_REGISTER(3) or
 	F_REGISTER(4) or F_REGISTER(5) or F_REGISTER(6) or F_REGISTER(7)) and EXT_TRAP_MASK_ON;  -- AC1G2 ?? Should this include EXT_TRAP_MASK_ON ?
 EI_LCH_Reset <= MACH_RST_SW or RESET_F_REG;
 EI_LCH_Set <= EXT_INT and T3; -- ?? Seems to be needed, not as per MDM
-EI_LCH: entity FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2
+EI_LCH: entity work.FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2
 
 -- F register - here it is held in True polarity, in the 2030 it is inverted
 C_EXT_INT <= "000000";
@@ -180,11 +184,11 @@ RESET_F_REG <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and not CK_SALS(3) and G
 
 F1A_LCH_Reset <= (L_REGISTER(1) and RESET_F_REG) or RECYCLE_RST;
 F1_LCH_Set <= F_REGISTER_1A and SW_CONS_INTRP;
-F1A_LCH: entity FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2
+F1A_LCH: entity work.FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2
 
 F07_LCH_Set <= SET_F_REG_0 & F1_LCH_Set & C_EXT_INT(2 to 7);
 F07_LCH_Reset <= (0 to 7 => RECYCLE_RST) or ((0 to 7 => RESET_F_REG) and ('1' & L_REGISTER(1 to 7)));
-F07_LCH: entity FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2
+F07_LCH: entity work.FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2
 
 -- H register
 H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or
@@ -192,9 +196,9 @@ H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or
 GT_1050_TAGS <= not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and not CD_CTRL_REG(3); -- AB1B3 CD=0100
 GT_1050_BUS <= not CD_CTRL_REG(0) and not CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3); -- AB1B3 CD=0001
 CD_REG_2 <= CD_CTRL_REG(2); -- AB1B3
-H_LCH: entity PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3
+H_LCH: entity work.PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3
 H_REG_BITS <= sH_REG_BITS;
-HP_LCH: entity PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3
+HP_LCH: entity work.PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3
 H_REG_P <= sH_REG_P;
 H_REG_6 <= sH_REG_BITS(6); -- AB1C6,AB1G2
 H_REG_5_PWR <= sH_REG_BITS(5); -- AB1L2
@@ -211,5 +215,24 @@ A_BUS <= not ("0000" & C_BINARY_CNTR & '0') when GT_C_TO_A_BUS='1'
 	else (F_REGISTER & '0') when GT_F_TO_A='1' -- ?? F_REGISTER should be inverted?
 	else not (sH_REG_BITS & sH_REG_P) when GT_H_TO_A='1'
 	else "111111111"; -- AB1F6
+
+with DEBUG.Selection select
+	DEBUG.Probe <=
+		C_BINARY_CNTR(7) when 0,
+		C_BINARY_CNTR(6) when 1,
+		C_BINARY_CNTR(5) when 2,
+		C_BINARY_CNTR(4) when 3,
+		N10MSPULSE when 4,
+		CNTR_FULL when 5,
+		CTRL_LCH when 6,
+		CTRL_TRG when 7,
+		BIN_DRIVE when 8,
+		RST_COUNTER when 9,
+		N60_CY_TIMER_PULSE when 10,
+		CTL_LCH_Set when 11,
+		CTL_LCH_Reset when 12,
+		BD_FF_Set when 13,
+		EXT_INT when 14,
+		sTIMER_UPDATE when 15;
 
 END FMD;
diff --git a/FMD2030_5-04D.vhd b/FMD2030_5-04D.vhd
index 0672cdd..d7e6ac2 100644
--- a/FMD2030_5-04D.vhd
+++ b/FMD2030_5-04D.vhd
@@ -115,7 +115,7 @@ RD_SEL <= MANUAL_RD_CALL or (sCPU_READ_PWR and T1) or sCHANNEL_RD_CALL; -- BE3D3
 WR_SEL <= (T1 and sCPU_WRITE_PWR and ALLOW_WRITE_2) or MANUAL_WR_CALL or (SEL_RD_CALL_TO_STP or HSMPX_READ_CALL); -- BE3J5,BE3H5
 N_MEM_SELECT <= not (not SELECT_CPU_BUMP and (RD_SEL or WR_SEL)); -- BE3H6
 -- ?? Note TD not implemented (yet)
-RW_LCH: entity FLL port map(RD_SEL,WR_SEL,RW_CTRL_STACK); -- BE3J5
+RW_LCH: entity work.FLL port map(RD_SEL,WR_SEL,RW_CTRL_STACK); -- BE3J5
 
 sUSE_ALT_CU_DECODE <= not ANY_PRIORITY_PULSE and not sCPU_READ_PWR; -- AB3D2
 USE_ALT_CU_DECODE <= sUSE_ALT_CU_DECODE;
@@ -152,8 +152,8 @@ sGT_LOCAL_STG <= ((MEM_SEL and not ALLOW_WRITE) and MAN_STOR_OR_DISPLAY) or (T1
 GT_LOCAL_STG <= sGT_LOCAL_STG;
 
 
-LS_LCH: entity PH port map(not sMAIN_STORAGE_CP,sGT_LOCAL_STG,LOCAL_STORAGE_CP); -- AA1F4
-MS_LCH: entity PH port map(not sEARLY_LOCAL_STG,sGT_LOCAL_STG,MAIN_STORAGE); -- AA1F4
+LS_LCH: entity work.PH port map(not sMAIN_STORAGE_CP,sGT_LOCAL_STG,LOCAL_STORAGE_CP); -- AA1F4
+MS_LCH: entity work.PH port map(not sEARLY_LOCAL_STG,sGT_LOCAL_STG,MAIN_STORAGE); -- AA1F4
 
 END FMD; 
 
diff --git a/FMD2030_5-05A.vhd b/FMD2030_5-05A.vhd
index 74af8ff..e476e1e 100644
--- a/FMD2030_5-05A.vhd
+++ b/FMD2030_5-05A.vhd
@@ -95,7 +95,7 @@ BEGIN
 
 	N1401_MODE_SET <= W3_TO_MATCH and not ROS_SCAN; -- AC1C4
 	N1401_MODE_RESET <= T2 or GT_SW_MACH_RST;
-	MODE1401: entity FLL port map(N1401_MODE_SET,N1401_MODE_RESET,sN1401_MODE); -- AB2B2,AB1B3,AB2C2
+	MODE1401: entity work.FLL port map(N1401_MODE_SET,N1401_MODE_RESET,sN1401_MODE); -- AB2B2,AB1B3,AB2C2
 	N1401_MODE <= sN1401_MODE;
 
 	V67_EQUALS_00 <= not V_REG_6 and not V_REG_7; -- AA1H6
diff --git a/FMD2030_5-05D.vhd b/FMD2030_5-05D.vhd
index c00ed3c..3ff3132 100644
--- a/FMD2030_5-05D.vhd
+++ b/FMD2030_5-05D.vhd
@@ -119,7 +119,7 @@ WRITE_CALL_TO_MEM <= (MAN_WR_CALL or SEL_WR_CALL or START_WR) and not ROAR_RESTT
 
 USE_LOCAL_Set <= EARLY_LOCAL_STG and READ_CALL_TO_MEM;
 USE_LOCAL_Reset <= not EARLY_LOCAL_STG and READ_CALL_TO_MEM;
-USE_LOCAL: entity FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2
+USE_LOCAL: entity work.FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2
 USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM;
 USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2
 
@@ -143,38 +143,38 @@ TD1_680 <= TD1(34); -- 680ns
 TD1_700 <= TD1(35); -- 700ns
 
 nRD_OR_WR_SET1 <= not RD_OR_WR_SET1;
-RD_OR_WR_RST1_FL: entity FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1);
+RD_OR_WR_RST1_FL: entity work.FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1);
 RD_OR_WR_SET1_RESET <= RD_OR_WR_RST1 or MACH_RST_SW;
 -- The delay is to prevent a combinatorial loop:
 Delay_RD_OR_WR_SET1_RESET: AR port map (D=>RD_OR_WR_SET1_RESET, clk=>Clk, Q=>dRD_OR_WR_SET1_RESET);
-RD_OR_WR_SET1_FL: entity FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1);
+RD_OR_WR_SET1_FL: entity work.FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1);
 TD1IN <= not RD_OR_WR_RST1 and RD_OR_WR_SET1;
 
 -- READ CLOCK 0
 READ_ECHO_1_SET <= TD1_150 and SET_READ_LCHS1;
 READ_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and RD_RST_CTRL1);
-READ_ECHO_1_FL: entity FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns
+READ_ECHO_1_FL: entity work.FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns
 -- READ CLOCK 4
 DATA_READY1_SET <= TD1_560 and SET_READ_LCHS1;
 DATA_READY1_RESET <= MACH_RST_SW or (TD1_660 and RD_RST_CTRL1);
-DATA_READY1_FL: entity FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns
+DATA_READY1_FL: entity work.FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns
 DATA_READY_1 <= sDATA_READY_1;
 
 -- READ CLOCK 5
 READ_RST_SET1 <= TD1_500 and SET_READ_LCHS1;
 READ_RST_RESET1 <= MACH_RST_SW or TD1_700;
-READ_RST1_FL: entity FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns
+READ_RST1_FL: entity work.FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns
 -- WRITE CLOCK 0
 WRITE_ECHO_1_SET <= TD1_150 and not SET_READ_LCHS1;
 WRITE_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and WR_RST_CTRL1);
-WRITE_ECHO_1_FL: entity FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns
+WRITE_ECHO_1_FL: entity work.FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns
 -- WRITE CLOCK 4
 SET_READ_LCHS1_RESET <= MACH_RST_SW or WRITE_CALL_TO_MEM; -- ??
-SET_READ_LCHS1_FL: entity FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL
+SET_READ_LCHS1_FL: entity work.FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL
 -- WRITE CLOCK 5
 WRITE_RST_SET1 <= TD1_500 and not SET_READ_LCHS1;
 WRITE_RST_RESET1 <= MACH_RST_SW or TD1_150; -- 150ns or 1050ns or 1500ns?
-WRITE_RST1_FL: entity FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns??
+WRITE_RST1_FL: entity work.FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns??
 
 -- Second 32K
 READ_ECHO_2 <= '0';
diff --git a/FMD2030_5-07A2.vhd b/FMD2030_5-07A2.vhd
index f1892ba..8fcc311 100644
--- a/FMD2030_5-07A2.vhd
+++ b/FMD2030_5-07A2.vhd
@@ -42,7 +42,7 @@ USE ieee.std_logic_unsigned.all;
 
 library work;
 use work.Gates_package.all;
-use work.Buses_package.all;
+use work.Buses_package.all;
 
 ENTITY ChkRegInd IS
 	port
@@ -133,10 +133,10 @@ ALLW_A_REG_CHK_Set <= (P1 and USE_BASIC_CA_DECO and not GT_CA_TO_W_REG and CAX1X
 	(CAX11X and not GT_CA_TO_W_REG and USE_BASIC_CA_DECO and P1) or -- AB3F3
 	(USE_BASIC_CA_DECO and CA1XXX and P1); -- AB3K5
 ALLW_A_REG_CHK_Reset <= T1 or ROS_SCAN or sSUPPR_A_REG_CHK or ANY_PRIORITY_LCH;
-ALLW_A_REG_CHK: entity FLL port map(ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,ALLOW_A_REG_CHK); -- AB3K5,AB3B6,AB3J4
+ALLW_A_REG_CHK: entity work.FLL port map(ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,ALLOW_A_REG_CHK); -- AB3K5,AB3B6,AB3J4
 
 NOT_ALLOW_PC_SALS_Set <= (SET_IND_ROSAR and T4) or MACH_RST_6;
-NOT_ALLOW_PC_SALS: entity FLL port map(NOT_ALLOW_PC_SALS_Set,not T3,N_ALLOW_PC_SALS); -- AB3F6,AB3D7,AB3E5
+NOT_ALLOW_PC_SALS: entity work.FLL port map(NOT_ALLOW_PC_SALS_Set,not T3,N_ALLOW_PC_SALS); -- AB3F6,AB3D7,AB3E5
 sALLOW_PC_SALS <= not N_ALLOW_PC_SALS;
 ALLOW_PC_SALS <= sALLOW_PC_SALS;
 
diff --git a/FMD2030_5-07B1.vhd b/FMD2030_5-07B1.vhd
index 6c533ec..6eb7328 100644
--- a/FMD2030_5-07B1.vhd
+++ b/FMD2030_5-07B1.vhd
@@ -89,20 +89,20 @@ sMACH_RST_PROTECT <= MACH_RST_SW; -- AA3H3
 MACH_RST_PROTECT <= sMACH_RST_PROTECT;
 LATCH_MN <= MACH_RESET_SET_LCH_DLY or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1D4
 LATCH_MN_ST3 <= sMACH_RST_PROTECT or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1E4
-REG_M: entity PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN,sMN(0 to 7)); -- AA1D2
+REG_M: entity work.PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN,sMN(0 to 7)); -- AA1D2
 REG_MP: entity PH port map(M_ASSM_BUS(8),LATCH_MN,M_P); -- AA1D2
-REG_N: entity PHV8 port map(N_ASSM_BUS(0 to 7),LATCH_MN,sMN(8 to 15) ); -- AA1D3
+REG_N: entity work.PHV8 port map(N_ASSM_BUS(0 to 7),LATCH_MN,sMN(8 to 15) ); -- AA1D3
 REG_NP: entity PH port map(N_ASSM_BUS(8),LATCH_MN,N_P); -- AA1D3
-REG_MST3: entity PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN_ST3,MN_ST3(0 to 7)); -- AA1D5
+REG_MST3: entity work.PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN_ST3,MN_ST3(0 to 7)); -- AA1D5
 REG_MST3P: entity PH port map(M_ASSM_BUS(8),LATCH_MN_ST3,M_ST3_P); -- AA1D5
-REG_NST3: entity PHV8 port map(N_ASSM_BUS(0 TO 7),LATCH_MN_ST3,MN_ST3(8 to 15)); -- AA1D6
+REG_NST3: entity work.PHV8 port map(N_ASSM_BUS(0 TO 7),LATCH_MN_ST3,MN_ST3(8 to 15)); -- AA1D6
 REG_NST3P: entity PH port map(N_ASSM_BUS(8),LATCH_MN_ST3,N_ST3_P); -- AA1D6
 
 STACK_ADDR_REG_SET <= CHNL_RD_CALL or (CPU_RD_PWR and T1) or GT_MAN_SET_MN or sMACH_RST_PROTECT; -- BE3H7
 SA_REG_IN1 <= "111" & M_ASSM_BUS(0 to 4) when MAIN_STORAGE_CP='1' else "00000000"; -- PE3J6
 SA_REG_IN2 <= XXH & XL & XH & N_ASSM_BUS(0 to 4) when MPX_CP='1' else "00000000"; -- PE3J6
 SA_REG_IN <= SA_REG_IN1 or SA_REG_IN2; -- PE3J6
-REG_SA: entity PHV8 port map(SA_REG_IN,STACK_ADDR_REG_SET,SA_REG); -- PE3J6
+REG_SA: entity work.PHV8 port map(SA_REG_IN,STACK_ADDR_REG_SET,SA_REG); -- PE3J6
 
 MN <= sMN;
 EARLY_M0 <= M_ASSM_BUS(0);
diff --git a/FMD2030_5-07B2.vhd b/FMD2030_5-07B2.vhd
index d4ceac9..2aa3247 100644
--- a/FMD2030_5-07B2.vhd
+++ b/FMD2030_5-07B2.vhd
@@ -43,6 +43,7 @@ USE ieee.std_logic_unsigned.all;
 library work;
 use work.Gates_package.all;
 use work.Buses_package.all;
+-- use work.all;
 
 ENTITY SReg IS
 port
@@ -99,7 +100,7 @@ CS_1XXX <= '1' when CS(0)='1' else '0';
 GT_CS_OPT_Set <= SA and P1;
 GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
 -- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
-GT_CS_OPT: entity FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5
+GT_CS_OPT: entity work.FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5
 GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
 BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5  Could be" GT_CS_BASIC_DECODER and not CS(0)"
 sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5  Could be "GT_CS_BASIC_DECODER and CS(0)"
diff --git a/FMD2030_5-08A1.vhd b/FMD2030_5-08A1.vhd
index 36508a7..a518f35 100644
--- a/FMD2030_5-08A1.vhd
+++ b/FMD2030_5-08A1.vhd
@@ -43,6 +43,7 @@ use IEEE.STD_LOGIC_1164.ALL;
 -- use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use work.Gates_package.all;
+use work.all;
 
 entity Clock is Port (
 				-- Clock stuff
@@ -77,7 +78,7 @@ signal OSC2,OSC,M_DLYD_OSC,DLYN_OSC,T1A,T2A,T3A,T4A,OSC2_DLYD : STD_LOGIC := '0'
 -- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4);
 signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001";
 signal P1D,P2D,P3D,P4D : STD_LOGIC;
-signal OSC_T_LINEA, CLOCK_ONA, CLOCK_OFFA, P_CONV_OSCA,M_CONV_OSC_2A : STD_LOGIC;
+signal OSC_T_LINEA, CLOCK_ONA, CLOCK_OFFA, P_CONV_OSCA,M_CONV_OSC_2A, N_OSC : STD_LOGIC;
 
 begin
 -- Divide the 50MHz FPGA clock down
@@ -86,6 +87,7 @@ begin
 -- OSC2 is actually double the original oscillator (5.33MHz) as only one edge is used
 DIVIDER_MAX <= RatioSlow when Sw_Slow='1' else RATIOFast;
 OSC2 <= '1' when DIVIDER > '0' & DIVIDER_MAX(DIVIDER_MAX'left downto 1) else '0';
+N_OSC <= not OSC;
 
 process (CLOCK_IN)
 	begin
@@ -153,8 +155,8 @@ process (OSC2, MACH_RST_3, CLOCK_START)
 end process;
 
 OSC_T_LINEA <= OSC; -- AC1B6
-OSC_T_LINED : FDCE port map(D=>OSC_T_LINEA,Q=>OSC_T_LINE,CE=>'1',C=>CLOCK_IN);
-M_CONV_OSCD : FDCE port map(D=>not OSC,Q=>M_CONV_OSC,CE=>'1',C=>CLOCK_IN); -- AC1C6
+OSC_T_LINED : FDCE port map(D=>OSC_T_LINEA,Q=>OSC_T_LINE,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+M_CONV_OSCD : FDCE port map(D=>N_OSC,Q=>M_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0'); -- AC1C6
 M_DLYD_OSC <= not OSC; -- AC1C6
 DLYN_OSC <= OSC; -- AC1C6
 
@@ -173,22 +175,22 @@ T2A <= P1D and P2D;
 T3A <= P2D and P3D;
 T4A <= P3D and P4D;
 
-T1D : FDCE port map(D=>T1A,Q=>T1,CE=>'1',C=>CLOCK_IN);
-T2D : FDCE port map(D=>T2A,Q=>T2,CE=>'1',C=>CLOCK_IN);
-T3D : FDCE port map(D=>T3A,Q=>T3,CE=>'1',C=>CLOCK_IN);
-T4D : FDCE port map(D=>T4A,Q=>T4,CE=>'1',C=>CLOCK_IN);
-P1C : FDCE port map(D=>P1D,Q=>P1,CE=>'1',C=>CLOCK_IN);
-P2C : FDCE port map(D=>P2D,Q=>P2,CE=>'1',C=>CLOCK_IN);
-P3C : FDCE port map(D=>P3D,Q=>P3,CE=>'1',C=>CLOCK_IN);
-P4C : FDCE port map(D=>P4D,Q=>P4,CE=>'1',C=>CLOCK_IN);
+T1D : FDCE port map(D=>T1A,Q=>T1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+T2D : FDCE port map(D=>T2A,Q=>T2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+T3D : FDCE port map(D=>T3A,Q=>T3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+T4D : FDCE port map(D=>T4A,Q=>T4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+P1C : FDCE port map(D=>P1D,Q=>P1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+P2C : FDCE port map(D=>P2D,Q=>P2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+P3C : FDCE port map(D=>P3D,Q=>P3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
+P4C : FDCE port map(D=>P4D,Q=>P4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
 
 CLOCK_ONA <= CLK(1) or CLK(2) or CLK(3);
-CLOCK_OND : FDCE port map(D=>CLOCK_ONA,Q=>CLOCK_ON,CE=>'1',C=>CLOCK_IN);
+CLOCK_OND : FDCE port map(D=>CLOCK_ONA,Q=>CLOCK_ON,CE=>'1',C=>CLOCK_IN,CLR=>'0');
 CLOCK_OFFA <= not CLOCK_ONA;
-CLOCK_OFFD : FDCE port map(D=>CLOCK_OFFA,Q=>CLOCK_OFF,CE=>'1',C=>CLOCK_IN);
+CLOCK_OFFD : FDCE port map(D=>CLOCK_OFFA,Q=>CLOCK_OFF,CE=>'1',C=>CLOCK_IN,CLR=>'0');
 P_CONV_OSCA <= OSC and CLOCK_OFFA;
-P_CONV_OSCD : FDCE port map(D=>P_CONV_OSCA,Q=>P_CONV_OSC,CE=>'1',C=>CLOCK_IN);
+P_CONV_OSCD : FDCE port map(D=>P_CONV_OSCA,Q=>P_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0');
 M_CONV_OSC_2A <= not(P_CONV_OSCA);
-M_CONV_OSC_2D : FDCE port map(D=>M_CONV_OSC_2A,Q=>M_CONV_OSC_2,CE=>'1',C=>CLOCK_IN);
+M_CONV_OSC_2D : FDCE port map(D=>M_CONV_OSC_2A,Q=>M_CONV_OSC_2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
 
 end FMD;
diff --git a/FMD2030_5-10D.vhd b/FMD2030_5-10D.vhd
index 932446f..4acd779 100644
--- a/FMD2030_5-10D.vhd
+++ b/FMD2030_5-10D.vhd
@@ -41,6 +41,7 @@ USE ieee.std_logic_unsigned.all;
 library work;
 use work.Gates_package.all;
 use work.Buses_package.all;
+use work.all;
 
 ENTITY n1050_ATTACH IS
 
diff --git a/FMD2030_UDC3.vhd b/FMD2030_UDC3.vhd
index a049035..12e2510 100644
--- a/FMD2030_UDC3.vhd
+++ b/FMD2030_UDC3.vhd
@@ -172,7 +172,7 @@ M_ASSM_BUS <= (others=>'0');
 N_ASSM_BUS <= (others=>'0');
 
 -- Fig 5-09C
-n1050_TRANSLATE : entity n1050_TRANSLATE port map(
+n1050_TRANSLATE : entity work.n1050_TRANSLATE port map(
 		-- Inputs        
 		DATA_REG_BUS => DATA_REG_BUS,
 		RDR_ON_LCH => RDR_ON_LCH,
@@ -218,7 +218,7 @@ n1050_TRANSLATE : entity n1050_TRANSLATE port map(
 		);
 		
 -- Fig 5-10A
-n1050_CLOCK : entity n1050_CLOCK port map (
+n1050_CLOCK : entity work.n1050_CLOCK port map (
 		-- Inputs        
 		WRITE_LCH => WRITE_LCH, -- 09CD2
 		READ_OR_READ_INQ => RD_OR_RD_INQ, -- 09CC5
@@ -239,7 +239,7 @@ n1050_CLOCK : entity n1050_CLOCK port map (
 		);
 		
 -- Fig 5-10B
-n1050_TAGS : entity n1050_TAGS port map (
+n1050_TAGS : entity work.n1050_TAGS port map (
 		-- Inputs
 		RD_OR_RD_INQ => RD_OR_RD_INQ, -- 09CC5
 		Y_TIME => Y_TIME, -- 10AXX
@@ -319,7 +319,7 @@ TT6_POS_ATTN <= sTT6_POS_ATTN;
 n1050_OP_IN <= sn1050_OP_IN;
 
 -- Fig 5-10C
-n1050_DATA : entity n1050_DATA port map (
+n1050_DATA : entity work.n1050_DATA port map (
 		-- Inputs        
 		E_SW_SEL_BUS => E_SW_SEL_BUS,
 		USE_MANUAL_DECODER => USE_MANUAL_DECODER,
@@ -406,7 +406,7 @@ n1050_DATA : entity n1050_DATA port map (
 n1050_INTRV_REQ <= sn1050_INTRV_REQ;
 
 -- Fig 5-10D
-n1050_ATTACH : entity n1050_ATTACH port map (
+n1050_ATTACH : entity work.n1050_ATTACH port map (
 		-- Inputs        
 		-- CE Cable
 		CE_CABLE_IN => open,
diff --git a/ibm2030.vhd b/ibm2030.vhd
index b038147..93213f2 100644
--- a/ibm2030.vhd
+++ b/ibm2030.vhd
@@ -76,6 +76,11 @@ entity ibm2030 is
 				-- Video output
 				vga_r,vga_g,vga_b,vga_hs,vga_vs : out std_logic; -- VGA output RGB+Sync
 				
+				-- Panel lights output
+				MAX7219_CLK,MAX7219_LOAD,MAX7219_DIN : out std_logic;
+				-- MAX6951 is charlieplexed LED mux (miniature panel)
+				MAX6951_CLK,MAX6951_CS0,MAX6951_CS1,MAX6951_CS2,MAX6951_CS3,MAX6951_DIN : out std_logic;
+				
 			  -- Static RAM interface
 			  sramaddr : out std_logic_vector(17 downto 0);
 			  srama : inout std_logic_vector(8 downto 0);
@@ -141,6 +146,18 @@ signal	IND_MAN : STD_LOGIC;
 signal	IND_WAIT : STD_LOGIC;
 signal	IND_TEST : STD_LOGIC;
 signal	IND_LOAD : STD_LOGIC;
+signal	IND_LP : STD_LOGIC;
+-- SX
+signal   IND_COUNT : STD_LOGIC_VECTOR(0 to 15) := "0000000000000000";
+signal	IND_COUNT_LP, IND_COUNT_HP : STD_LOGIC := '1';
+signal	IND_SX1_DATA : STD_LOGIC_VECTOR(0 to 7) := "00000000";
+signal	IND_SX1_DATAP : STD_LOGIC := '1';
+signal	IND_SX1_COMMAND: STD_LOGIC_VECTOR(0 to 7) := "00000000";
+signal	IND_SX1_KEY: STD_LOGIC_VECTOR(0 to 3) := "0000";
+signal	IND_SX1_KEYP : STD_LOGIC := '1';
+signal	IND_SX1_PCI, IND_SX1_SKIP, IND_SX1_SLI, IND_SX1_CD, IND_SX1_CC : STD_LOGIC;
+signal	IND_SX1_DA_CHK, IND_SX1_PROT_CHK, IND_SX1_PROG_CHK, IND_SX1_IL_CHK, IND_SX1_CHNLDATA_CHK, IND_SX1_IF_CHK, IND_SX1_CHNLCTRL_CHK : STD_LOGIC;
+signal	IND_SX1_STATIN_TAG, IND_SX1_ADRIN_TAG, IND_SX1_OPIN_TAG, IND_SX1_SUPOUT_TAG, IND_SX1_SERVOUT_TAG, IND_SX1_CMMDOUT_TAG, IND_SX1_ADROUT_TAG, IND_SX1_SELOUT_TAG : STD_LOGIC;
 
 -- Switch inputs to CPU
 signal	SW_START,SW_LOAD,SW_SET_IC,SW_STOP,SW_POWER_OFF : STD_LOGIC;
@@ -179,7 +196,7 @@ signal LED_vector : std_logic_vector(0 to 255);
 
 begin
 
-	cpu : entity cpu port map (
+	cpu : entity work.cpu port map (
 			WX_IND => WX_IND,
 			W_IND_P => W_IND_P,
 			X_IND_P => X_IND_P,
@@ -313,7 +330,7 @@ begin
 		Indicators(  		  1) => IND_SALS.SALS_PN,
 		Indicators(  2 to	  7) => IND_SALS.SALS_CN,
 		Indicators(  		  8) => IND_SALS.SALS_PA,
-		Indicators(			  9) => '0', -- LP
+		Indicators(			  9) => IND_LP,
 		Indicators(			 10) => W_IND_P,
 		Indicators( 11 to	 15) => WX_IND(0 to 4),
 		Indicators(			 16) => X_IND_P,
@@ -404,8 +421,40 @@ begin
 	led(4) <= IND_SYST;
 	led(5) <= '0';
  	led(6) <= '0';
-	led(7) <= DEBUG.Probe;
-	
+	led(7) <= DEBUG.Probe;
+	
+	IND_LP <= SW_LAMP_TEST;
+	
+	-- Temporary Selector Channel indicators
+	IND_COUNT_LP <= '1';
+	IND_COUNT_HP <= '1';
+	IND_COUNT <= (others => SW_LAMP_TEST);
+	IND_SX1_DATA <= (others => SW_LAMP_TEST);
+	IND_SX1_DATAP <= SW_LAMP_TEST;
+	IND_SX1_COMMAND <= (others => SW_LAMP_TEST);
+	IND_SX1_KEY <= (others => SW_LAMP_TEST);
+	IND_SX1_KEYP <= SW_LAMP_TEST;
+	IND_SX1_PCI <= SW_LAMP_TEST;
+	IND_SX1_SKIP <= SW_LAMP_TEST;
+	IND_SX1_SLI <= SW_LAMP_TEST;
+	IND_SX1_CD <= SW_LAMP_TEST;
+	IND_SX1_CC <= SW_LAMP_TEST;
+	IND_SX1_DA_CHK <= SW_LAMP_TEST;
+	IND_SX1_PROT_CHK <= SW_LAMP_TEST;
+	IND_SX1_PROG_CHK <= SW_LAMP_TEST;
+	IND_SX1_IL_CHK <= SW_LAMP_TEST;
+	IND_SX1_CHNLDATA_CHK <= SW_LAMP_TEST;
+	IND_SX1_STATIN_TAG <= SW_LAMP_TEST;
+	IND_SX1_ADRIN_TAG <= SW_LAMP_TEST;
+	IND_SX1_OPIN_TAG <= SW_LAMP_TEST;
+	IND_SX1_SUPOUT_TAG <= SW_LAMP_TEST;
+	IND_SX1_SERVOUT_TAG <= SW_LAMP_TEST;
+	IND_SX1_CMMDOUT_TAG <= SW_LAMP_TEST;
+	IND_SX1_ADROUT_TAG <= SW_LAMP_TEST;
+	IND_SX1_SELOUT_TAG <= SW_LAMP_TEST;
+	IND_SX1_IF_CHK <= SW_LAMP_TEST;
+	IND_SX1_CHNLCTRL_CHK <= SW_LAMP_TEST;
+				
 	frontPanel_switches: entity switches port map (
 	   -- Hardware switch inputs and scan outputs
 		SwA_scan => pa_io5,
@@ -523,7 +572,7 @@ begin
 				12 => WX_IND(1),
 				13 => WX_IND(0),
 				14 => W_IND_P,
-				15 => '0', -- LP
+				15 => IND_LP,
 				16 => WX_IND(12),
 				17 => WX_IND(11),
 				18 => WX_IND(10),
@@ -539,7 +588,7 @@ begin
 				28 => IND_SALS.SALS_CH(2),
 				29 => IND_SALS.SALS_CH(1),
 				30 => IND_SALS.SALS_CH(0),
-				31 => IND_SALS.SALS_PA,
+				31 => IND_SALS.SALS_PS,
 				32 => IND_SALS.SALS_CB(1),
 				33 => IND_SALS.SALS_CB(0),
 				34 => IND_SALS.SALS_CA(3),
@@ -572,11 +621,87 @@ begin
 				61 => IND_SALS.SALS_CF(2),
 				62 => IND_SALS.SALS_CF(1),
 				63 => IND_SALS.SALS_CF(0),
-				-- Count
+				64 => IND_COUNT_HP, -- Count-P
+				65 => IND_SALS.SALS_CS(3),
+				66 => IND_SALS.SALS_CS(2),
+				67 => IND_SALS.SALS_CS(1),
+				68 => IND_SALS.SALS_CS(0),
+				69 => IND_SALS.SALS_SA,
+				70 => IND_SALS.SALS_CC(2),
+				71 => IND_SALS.SALS_CC(1),
+				-- Count 72-87,95
+				72 => IND_COUNT(8),
+				73 => IND_COUNT(6),
+				74 => IND_COUNT(5),
+				75 => IND_COUNT(4),
+				76 => IND_COUNT(3),
+				77 => IND_COUNT(2),
+				78 => IND_COUNT(1),
+				79 => IND_COUNT(0),
+				80 => IND_COUNT(15),
+				81 => IND_COUNT(14),
+				82 => IND_COUNT(13),
+				83 => IND_COUNT(12),
+				84 => IND_COUNT(11),
+				85 => IND_COUNT(10),
+				86 => IND_COUNT(9),
+				87 => IND_COUNT_LP,
+				95 => IND_COUNT(0),
 				-- SX1
-				-- SX2
+				88 => IND_SX1_DATA(5),
+				89 => IND_SX1_DATA(4),
+				90 => IND_SX1_DATA(3),
+				91 => IND_SX1_DATA(2),
+			   92 => IND_SX1_DATA(1),
+				93 => IND_SX1_DATA(0),
+				94 => IND_SX1_DATAP,
+				96 => IND_SX1_COMMAND(4),
+				97 => IND_SX1_KEY(3),
+				98 => IND_SX1_KEY(2),
+				99 => IND_SX1_KEY(1),
+				100 => IND_SX1_KEY(0),
+				101 => IND_SX1_KEYP,
+				102 => IND_SX1_DATA(7),
+				103 => IND_SX1_DATA(6),
+				104 => IND_SX1_PCI,
+				105 => IND_SX1_SKIP,
+				106 => IND_SX1_SLI,
+				107 => IND_SX1_CD,
+				108 => IND_SX1_CC,
+				109 => IND_SX1_COMMAND(7),
+				110 => IND_SX1_COMMAND(6),
+				111 => IND_SX1_COMMAND(5),
+				112 => IND_SX1_DA_CHK,
+				113 => IND_SX1_PROT_CHK,
+				114 => IND_SX1_PROG_CHK,
+				115 => IND_SX1_IL_CHK,
+				116 => IND_SX1_CHNLDATA_CHK,
+				117 => IND_SX1_STATIN_TAG,
+				118 => IND_SX1_ADRIN_TAG,
+				119 => IND_SX1_OPIN_TAG,
+				120 => '0', -- LED5
+				121 => IND_SX1_SUPOUT_TAG,
+				122 => IND_SX1_SERVOUT_TAG,
+				123 => IND_SX1_CMMDOUT_TAG,
+				124 => IND_SX1_ADROUT_TAG,
+				125 => IND_SX1_SELOUT_TAG,
+				126 => IND_SX1_IF_CHK,
+				127 => IND_SX1_CHNLCTRL_CHK,
+				-- SX2 128-150. 162-167
+				
+				-- Temporary indicators 152-159
+				152 => IND_LOAD,
+				153 => IND_TEST,
+				154 => IND_WAIT,
+				155 => IND_MAN,
+				156 => IND_SYST,
+				157 => '1', -- Power
+				158 => '1',
+				159 => '1',
+
 				160 => IND_ADDR_IN,
 				161 => IND_OPNL_IN,
+				-- 162-167 in SX2
 				168 => IND_FO_P,
 				169 => IND_SUPPR_OUT,
 				170 => IND_SERV_OUT,
@@ -675,47 +800,18 @@ begin
 		port map(
 			clk => clk,
 			LEDs => LED_vector,
---			(
---				0 => W_IND_P,
---				0 => IND_SALS.SALS_PA,
---				1 => IND_SALS.SALS_CN(5),
---				2 => IND_SALS.SALS_CN(4),
---				3 => IND_SALS.SALS_CN(3),
---				4 => IND_SALS.SALS_CN(2),
---				5 => IND_SALS.SALS_CN(1),
---				6 => IND_SALS.SALS_CN(0),
---				7 => IND_SALS.SALS_PN,
---				16#01# to 16#0F# => '0',
---				16#10# to 16#1F# => '0',
---				16#20# to 16#2F# => '0',
---				16#30# to 16#3F# => '0',
---				16#40# to 16#4F# => '0',
---				16#50# to 16#5F# => '0',
---				16#60# to 16#6F# => '0',
---				16#70# to 16#7F# => '0',
---				16#80# to 16#8F# => '0',
---				16#90# to 16#9F# => '0',
---				16#A0# to 16#AF# => '0',
---				16#B0# to 16#BF# => '0',
---				16#C0# to 16#CF# => '0',
---				16#D0# to 16#DF# => '0',
---				16#E0# to 16#EF# => '0',
---				16#F0# to 16#FF# => '0'
---				),
+
 			-- MAX7219 is standard LED mux (full-size panel)
-			MAX7219_CLK => open,
-			MAX7219_LOAD => open,
-			MAX7219_DIN0 => open,
-			MAX7219_DIN1 => open,
-			MAX7219_DIN2 => open,
-			MAX7219_DIN3 => open,
+			MAX7219_CLK => MAX7219_CLK,
+			MAX7219_LOAD => MAX7219_LOAD,
+			MAX7219_DIN => MAX7219_DIN,
 			-- MAX6951 is charlieplexed LED mux (miniature panel)
-			MAX6951_CLK => open,
-			MAX6951_CS0 => open,
-			MAX6951_CS1 => open,
-			MAX6951_CS2 => open,
-			MAX6951_CS3 => open,
-			MAX6951_DIN => open
+			MAX6951_CLK => MAX6951_CLK,
+			MAX6951_CS0 => MAX6951_CS0,
+			MAX6951_CS1 => MAX6951_CS1,
+			MAX6951_CS2 => MAX6951_CS2,
+			MAX6951_CS3 => MAX6951_CS3,
+			MAX6951_DIN => MAX6951_DIN
 			);
 		
 		DEBUG.Selection <= CONV_INTEGER(unsigned(SW_J));