{\rtf1\ansi\ansicpg1252\deff0 {\fonttbl {\f0\fnil\fcharset0\fprq0\fttruetype Courier New;} {\f1\fnil\fcharset0\fprq0\fttruetype NULL;} {\f2\fnil\fcharset0\fprq0\fttruetype Dingbats;} {\f3\fnil\fcharset0\fprq0\fttruetype Symbol;} {\f4\fnil\fcharset0\fprq0\fttruetype Times New Roman;} {\f5\fnil\fcharset0\fprq0\fttruetype Arial;}} {\colortbl \red0\green0\blue0; \red255\green255\blue255;} {\stylesheet {\s7\sl240\slmult1\f4\fs24 Default;} {\s18\sl240\slmult1\fi-431\li720\sbasedon19 Lower Roman List;} {\s20\sl240\slmult1\tx431\sbasedon10\snext19 Numbered Heading 1;} {\s21\sl240\slmult1\tx431\sbasedon11\snext19 Numbered Heading 2;} {\s8\sl240\slmult1\fi-431\li720 Diamond List;} {\s22\sl240\slmult1\tx431\sbasedon12\snext19 Numbered Heading 3;} {\s23\sl240\slmult1\fi-431\li720 Numbered List;} {\s10\sl240\slmult1\sb440\sa60\f5\fs34\b\sbasedon19\snext19 Heading 1;} {\s27\sl240\slmult1\fi-431\li720 Square List;} {\s6\sl240\slmult1\fi-431\li720 Dashed List;} {\s29\sl240\slmult1\sa117\f4\fs24\sbasedon7 Text body;} {\s13\sl240\slmult1\fi-431\li720 Heart List;} {\s33\sl240\slmult1\fi-431\li720\sbasedon23 Upper Roman List;} {\s25\sl240\slmult1\f0\fs20\sbasedon7 Preformatted Text;} {\s4\sl240\slmult1\sb117\sa117\f4\fs20\i\sbasedon7 Caption;} {\s31\sl240\slmult1\fi-431\li720 Triangle List;} {\s32\sl240\slmult1\fi-431\li720\sbasedon23 Upper Case List;} {\s3\sl240\slmult1\fi-431\li720 Bullet List;} {\s9\sl240\slmult1\fi-431\li720 Hand List;} {\s26\sl240\slmult1\tx1584\sbasedon20\snext19 Section Heading;} {\s11\sl240\slmult1\sb440\sa60\f5\fs28\b\sbasedon19\snext19 Heading 2;} {\s12\sl240\slmult1\sb440\sa60\f5\fs24\b\sbasedon19\snext19 Heading 3;} {\s30\sl240\slmult1\fi-431\li720 Tick List;} {\s19\sl240\slmult1\f4\fs24 Normal;} {\s17\sl240\slmult1\fi-431\li720\sbasedon23 Lower Case List;} {\s1\sl240\slmult1\li1440\ri1440\sa117\sbasedon19 Block Text;} {\s16\sl240\slmult1\f4\fs24\sbasedon29 List;} {\s15\sl240\slmult1\f4\fs24\sbasedon7 Index;} {\s14\sl240\slmult1\fi-431\li720 Implies List;} {\s2\sl240\slmult1\fi-431\li720 Box List;} {\s28\sl240\slmult1\fi-431\li720 Star List;} {\s24\sl240\slmult1\f0\sbasedon19 Plain Text;} {\s5\sl240\slmult1\tx1584\sbasedon20\snext19 Chapter Heading;}} \kerning0\cf0\viewkind1\paperw23811\paperh16837\margl1440\margr1440\landscape\widowctl \sectd\sbknone\colsx360\margtsxn720\margbsxn720\pgncont\ltrsect \pard\plain\ltrpar\s19\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}QD061 0 1 2 3 4 5 6 7 8 9} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} \par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} The CCW addr fetch and update routine is used only during this CCW is to be skipped and the next CCW executed. In} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} chaining. It fetches the CCW addr from local storage, this case, eight must be added to the CCW addr to get the} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}A updates it and restores it for future chaining. Normally addr of the CCW which is to be executed and an additional} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} the CCW addr as fetched is the addr of the CCW. Eight is eight to get the next CCW addr.} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} added to it and stored as the next CCW addr. There is one} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} exception, and that is while doing a CC. If a Device End} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} with a status modifier is received from the control unit,} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} \par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} \par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 00 014 093C 00 014 0940 01 014 0941 00 014 0944 01 014 0945 01 014 094D } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} K 0111,0 | K 1000 | K 1000 | K 0110,1 | | | | | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} A 0>S | A R+KL>RC | A R-KL+1>V | A GT>Z | A R+0+1>R | A R-0>U | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C QD091.JGE------------*S *8F LS S*------| |*------S WRITE |*--O---S *8E LS S*--O---| |*------S WRITE |*O------------------------------------------------------------------------------QD051------CFE} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (00) C 1>S0 | C HZ>S4 | C ANSNZ>S2 | | C LZ>S5 | | | | C ANSNZ>S2 | | (10)} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr Ch | 014V ----| 014V | 014V --+---| 014V | | 014V | 014V | Selr Ch CD} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} CCW addr R 0,0 40R | R 0,1 41R R S0,0 44R | | R AC,1 45R | R 0,1 4DR R S0,S5 08R | CCW fetch} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} fetch CD C1-- 00 --CA | C2-- 01 --CB C3-- *0 --CC | | C4-- *1 --CD | C5-- 01 --CE C6-- ** --CF | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} waiting | Low CCW addr+8 | | CC=test Op In | High CCW addr | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D | | | | | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 00 014 093E | 10 014 0942 11 014 0943 | | 10 014 0946 | 11 014 0947 11 014 094F | 01 014 0909 11 014 0937 } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} K 0111,0 | | K 0001 | K 1000 | | | K 0110,1 | | | | | | | K 0101,1 | K 1100,0 | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | A R+KH>RC | A R-KL+1>V | | | | | | A R+0+C>RC | A R>U | | | | | | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}E QD091.JJE---------O--*S *8F LS S*--O---| |*------S WRITE |*- ----S *8E LS S---O---| |*------S WRITE |-O-----S *8D LS S*------S WRITE GR S*-----------------------------------QD051------EHE} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (10) | C 0>S2 | | | C HZ>S4 | | | | | C ANSNZ>S2 | | | | C K>GA | Selr Ch CC} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} QD111.EHE---------- | 014V | 014V | 014V | 014V | 014V | 014V | ----| 014V | 014V CCW fetch} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (10) R S1,0 40R R 1,1 43R R 0,0 44R R AC,1 45R R 1,1 4FR R S0,S5 08R | | R 1,1 37R R 1,0 72R } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr Ch E1-- *0 --EA E2-- 11 --EB E3-- 00 --EC E4-- *1 --ED E5-- 11 --EE E6-- ** --EF | | E7-- 11 --EG E8-- 10 --EH } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} CCW addr Fetch low Low CCW addr+16 V=low CCW addr CDA High CCW addr+ U=high CCW addr | | CC-Op In down Addr Out} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F fetch CCW addr Store next low Fetch high CCW addr carry Store next high | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} CCW addr CCW addr | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S2=0=high CCW | | 00 014 0908 } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S2=0=low CCW addr is 00 addr is 00 | | K 1111 | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S4=1=low CCW addr is 00 or 08 | | A GTL+K>R | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G --+---| |*---} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 014V |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | R 0,0 48R |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | G7-- 00 --GG |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | CC-Op In up |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H | Test Op In |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 11 014 090B | 00 014 0948 } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 1111 | ----| | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A GTL+K>Z | A R+0+1>R | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}J O---| |*--O---| |*---} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 014V | | 014V |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | R AC,0 48R | R AC,1 09R |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | J7-- *0 --JG | J8-- *1 --JH |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | Test Op In,Adr In | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K | and StaIn | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ----------------------+----------------------} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 00 014 094C} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 1000 |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A 0+KH>R | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}L --------------------------------------------- ----| |*-------------QD161------LJE} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | C 0>S4,S5 | (10)} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | 014V Selr Ch} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | R 1,0 2AR Inf Ctrl Chk} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | L9-- 10 --LJ} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | R=Cat. Num 80} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}M | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | ----------------------- |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 10 014 094A | 11 014 094B | 01 014 0949 | 10 014 094E} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 0111,0 | | K 1111 | ----| | | K 0110,1 |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A V-KL>RC | | A V-KL>RC | | | | A V-0+C>RC | } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}N ----S *8F LS S*--O---| |*------S STORE |*--O---S *8E LS S*---} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C 1>S0 | | | C 0>S0 | | | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 014V | 014V ----| 014V | 014V |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R S1,1 49R R 0,1 49R | R S0,0 4CR R 0,1 49R |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} N6-- *1 --NF N7-- 01 --NG | N8-- *0 --NH N9-- 01 --NJ |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Time-out Jumped | Store corrected R=high CCW addr |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}P R=low CCW addr-8 R=low CCW addr-16 | CCW addr 1 or 0 |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ---------------------------------------------} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} If doing CD, this routine then goes to the CCW fetch} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} routine. If doing CC, this routine checks that Op In and} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Q Status In has dropped and then starts the Unit Selection.} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} If the interface does not clear, the CCW address must be} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} corrected and the routine then goes to the error routine} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} and indicates an Interface Control check.} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} } \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S2,S4 will be used to determine if this CCW adder was} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R obtained by a storage wrap of a 64k storage and indicate} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} a program check if storage wrap did occur. While} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} chaining, a program check is indicated when the CCW addr} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} is 0000 and also when a jump has occurred and the CCW} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} addr is 000X.} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} \par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} D} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 0} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 6 | 128055 02/10/66 | Mach 2030 | Date 10/12/66 Sheet 1 QD061 |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 1 | 128061 10/06/66 | Name | Log 2245 Version 014 |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | Mode Manual | |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | P.N. 837192 | Selr CHannel CCW addr |} \par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | IBM Corp. | fetch and update |} \par\pard\plain\ltrpar\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}}}