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239 lines
9.6 KiB
VHDL
239 lines
9.6 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-04C.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- Manual Data (E switch) & C,F,H registers
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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-- Revision 1.01 2012-04-07
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-- Fix typo in comment
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY ManualDataCFH IS
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port
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(
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-- Inputs
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MACH_RST_PROT : IN STD_LOGIC; -- 07B
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USE_MAN_DECO_PWR : IN STD_LOGIC; -- 03D
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N60_CY_TIMER_PULSE : IN STD_LOGIC; -- 14A
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L_REGISTER : IN STD_LOGIC_VECTOR(0 to 7); -- 05C
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MACH_RST_SW : IN STD_LOGIC; -- 03D
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EXT_TRAP_MASK_ON : IN STD_LOGIC; -- 08C
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USE_MAN_DECODER, USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
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USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
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USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A
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GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
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CK_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
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GT_CK_DECO : IN STD_LOGIC; -- 03B
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Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
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Z_BUS_P : IN STD_LOGIC;
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MACH_RST_2B : IN STD_LOGIC; -- 06B
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MAN_STOR_PWR : IN STD_LOGIC; -- 03D
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CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
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RECYCLE_RST : IN STD_LOGIC; -- 04A
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-- Switches
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SW_INTRP_TIMER : IN STD_LOGIC;
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SW_CONS_INTRP : IN STD_LOGIC;
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SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
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SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
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-- Outputs
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ABCD_SW_BUS,FGHJ_SW_BUS : OUT STD_LOGIC_VECTOR(0 to 15);
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AB_SW_P,CD_SW_P,FG_SW_P,HJ_SW_P : OUT STD_LOGIC;
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IJ_SEL,UV_SEL : OUT STD_LOGIC;
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TIMER_UPDATE : OUT STD_LOGIC; -- 02A
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TIMER_UPDATE_OR_EXT_INT : OUT STD_LOGIC; -- 02A
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EXT_INTRP : OUT STD_LOGIC; -- 02A
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A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
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H_REG_BITS : OUT STD_LOGIC_VECTOR(0 to 7); -- 03B,03A
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H_REG_P : OUT STD_LOGIC; -- 03B,03A
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H_REG_6 : OUT STD_LOGIC;
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H_REG_5_PWR : OUT STD_LOGIC; -- 02A,08B
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GT_1050_TAGS : OUT STD_LOGIC; -- 10C
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GT_1050_BUS : OUT STD_LOGIC; -- 10C
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CD_REG_2 : OUT STD_LOGIC; -- 05C
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-- E switch
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E_SW : IN E_SW_BUS_Type;
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DEBUG : INOUT DEBUG_BUS;
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-- Clocks
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T1,T2,T3,T4 : IN STD_LOGIC;
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clk : IN STD_LOGIC
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);
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END ManualDataCFH;
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ARCHITECTURE FMD OF ManualDataCFH IS
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signal RST_COUNTER : STD_LOGIC;
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signal N10MSPULSE : STD_LOGIC;
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signal BIN_DRIVE : STD_LOGIC;
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signal CTRL_TRG : STD_LOGIC;
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signal CTRL_LCH : STD_LOGIC;
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signal CNTR_FULL : STD_LOGIC;
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signal C_BINARY_CNTR : STD_LOGIC_VECTOR(4 to 7);
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signal EXT_INT : STD_LOGIC;
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signal RESET_F_REG : STD_LOGIC;
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signal F_REGISTER : STD_LOGIC_VECTOR(0 to 7);
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signal F_REGISTER_1A : STD_LOGIC;
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signal SET_F_REG_0 : STD_LOGIC;
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signal GT_C_TO_A_BUS : STD_LOGIC;
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signal GT_F_TO_A : STD_LOGIC;
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signal GT_H_TO_A : STD_LOGIC;
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signal C_EXT_INT : STD_LOGIC_VECTOR(2 to 7);
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signal H_SET : STD_LOGIC;
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signal sTIMER_UPDATE : STD_LOGIC;
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signal sH_REG_BITS : STD_LOGIC_VECTOR(0 to 7);
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signal sH_REG_P : STD_LOGIC;
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signal CTL_LCH_Set,CTL_LCH_Reset,CT_FF_Set,BD_FF_Set,EI_LCH_Set,EI_LCH_Reset,F0_LCH_Reset,F1_LCH_Set,F1A_LCH_Reset : STD_LOGIC;
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signal F07_LCH_Reset,F07_LCH_Set : STD_LOGIC_VECTOR(0 to 7);
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BEGIN
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-- Fig 5-04C
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-- Rotary switches ABCD and FGHJ
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ABCD_SW_BUS <= SW_A & SW_B & SW_C & SW_D;
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AB_SW_P <= SW_AP xnor SW_BP; -- AC1D2,AC1E3
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CD_SW_P <= SW_CP xnor SW_DP; -- AC1D4,AC1E3,AC1D2
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FGHJ_SW_BUS <= SW_F & SW_G & SW_H & SW_J;
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FG_SW_P <= SW_FP xnor SW_GP; -- AC1D4,AC1E3,AC1D2
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HJ_SW_P <= SW_HP xnor SW_JP; -- AC1D4,AC1E3,AC1D2
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IJ_SEL <= '1' when (E_SW.I_SEL='1' or E_SW.J_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
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UV_SEL <= '1' when (E_SW.U_SEL='1' or E_SW.V_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
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RST_COUNTER <= MACH_RST_PROT; -- BE3G5
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CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (not sTIMER_UPDATE and SW_INTRP_TIMER);
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-- CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (sTIMER_UPDATE and SW_INTRP_TIMER);
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CTL_LCH_Reset <= CTRL_TRG and T3;
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CTL_LCH: entity work.FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5
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N10MSPULSE <= not(N60_CY_TIMER_PULSE and not T3); -- 10ms monostable here
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CT_FF_Set <= CTRL_LCH and T4;
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CT_FF: entity work.FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6
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BD_FF_Set <= not CTRL_LCH and T3 and N10MSPULSE and not CNTR_FULL; -- Not T2 as per MDM (refer FETOM)
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BD_FF: entity work.FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6
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process(BIN_DRIVE,RST_COUNTER,CTRL_TRG) -- BE3G7,BE3F7
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begin
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if RST_COUNTER='1' or CTRL_TRG='1' then
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C_BINARY_CNTR <= "0000";
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else if BIN_DRIVE'event and BIN_DRIVE='0' then
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C_BINARY_CNTR <= C_BINARY_CNTR + "0001";
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end if;
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end if;
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end process;
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CNTR_FULL <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6
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-- Interrupt generation
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sTIMER_UPDATE <= C_BINARY_CNTR(4) or C_BINARY_CNTR(5) or C_BINARY_CNTR(6) or C_BINARY_CNTR(7); -- BE3G6,BE3G5
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TIMER_UPDATE <= sTIMER_UPDATE and EXT_TRAP_MASK_ON; -- Modified to include EXT_TRAP_MASK_ON for timer as well
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-- TIMER_UPDATE <= sTIMER_UPDATE;
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TIMER_UPDATE_OR_EXT_INT <= (sTIMER_UPDATE and EXT_TRAP_MASK_ON) or EXT_INT; -- AC1D5 Modified to include EXT_TRAP_MASK_ON for timer as well
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-- TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporarily prevent Timer
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EXT_INT <= (F_REGISTER(0) or F_REGISTER(1) or F_REGISTER(2) or F_REGISTER(3) or
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F_REGISTER(4) or F_REGISTER(5) or F_REGISTER(6) or F_REGISTER(7)) and EXT_TRAP_MASK_ON; -- AC1G2 ?? Should this include EXT_TRAP_MASK_ON ?
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EI_LCH_Reset <= MACH_RST_SW or RESET_F_REG;
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EI_LCH_Set <= EXT_INT and T3; -- ?? Seems to be needed, not as per MDM
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EI_LCH: entity work.FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2
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-- F register - here it is held in True polarity, in the 2030 it is inverted
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C_EXT_INT <= "000000";
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SET_F_REG_0 <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1111
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RESET_F_REG <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and not CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1110
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F1A_LCH_Reset <= (L_REGISTER(1) and RESET_F_REG) or RECYCLE_RST;
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F1_LCH_Set <= F_REGISTER_1A and SW_CONS_INTRP;
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F1A_LCH: entity work.FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2
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F07_LCH_Set <= SET_F_REG_0 & F1_LCH_Set & C_EXT_INT(2 to 7);
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F07_LCH_Reset <= (0 to 7 => RECYCLE_RST) or ((0 to 7 => RESET_F_REG) and ('1' & L_REGISTER(1 to 7)));
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F07_LCH: entity work.FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2
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-- H register
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H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or
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(T4 and not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3)); -- AB1J2 CD=0101
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GT_1050_TAGS <= not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and not CD_CTRL_REG(3); -- AB1B3 CD=0100
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GT_1050_BUS <= not CD_CTRL_REG(0) and not CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3); -- AB1B3 CD=0001
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CD_REG_2 <= CD_CTRL_REG(2); -- AB1B3
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H_LCH: entity work.PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3
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H_REG_BITS <= sH_REG_BITS;
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HP_LCH: entity work.PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3
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H_REG_P <= sH_REG_P;
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H_REG_6 <= sH_REG_BITS(6); -- AB1C6,AB1G2
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H_REG_5_PWR <= sH_REG_BITS(5); -- AB1L2
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-- A bus drive
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GT_C_TO_A_BUS <= (E_SW.C_SEL and USE_MAN_DECODER) or
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(not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0100
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GT_F_TO_A <= (E_SW.F_SEL and USE_MAN_DECO_PWR) or
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(not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0000
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GT_H_TO_A <= (E_SW.H_SEL and USE_MAN_DECODER) or
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(not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3) and USE_BASIC_CA_DECODER); -- AB3C7 CA=0101
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A_BUS <= not ("0000" & C_BINARY_CNTR & '0') when GT_C_TO_A_BUS='1'
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else (F_REGISTER & '0') when GT_F_TO_A='1' -- ?? F_REGISTER should be inverted?
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else not (sH_REG_BITS & sH_REG_P) when GT_H_TO_A='1'
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else "111111111"; -- AB1F6
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with DEBUG.Selection select
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DEBUG.Probe <=
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C_BINARY_CNTR(7) when 0,
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C_BINARY_CNTR(6) when 1,
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C_BINARY_CNTR(5) when 2,
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C_BINARY_CNTR(4) when 3,
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N10MSPULSE when 4,
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CNTR_FULL when 5,
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CTRL_LCH when 6,
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CTRL_TRG when 7,
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BIN_DRIVE when 8,
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RST_COUNTER when 9,
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N60_CY_TIMER_PULSE when 10,
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CTL_LCH_Set when 11,
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CTL_LCH_Reset when 12,
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BD_FF_Set when 13,
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EXT_INT when 14,
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sTIMER_UPDATE when 15;
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END FMD;
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