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160 lines
6.3 KiB
VHDL
160 lines
6.3 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-04D.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- Read/Write Storage Controls
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY RWStgCntl IS
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port
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(
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-- Inputs
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SALS : IN SALS_Bus;
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ANY_PRIORITY_PULSE,ANY_PRIORITY_PULSE_2 : IN STD_LOGIC; -- 03A
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SEL_SHARE_HOLD : IN STD_LOGIC; -- 12D
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G_REG_0_BIT,G_REG_1_BIT : IN STD_LOGIC; -- 05C
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N1401_MODE : IN STD_LOGIC; -- 05A
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USE_CPU_DECODER : IN STD_LOGIC; -- 05C
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USE_MAN_DECODER : IN STD_LOGIC; -- 03D
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E_SW_SEL_AUX_STG : IN STD_LOGIC; -- 04C
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MEM_SEL : IN STD_LOGIC; -- 03D
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ALLOW_WRITE,ALLOW_WRITE_2 : IN STD_LOGIC; -- 03D
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SEL_RD_WR_CTRL : IN STD_LOGIC; -- 12C
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MAN_STOR_OR_DISPLAY : IN STD_LOGIC; -- 03D
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MACH_RST_1 : IN STD_LOGIC; -- 03D
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MANUAL_RD_CALL,MANUAL_WR_CALL : IN STD_LOGIC; -- 03D
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HSMPX_READ_CALL : IN STD_LOGIC; -- ?
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SEL_RD_CALL_TO_STP : IN STD_LOGIC; -- 12C
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SELECT_CPU_BUMP : IN STD_LOGIC; -- 08B
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-- Outputs
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USE_ALT_CU_DECODE : OUT STD_LOGIC; -- 01B
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USE_GR_OR_HR : OUT STD_LOGIC; -- 12D,14D
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USE_R : OUT STD_LOGIC; -- 06C,03D
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CPU_WRITE_IN_R_REG : OUT STD_LOGIC; -- 07A
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CPU_WRITE_PWR : OUT STD_LOGIC; -- 03D,12D,03D,05D
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COMPUTE : OUT STD_LOGIC; -- 01C
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CPU_READ_PWR : OUT STD_LOGIC; -- 07B,03D,05D
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FORCE_M_REG_123 : OUT STD_LOGIC; -- 05B,08B
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CU_DECODE_UCW : OUT STD_LOGIC; -- 05B
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MAIN_STORAGE_CP : OUT STD_LOGIC; -- 07B,05Bm08B
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LOCAL_STORAGE_CP : OUT STD_LOGIC; -- 07A
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MAIN_STORAGE : OUT STD_LOGIC; -- 03B,06C,04B,06C,07A,08B
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EARLY_LOCAL_STG : OUT STD_LOGIC; -- 05D
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GT_LOCAL_STG : OUT STD_LOGIC; -- 08B
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CHANNEL_RD_CALL : OUT STD_LOGIC; -- 07B
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N_MEM_SELECT : OUT STD_LOGIC; -- 07B
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RW_CTRL_STACK : OUT STD_LOGIC; -- 07B
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-- Clocks
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T1 : IN STD_LOGIC;
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SEL_T1 : IN STD_LOGIC;
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clk : IN STD_LOGIC
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);
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END RWStgCntl;
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ARCHITECTURE FMD OF RWStgCntl IS
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signal RD_SEL,WR_SEL : STD_LOGIC;
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signal CU01,CM0X0 : STD_LOGIC;
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signal CU_DECODE_CPU_LOCAL,MAN_SEL_LOCAL : STD_LOGIC;
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signal sCU_DECODE_UCW : STD_LOGIC;
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signal sMAIN_STORAGE_CP : STD_LOGIC;
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signal sGT_LOCAL_STG : STD_LOGIC;
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signal sCHANNEL_RD_CALL : STD_LOGIC;
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signal sCPU_READ_PWR : STD_LOGIC;
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signal sCPU_WRITE_PWR : STD_LOGIC;
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signal sUSE_ALT_CU_DECODE : STD_LOGIC;
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signal sUSE_R : STD_LOGIC;
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signal sEARLY_LOCAL_STG : STD_LOGIC;
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BEGIN
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-- Fig 5-04D
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sCHANNEL_RD_CALL <= (SEL_T1 and not SEL_RD_WR_CTRL) or HSMPX_READ_CALL; -- AD1L5,BE3E4
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CHANNEL_RD_CALL <= sCHANNEL_RD_CALL;
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RD_SEL <= MANUAL_RD_CALL or (sCPU_READ_PWR and T1) or sCHANNEL_RD_CALL; -- BE3D3,BE3H5,BE3J5
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WR_SEL <= (T1 and sCPU_WRITE_PWR and ALLOW_WRITE_2) or MANUAL_WR_CALL or (SEL_RD_CALL_TO_STP or HSMPX_READ_CALL); -- BE3J5,BE3H5
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N_MEM_SELECT <= not (not SELECT_CPU_BUMP and (RD_SEL or WR_SEL)); -- BE3H6
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-- ?? Note TD not implemented (yet)
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RW_LCH: entity work.FLL port map(RD_SEL,WR_SEL,RW_CTRL_STACK); -- BE3J5
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sUSE_ALT_CU_DECODE <= not ANY_PRIORITY_PULSE and not sCPU_READ_PWR; -- AB3D2
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USE_ALT_CU_DECODE <= sUSE_ALT_CU_DECODE;
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CU01 <= not SALS.SALS_CU(0) and SALS.SALS_CU(1); -- AB3E2
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USE_GR_OR_HR <= (sUSE_ALT_CU_DECODE and USE_CPU_DECODER and CU01); -- AB3E2,AB3H6-removed??
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sUSE_R <= not CU01 and not SEL_SHARE_HOLD; -- AB3D5,AB3H3
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USE_R <= sUSE_R;
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CM0X0 <= not SALS.SALS_CM(0) and not SALS.SALS_CM(2); -- AB3D6
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CPU_WRITE_IN_R_REG <= sUSE_R and CM0X0; -- AB3F2
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sCPU_WRITE_PWR <= CM0X0;
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CPU_WRITE_PWR <= sCPU_WRITE_PWR;
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sCPU_READ_PWR <= (SALS.SALS_CM(0) and not ANY_PRIORITY_PULSE_2) or (SALS.SALS_CM(1) and SALS.SALS_CM(2) and not ANY_PRIORITY_PULSE_2); -- AB3B6,AB3D2
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CPU_READ_PWR <= sCPU_READ_PWR;
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COMPUTE <= not sCPU_WRITE_PWR and not sCPU_READ_PWR; -- AB3F2
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CU_DECODE_CPU_LOCAL <= ((not G_REG_0_BIT or N1401_MODE) and (N1401_Mode or not G_REG_1_BIT) and SALS.SALS_CU(0) and SALS.SALS_CU(1) and USE_CPU_DECODER) or
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(not SALS.SALS_CU(0) and SALS.SALS_CU(1) and USE_CPU_DECODER); -- AA1C2,AA1J4 ?? *not* N1401_MODE ??
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FORCE_M_REG_123 <= CU_DECODE_CPU_LOCAL; -- AA1H2
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sCU_DECODE_UCW <= SALS.SALS_CU(0) and not SALS.SALS_CU(1) and USE_CPU_DECODER; -- AA1C2
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CU_DECODE_UCW <= sCU_DECODE_UCW;
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MAN_SEL_LOCAL <= USE_MAN_DECODER and E_SW_SEL_AUX_STG; -- AA1C2
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sEARLY_LOCAL_STG <= CU_DECODE_CPU_LOCAL or sCU_DECODE_UCW or MAN_SEL_LOCAL; -- AA1C3
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EARLY_LOCAL_STG <= sEARLY_LOCAL_STG;
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sMAIN_STORAGE_CP <= not sEARLY_LOCAL_STG; -- AA1J2
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MAIN_STORAGE_CP <= sMAIN_STORAGE_CP;
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-- SELECT_CPU_BUMP <= sEARLY_LOCAL_STG; -- ? Not sure!
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sGT_LOCAL_STG <= ((MEM_SEL and not ALLOW_WRITE) and MAN_STOR_OR_DISPLAY) or (T1 and sCPU_READ_PWR) or (SEL_T1 and not SEL_RD_WR_CTRL) or MACH_RST_1; -- AA1C2,AA1J2-removed??,AA1G4
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GT_LOCAL_STG <= sGT_LOCAL_STG;
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LS_LCH: entity work.PH port map(not sMAIN_STORAGE_CP,sGT_LOCAL_STG,LOCAL_STORAGE_CP); -- AA1F4
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MS_LCH: entity work.PH port map(not sEARLY_LOCAL_STG,sGT_LOCAL_STG,MAIN_STORAGE); -- AA1F4
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END FMD;
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