ibm2030.IBM2030/CLD/Regs.rtf

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{\s5\sl240\slmult1\fi-431\li720 Dashed List;}
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\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs16\b\ul\lang1033{\*\listtag0}Register usage}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}* = Bits detailed below}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}A = ALU input}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B = ALU input}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C = Interval timer count}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D = General data register}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F = External interrupts *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G = Op code}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H = Priority status register *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}I = Instruction counter (high)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}J = Instruction counter (low)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}L = Data length}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}M = Memory address (high)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC= Machine check status *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}N = Memory address (low)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Q = Storage protection key}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R = Memory buffer}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S = Status bits *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}T = Aux storage address}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}U = Data pointer (high)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}V = Data pointer (low)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}W = Microcode address (high)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}X = Microcode address (low)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Y = Wrap latch}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Z = ALU output bus}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC = Machine check reg *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}OE = Odd/Even ctrl latch}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}WRAP = Wrap store latch}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}XXH,XH,XL = Bump memory high addr}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}XXHBU,XHBU,XLBU = Backup regs\column }
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\b\lang1033{\*\listtag0}1050 registers}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}TA = 1050 Tags out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}TE = 1050 Bus out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}TI = 1050 Bus in}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}TREQ = 1050 Request in}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}TT = 1050 Tags in}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\b\lang1033{\*\listtag0}Direct Control registers}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}JE = Direct data channel Bus out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}JI = Direct data channel Bus in}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\b\lang1033{\*\listtag0}Front panel switches}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}(AB) (CD) ((*)) (FG) (HJ)\column }{\f0\fs16\b\lang1033{\*\listtag0}Register bit allocations}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F0 = 0}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F1 = Console interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F2 = External interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F3 = External interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F4 = External interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F5 = External interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F6 = External interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F7 = External interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H0 = ?}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H1 = MC Trap}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H2,3,4 = ?}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H5 = Selector hold flag}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H6 = Multiplexor hold flag}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H7 = ?}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC0 = A reg PC}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC1 = B reg PC}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC2 = MN reg PC}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC3 = Ctrl reg PC}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC4 = SALS PC}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC5 = W reg chk}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC6 = R reg PC or Stack PC}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}MC7 = ALU chk}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S0 = Add(0)/Sub(1) control}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S1 = Execute instruction}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S2 = Result non-zero accumulate}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S3 = ALU Carry store}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S4}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S5}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S6}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S7}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}\column }{\f0\fs14\b\ul\lang1033{\*\listtag0}Multiplexor registers}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FA = Multiplexor Tags out *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FB = Multiplexor Tags out *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FI = Multiplexor Bus in}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FO = Multiplexor Bus out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT = Multiplexor Tags in *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FWX = Multiplexor WX store}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FA0 = Set Bus Out (8)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FA1 = Address Out (4)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FA2 = Command Out (2)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FA3 = Service Out (1)\line FAP = Command Start (P)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\b\lang1033{\*\listtag0}K>FB actions}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K=1XX1 S012>XXH,XH,XL}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}or XXH,XH,XLBU>XXH,XH,XL}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K=11XX KP>Mpx Interrupt}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K=X11X KP>Mpx Opn Lch}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K=1X1X KP>Suppr Ctrl Lch}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K=X1X1 KP>Op Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K=XX11 R>Mask}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R0 = Mpx mask}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R1 = Sx1 mask}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R2 = Sz2 mask}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R7 = Ext mask}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT0 = Suppr Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT1 = Hold In}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT2 = Mpx opn lch}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT3 = Mpx share req}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT4 = Load ind (IPL)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT5 = Sel In}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT6 = Sel Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}FT7 = Mpx chnl intrpt\column }{\f0\fs14\b\ul\lang1033{\*\listtag0}Selector registers}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G1 = Status 1 (GJ,K=0111) *\line G2 = Status 2 (GJ,K=0110) *\line GA = Tags out *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GB = Control *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GC = Count high (GJ,K=0001)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GD = Count low (GJ,K=0010)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GE = Channel status (GJ,K=0100) *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GF = Flags *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GG = Command (Bits 4-7)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GH = Control *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GJ = K selects register to read}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GK = Prot key (GJ,K=0011)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GO = Bus out (GJ,K=1000)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GR = Data reg}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GS = Status *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT = Tags in *}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GU = Address high}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GV = Address low}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GWX = Selector WX store}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H1-HWX = Selector 2 registers}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G1 (GJ, K=0111)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}0 Input}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}1 Suppress Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}2 ROS Req}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}3 Addr Out (GA1)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}4 Comd Out (GA2)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}5 Serv Out (GA3)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}6 Bus Out Ctrl (GA0)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}7 Op Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G2 (GJ, K=0110)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}0 Cnt rdy + not zero}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}1 SLI (GF2)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}2 Com 7 bit (GG7)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}3 Cnt rdy + zero}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}4 0}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}5 CC (GF1)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}6 Rd Bkwd}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}7 Skip (GF3)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}\line GA0 = Set Bus Out (8)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GA1 = Address Out (4)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GA2 = Command Out (2)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GA3 = Service Out (1)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\b\lang1033{\*\listtag0}K>GB Actions}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}0 Set Prog Chk (GE2)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}1 KP>Chan (0=Sx1,1=Sx2)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}2 Reset Op Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}3 Reset PCI (GF4)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}4 Set Intrp latch}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}5 Set CCC (GE5)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}6 Reset GR}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}7 Unused?}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}8 KP>Cnt rdy}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}9 Chan reset}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}A KP>Suppr Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B KP>Poll Ctrl}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C KP>Sel Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D Set Chnl busy}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}E Set Halt IO}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F Set ICC (GE6)GS0 = GR full}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}\line GE0 = PCI\line GE1 = Inc Len\line GE2 = Prog Chk\line GE3 = Prot Chk\line GE4 = Chnl Data Chk\line GE5 = Chnl Ctrl Chk}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GE6 = Intrf Ctrl Chk\line }
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GF0 = CD}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GF1 = CC}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GF2 = SLI}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GF3 = Skip}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GF4 = PCI}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\b\lang1033{\*\listtag0}K>GH Actions}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}0 Reset Sx1,Sx2}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}1 Set Diag mode}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}2 Reset Diag Tag Ctrl}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}4 Sx1/Sx2 select?}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}7 Set Chain Det}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B Set Cnt rdy + zero}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C Set Sel Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D Chain reset}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}\line GS1 = Chain detect\line GS2 = Interrupt latch\line GS3 = Interrupt condition}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GS4 = CD flag}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GS5 = 1=GS (Sx1) 0=HS (Sx2)}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GS6 = Unused}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GS7 = Chain waiting}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT0 = Select In}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT1 = Srv In not Srv Out}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT2 = Poll Ctrl}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT3 = Channel busy}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT4 = Address In}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT5 = Status In}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT6 = Interrupt latch or PCI}
\par\pard\plain\ltrpar\s15\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}GT7 = Op In}
\par\pard\plain\ltrpar\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}}}