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ibm2030.IBM2030/CLD/qa071.rtf
Lawrence Wilkinson bf39525f5f Add CLD files in RTF format
2021-07-23 21:56:41 +02:00

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\s20\ql \li0\ri0\sl240\slmult0\nowidctlpar\aspalpha\faauto\rin0\lin0\itap0 \fs20\lang1033\langfe255\loch\af2\hich\af0\dbch\af0\cgrid\langnp1033\langfenp255 {\fs14\insrsid9449776 \hich\af0\dbch\af0\loch\f2 0 1
\hich\af0\dbch\af0\loch\f2 2 3 4 5 6 7 8 9
\par \hich\af0\dbch\af0\loch\f2
\par \hich\af0\dbch\af0\loch\f2 This microprogram separates the SS ops
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2 from the RS and SI ops and finishes the
\par \hich\af0\dbch\af0\loch\f2 I cycle op branching for the RS and SI ops
\par \hich\af0\dbch\af0\loch\f2 A
\par \hich\af0\dbch\af0\loch\f2
\par \hich\af0\dbch\af0\loch\f2
\par \hich\af0\dbch\af0\loch\f2
\par \hich\af0\dbch\af0\loch\f2
\par
\par \hich\af0\dbch\af0\loch\f2 B \hich\af0\dbch\af0\loch\f2
---------------------------------------------------------------------------------------------------QA311------EDE...
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| (10)
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| Shifts
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
|
\par \hich\af0\dbch\af0\loch\f2 | \hich\af0\dbch\af0\loch\f2
\par \hich\af0\dbch\af0\loch\f2 C | \hich\af0\dbch\af0\loch\f2
\par \hich\af0\dbch\af0\loch\f2 | \hich\af0\dbch\af0\loch\f2
\par \hich\af0\dbch\af0\loch\f2 |
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
|
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
|
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2 |
\par \hich\af0\dbch\af0\loch\f2
D | -----------QA911------EFE
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| | (00)
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
10 --- 0146 00 --- 0164 | 00 --- 0318 | Set sys mask
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| | K 0011,1 | | K 0011 | | (01)
\par \hich\af0\dbch\af0\loch\f2 A U+R+C>UC \hich\af0\dbch\af0\loch\f2
| A R+0+C>DC | | A LH+KL>T | | Read/write
\par \hich\af0\dbch\af0\loch\f2 E QA031.JEE-----------------------------------S T>MN LS S*------------\hich\af0\dbch\af0\loch\f2
------------O---S WRITE K>W R*------------------------O---| |*--------------------------------------------------------------------O direct
\par \hich\af0\dbch\af0\loch\f2 (10) | | | C \hich\af0\dbch\af0\loch\f2
ANSNZ>S2 | | C 0>S6 | | (10)
\par \hich\af0\dbch\af0\loch\f2 RS,SS index | | | | | \hich\af0\dbch\af0\loch\f2
| | | | Load PSW
\par \hich\af0\dbch\af0\loch\f2 R G2,G1 64R | R G4,G3 18R \hich\af0\dbch\af0\loch\f2
| R G6,G5 24R | Diagnose
\par \hich\af0\dbch\af0\loch\f2 E2-- ** --EB | E4-- ** --ED | E6-- \hich\af0\dbch\af0\loch\f2
** --EF |
\par \hich\af0\dbch\af0\loch\f2 Add hi displacement | Check for unavail | Set up R1 \hich\af0\dbch\af0\loch\f2
-----------QA191------EFE
\par \hich\af0\dbch\af0\loch\f2 F to hi base address | address. | address \hich\af0\dbch\af0\loch\f2
(11)
\par \hich\af0\dbch\af0\loch\f2 read unavailable address | Br on RS-SI ops | finish op br
\hich\af0\dbch\af0\loch\f2 BR IX
\par \hich\af0\dbch\af0\loch\f2 from base register | 10 --- 0166 |
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
branch to seperate | | | |
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
SS ops | A 0+0+1>L | |
\par \hich\af0\dbch\af0\loch\f2 G \hich\af0\dbch\af0\loch\f2
O---S WRITE |*------------------------------------------------------------------------------------------- O----------QA431------JFE
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| C 0>S6 | | | | (11)
\par \hich\af0\dbch\af0\loch\f2 | | |\hich\af0\dbch\af0\loch\f2
| | | Logics SX
\par \hich\af0\dbch\af0\loch\f2 | R 1,1 47R \hich\af0\dbch\af0\loch\f2
| | |
\par \hich\af0\dbch\af0\loch\f2 | G4-- 11 --GD | \hich\af0\dbch\af0\loch\f2
| |
\par \hich\af0\dbch\af0\loch\f2 | Inv op | \hich\af0\dbch\af0\loch\f2
| |
\par \hich\af0\dbch\af0\loch\f2 H | | ----------------------------------------------
\hich\af0\dbch\af0\loch\f2 ---------QA451------JFE
\par \hich\af0\dbch\af0\loch\f2
| | | | (
\hich\af0\dbch\af0\loch\f2 00)
\par \hich\af0\dbch\af0\loch\f2
00 --- 0160 | | 01 --- 0319 | 10 --- 03F6 | Store mtpl,
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| | | | | | | K 0101,0 | | Test/mask,
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
A 0>RC | | | A LM>T | | A 0+KL>L | | Move char,
\par \hich\af0\dbch\af0\loch\f2 J QA021,JJE---------O--------------\hich\af0\dbch\af0\loch\f2
----------*| |-------------------------O O---| |*------------------------O---| |*--O Test and Set
\par \hich\af0\dbch\af0\loch\f2 (00,01) | \hich\af0\dbch\af0\loch\f2
| | | | | | | C 0>S6 | |
\par \hich\af0\dbch\af0\loch\f2 RS,SS B=0 | | | | | | | | | | |
\par \hich\af0\dbch\af0\loch\f2 | \hich\af0\dbch\af0\loch\f2
|--*R G2,G1 64R | | R S2,G5 F4R | R 1,CA01>W 46R |
\par \hich\af0\dbch\af0\loch\f2 | | J2-- ** --JB \hich\af0\dbch\af0\loch\f2
| | J6-- ** --JF | J8-- 11 --JH |
\par \hich\af0\dbch\af0\loch\f2 | | Set R to 0 to | \hich\af0\dbch\af0\loch\f2 | Branch if | Inv addr |
\par \hich\af0\dbch\af0\loch\f2 K | | indicate no hi | | unavail. addr \hich\af0\dbch\af0\loch\f2 | |
\par \hich\af0\dbch\af0\loch\f2 | | order address | | | |
\par \hich\af0\dbch\af0\loch\f2 |\hich\af0\dbch\af0\loch\f2
01 --- 0161 | BR to separate | | | 11 --- 03F7 | 11 --- XXX
\par \hich\af0\dbch\af0\loch\f2 | | | | SS ops \hich\af0\dbch\af0\loch\f2
| | | K 0101,0 | | | GO TO |
\par \hich\af0\dbch\af0\loch\f2 | A I+0+1>I | | | \hich\af0\dbch\af0\loch\f2
| | A 0+KL>L | | | QA879.CAE |
\par \hich\af0\dbch\af0\loch\f2 L ---*| |*--- | |\hich\af0\dbch\af0\loch\f2
----| |*--O---| |
\par \hich\af0\dbch\af0\loch\f2 | | | | \hich\af0\dbch\af0\loch\f2
C 0>S6 | | | |
\par \hich\af0\dbch\af0\loch\f2 | | | | \hich\af0\dbch\af0\loch\f2
| | | | |
\par \hich\af0\dbch\af0\loch\f2 R 0,0 60R | | 1,CA01>W 46R | |
\hich\af0\dbch\af0\loch\f2 |
\par \hich\af0\dbch\af0\loch\f2 L1-- 00 --LA | | L8-- 11 --LH | L9-- 11 --LJ
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| | Inv addr | Prg int
\par \hich\af0\dbch\af0\loch\f2 M \hich\af0\dbch\af0\loch\f2 | | |
\par \hich\af0\dbch\af0\loch\f2 | \hich\af0\dbch\af0\loch\f2 | |
\par \hich\af0\dbch\af0\loch\f2 | 01 --- 0165 | 11 --- 031B 10 -\hich\af0\dbch\af0\loch\f2
-- 031E |
\par \hich\af0\dbch\af0\loch\f2 | K 0011,1 | | K 0100 | K 0101,0 | |
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| A R+0+C>TC | | A GXL+KH+1>T | A 0+KL>L | |
\par \hich\af0\dbch\af0\loch\f2 N \hich\af0\dbch\af0\loch\f2
O---S WRITE K>W R*--- ----| |*------------------------O---| |*--- O----------QA461------NPE
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| C ANSNZ>S2 | | C ANSNZ>S2 | | C 0>S6 | | (00)
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| | | | | | | | | | Load Mtpl
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| R S1,S7 70R | R S2,G6 | | R 1,CA01>W 46R |
\par \hich\af0\dbch\af0\loch\f2 | N4-- ** --ND | \hich\af0\dbch\af0\loch\f2
N6-- ** --NF | N8-- 11 --NH |
\par \hich\af0\dbch\af0\loch\f2 | Put unavail. | Branch if \hich\af0\dbch\af0\loch\f2
| Inv addr |
\par \hich\af0\dbch\af0\loch\f2 P | addr. in T | unavail. Addr. -------------\hich\af0\dbch\af0\loch\f2
-------------------------------O----------QC001------NPE
\par \hich\af0\dbch\af0\loch\f2 | | Turn S2 on. \hich\af0\dbch\af0\loch\f2
(01,11)
\par \hich\af0\dbch\af0\loch\f2 | 11 --- 0167 | Make T=4A
\hich\af0\dbch\af0\loch\f2 I/O ops
\par \hich\af0\dbch\af0\loch\f2
| K 0011,1 | |
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| A R+0+C>ZC | |
\par \hich\af0\dbch\af0\loch\f2 Q \hich\af0\dbch\af0\loch\f2
----S WRITE K>W R*--O------------------------------------------------------------------------------------------------------------------------QA081------NDE
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
C ANSNZ>S2 | (00,10,11)
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| | SS ending
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
R S1,S7 70P
\par \hich\af0\dbch\af0\loch\f2 Q4-- *\hich\af0\dbch\af0\loch\f2
* --QD
\par \hich\af0\dbch\af0\loch\f2 Test unavail
\par \hich\af0\dbch\af0\loch\f2 R \hich\af0\dbch\af0\loch\f2 address
\par \hich\af0\dbch\af0\loch\f2 br on IC stored
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2 and second index
\par
\par
\par \hich\af0\dbch\af0\loch\f2 S
\par
\par
\par \hich\af0\dbch\af0\loch\f2 Q
\par \hich\af0\dbch\af0\loch\f2 A
\par \hich\af0\dbch\af0\loch\f2 0
\par \hich\af0\dbch\af0\loch\f2 7 | 128015 09/27/65 | Mach 2030 | Date 11/17/65
\hich\af0\dbch\af0\loch\f2 Sheet 1 QA071 |
\par \hich\af0\dbch\af0\loch\f2 1 | 128045 11/17/65 | Name | Log 3563 Vers
\hich\af0\dbch\af0\loch\f2 ion |
\par \hich\af0\dbch\af0\loch\f2
| | Mode Manual |
\hich\af0\dbch\af0\loch\f2 |
\par \hich\af0\dbch\af0\loch\f2
| | P.N. 837007 | RS-SI op branch |
\par \hich\af0\dbch\af0\loch\f2 \hich\af0\dbch\af0\loch\f2
| | IBM Corp. | |
\par }}
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