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106 lines
16 KiB
Plaintext
106 lines
16 KiB
Plaintext
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\viewkind4\uc1\pard\ltrpar\lang1033\f0\fs14 QA361 0 1 2 3 4 5 6 7 8 9\par
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\par
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\par
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The top routine on this page wll transfer the overflow The bottom routine on this page ends the logical\par
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indication to S5 to free up S3. It also examines the shifts without overflow testing and without setting\par
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A hi 2 bits of the L reg as required to set up S6 and S7. the cond reg. It ends algebraic shifts by\par
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At the end of this routine,everything is ready to enter setting the cond reg and by setting the correct\par
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QA371 which will move the operand from the loc stg F sign bit if an overflow has occurred.\par
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row back to the dest reg, shifting left 0 to 3 bits\par
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as required.\par
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QA341.JEE------------\par
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B (00) | \par
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Shift complete |\par
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| 00 --- 04E4 \par
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---------------------------------------------*K 0011 | \par
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A VH+KL>V | \par
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C QA351.GJE-------------------------------O------------------------*| |*--------------------------------------------O---------------------------------------------O------------------------------------------------------QA371------CCE\par
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(00,01,10,11) | C 0>S2 | | | (01,11)\par
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Determine S3=Value of 1st | ----| | | | Move operand\par
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left shift bit to be shifted | | R 0,1 71R | | back to reg\par
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amount and in | | C3-- 01 --CC | |\par
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overflow S4,S5 0 | | Left shift 0 or 1 bit. | |\par
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D VH=Register (odd | | V=lo order reg addr | |\par
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if dbl shift) | | | |\par
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| 01 --- 04E5 | 00 --- 04A0 | 00 --- 0478 |\par
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| | | | K 0011 | | K 0011 | |\par
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| A 0>Z | | A VH+KL>V | | A VH+KL>V | |\par
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E O---| |*--- ----| |-- ----| |---O\par
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| C LZ>S5 | | | | | C 0>S6 | |\par
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| | | | | | | | | |\par
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| R 0,0 E4R | R AC,1 71R | R AC,1 71R |\par
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| E2-- 00 --EB | E5-- *1 --EE | E7-- *1 --EG |\par
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| Overflow | Left shift 2. V=lo order reg | See below |\par
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F | Set S5=1 | addr. BR on AC will set S7=2nd | |\par
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| | bit during the next step. | |\par
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| 10 --- 04E6 | 01 --- 04A1 | 10 --- 047A |\par
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| | | | | | | K 0011 | |\par
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| A L+L>L | | A L+L>Z | | A VH+KL>V | |\par
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G O-------------------------| |*------------------------O---| |*------------------------O---| |----\par
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| C 0>S2 | | | C 1>S6 |\par
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| ----| | | | | |\par
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| | R 0,G3 A0R R AC,0 78R R AC,1 71R\par
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| | G3-- 0* --GC G5-- *0 --GE G7-- *1 --GG\par
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| | Left shift 2 or 3 Left shift 3. Shift L again to In the above 2 steps, V=lo order reg\par
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H | | bits. Shift L to determine 3rd bit to be shifted in. addr. S6 will be set to the value of\par
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| | determine 2nd bit the 2nd bit. The BR on AC will set\par
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| 11 --- 04E7 | to be shifted in S7=3rd bit during the next step.\par
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| | | |\par
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| A 0>Z | |\par
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J ----| |*---\par
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C LZ>S5 | \par
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| | \par
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R 1,0 E6R \par
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J2-- 10 --JB \par
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Overflow\par
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K Set S5=1\par
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\par
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00 --- 04E8 ** --- XXX\par
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K 0001,0 | | Go to |\par
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A 0>L | | QA001.CBB |\par
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L ---*S K>W R*--O-----------------------------------------------------------------------------------------------------------------| |\par
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| C 0>S2 | | | |\par
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| | | | | |\par
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| R S1,INTR 00R | | |\par
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| L3-- ** --LC | L9-- ** --LJ\par
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| Log,end op | Normal I\par
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M | | cycle start\par
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| |\par
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| 01 --- 04E9 | 11 --- 047B\par
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| K 0001,0 | | K 1000 |\par
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| A 0>L | | A R!KH>R |\par
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N QA371.QFE-----------------------------------------------------O---S K>W R---- | | \par
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(00,01,10,11) | C 0>S2 | C 0>S7 | \par
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Shift end S0=0 if Log or Alg + | | | ----| |----\par
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routines S0=1 if Alg - | R S1,INTR 00R | R 1,1 ABR |\par
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G=80 | N3-- ** --NC | N4-- 11 --ND |\par
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| Log,end op | Set sign bit - |\par
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P | | |\par
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| | |\par
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| 11 --- 04EB | 01 --- 0479 | 11 --- 04AB\par
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| | | | K 1000 | | K 0001,0 |\par
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| | | | A R.-KH>R | | | |\par
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Q O---S UV>MN LS S*--O---| |*--O---S WRITE K>W R*-----------------------------------------------------------------------------------------------------QA421------QEE\par
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| | | C 0>S7 | | | (01)\par
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| | | | | | | Set overflow\par
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| R S0,1 79R R 1,1 ABR R 0,1 D9R and check\par
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| Q3-- *1 --QC Q4-- 11 --QD Q5-- 01 --QE mask\par
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| Overflow Set sign bit + S7=0 in previous steps to cause mask to be examined\par
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R | in set. overflow cond reg routine.\par
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| In step SC, it has been determined that the Alg.\par
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| 10 --- 04EA shifts ended with no overflow. The sign is then\par
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| K 0001,0 | tested for setting the cond reg.\par
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| A GH.RH>Z |\par
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S ----S K>W R*-------------------------------------------------------------------------------------------------------------------------------------------------QA421------SCE\par
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| | (00)\par
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Q | | Set shift\par
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A R 0,0 D8R cond reg\par
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3 S3-- 00 --SC\par
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6 | 128015 09/27/65 | Mach 2030 | Date 07/07/66 Sheet 1 QA361 |\par
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1 | 128045 11/17/65 | Name | Log 2187 Version |\par
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| 128059 06/30/66 | Mode Manual | |\par
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| | P.N. 837027 | Shifts, left shift tests |\par
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| | IBM Corp. SDD | and end routine |\par
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}
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