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ibm2030.IBM2030/CLD/qb801.rtf
Lawrence Wilkinson bf39525f5f Add CLD files in RTF format
2021-07-23 21:56:41 +02:00

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\pard\plain\ltrpar\s19\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}QB801 0 1 2 3 4 5 6 7 8 9}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} 1.Rate Switch to Instruction Step Micro trace}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} 2.ROS Control to ROS Scan 300 BBB BCB BCA BC6 BC7 BB8 BBA BC1 BC0 BDF BDF}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}A}{\f0\fs14\lang1033{\*\listtag0} 3.CPU Check to Process B04 BC2 BBD BD9 BDA BC4 BC5 BBE BBE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} 4.Press IPL B04 BC3 AEA BC9 BBE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} 5.Visually check ROAR for 0BC7 at E5 on QB801 with B-reg B02 BBF BCF}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} check light on}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} 6.Press Set IC}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 7.Visually check ROAR for 0BBE at N5 on QB801 with A-reg}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B}{\f0\fs14\lang1033{\*\listtag0} check light on}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} 8.Follow instructions at word 0BBE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 00 --- 9399 }{\f0\fs14\lang1033{\*\listtag0} 9.Visually check ROAR for 0BCD at N5 on QB821 R-reg must}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} K 1011,0 | }{\f0\fs14\lang1033{\*\listtag0} equal FF}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} A 0+0>U | }{\f0\fs14\lang1033{\*\listtag0} 10.Follow instructions at word 0BCD}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C S K>W R*---}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 1,1 BBR |}{\f0\fs14\lang1033{\*\listtag0} Press}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C1-- 11 --CA |}{\f0\fs14\lang1033{\*\listtag0} Set IC}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} CD for U may |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D reset prior lth |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ---------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 11 --- 0BBB 00 --- 0BC8 10 --- 0BCA 10 --- 0BC6 11 --- 0BC7 00 --- 0BB8 10 --- 0BBA 01 --- 0BC1 00 --- 0BC0}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 0001,0 | K 1000,0 | K 1000,0 | K 1011,0 DECA K 1000,0 | K 1111,1 | K 0111,0 | K 0100,0 | K 1111,0 DECA}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A FTXH+KL>R | A L+0>L | A 0!L>TA | A 0^+-0>TE | A F-L0>T | A 0+K0>Q | | | A 0+KL>R | A 0^+-L0>H | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}E --S UV>MN MS S*------S STORE |*------| |*------| |*------| |*------S IJ>MN MS S*------S STORE |*------| |*------| |*-}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C K>GB | | | | | C LZ>S5 | C K>FA | | | C K>FB | | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | C 1>OE | C 1>OE | C 0>MC | | | | | | | | | C 1>F0 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 0,0 C8R R 1,0 CAR R 1,0 C6R R 1,1 C7R R 0,0 B8R R 1,0 BAR R 0,1 C1R R 0,0 C0R R 1,1 DFR |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} E1-- 00 --EA E2-- 10 --EB E3-- 10 --EC E4-- 11 --ED E5-- 00 --EE E6-- 10 --EF E7-- 01 --EG E8-- 00 --EH E9-- 11 --EJ |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 80+01=81 Set even latch B-reg Mch Chk Set supr mal FF-00=FE Set stack for Store prot req R5=1 Reset supr mal |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F FT 4 set from L-reg stores prior ltch blks funct trap ltch L-reg parity prot request funct trap ltch |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Load key bad parity traps. Set to stop on mch causes B-reg to allow trap |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R0 and R7=1 ALU Chk ltch to error mch check on B-reg mch |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R5=0 blk W-reg reset CD for TE may WX advance is R7=1 FB=K3 error |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Set Sx1 gate on trap. reset prior lth blocked Set ext trap |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G CD for TA may mask |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} reset prior lth FB=K5 set Op |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Out to clear |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} FI |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} QB821.NJE---------------------------------------------------------------------------- ---------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H (01) | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Loop | | -------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 00 --- 0BDC 10 --- 0BC2 01 --- 0BBD | 01 --- 0BD9 10 --- 0BDA 00 --- 0BC4 01 --- 0BC5 | | 11 --- 0BDF |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | K 0100,0 | K 1011,0 | ---*K 1011,0 | K 1011,0 | K 1110,0 | | | | --| | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} A L^-D>R | A FT+KL>T | A D0-KL>Q | A 0-0>G | A G+D>I | | | A FI+L0>Z | | A 0-0>D | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}J ----| |*--O---S UV>MN MS S*--O---| GR S*--O---S WRITE |*------| |*------S IJ>MN MS S*------S STORE |*- ----| |*-}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | C ANSNZ>S2 | | | | | | | | C K>GH | C TREQ>S1 | C GR>GF | C 1>S7 | | | | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | C 0>MC | | | | C 0>MC | C 0>F | | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | R 1,S7 C2R | R 0,Z=0 BDR | R 0,INTR D9R | R 1,S7 DAR R 0,0 C4R R 0,1 C5R R 1,0 BER | R 1,1 BFR}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | J1-- 1* --JA | J2-- 0* --JB | J3-- 0* --JC | J4-- 1* --JD J5-- 00 --JE J6-- 01 --JF J7-- 10 --JG | J9-- 11 --JJ}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | Supr A-reg chk | 1C+04=20 | CA of D resets | Set cnt ready FF+FF=FE CD-latch FI reg cause | 00-00=FF}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K | latch blocks | FT3-Mpx share | supr A chk ltch | Wrap I-reg conditions A-reg mch chk | To mch chk trap}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | stop on 2nd | FT4-Load Ind | | true with carry Sel ROM Req L-reg should | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | error | FT5-Sel In | 00 --- 0BBC | 00 --- 0BD8 on 64k Use I to set not cause B | 10 --- 0BCE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 00^00=00 | Contents of T ----| | | | | wrap request check | K 1011,0 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | indicates value A SP+0>Z | | R SP+0>Z | | A HXL-0>L | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}L --------------------- | of FT ----S WRITE |*- ----S WRITE |*- --------------------------------------------------------------- ----| |--}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | | | | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | --| | | --| | | | | C 0>MC | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | R 0,0 BCR | | R 0,0 D8R | | | R 1,INTR DER |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | L3-- 00 --LC | | L4-- 00 --LD | | | L9-- 1* --LJ |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Mch chk trap | | | ------------------- ------------------- | IPL Trap | L to 07 for |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}M | | ----------------------------------------------+---------------------------------------------------------------- | high speed loop |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 00 --- 0B04 | | 11 --- 0BC3 10 --- 0AEA 01 --- 0BC9 | 10 --- 0BBE Mch chk stop 10 --- 0B02 | 11 --- 0BBF | 11 --- 0BCF |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | K 1010,1 DECA K 0100,0 | K 0010,0 | --K 0000,0 | on 2nd error K 1011,0 | | K 1000,0 | | K 1011,0 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | A 0^+-0>D | A 0-KL>H | A 0+KL>L | A D0+0>H | A-reg light on A TX^L>D | | A L+KH>H | | A HXL+0>L | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}N | |*- ----| K>W R*------| |*------| |*------| |*- 1.Press Start | |*--O---| |*--O---| |*O------------QB811------NJE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | C 0>S7 | | | | | C K>FA | | 2.Press Start C ANSNZ>S2 | | | | | (10)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | | --| | | to mch chk trap C 0>MC | | | C 0>MC | Missed Trap}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 0,0 DCR R 1,0 EAR R 0,CA0B>W C9R R 1,0 BER | R 1,INTR BER | R G0,G1 BFR R 1,S5 CFR R 1,INTR |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} N1-- 00 --NA N2-- 10 --NB N3-- 01 --NC N4-- 10 --ND | N5-- 1* --NE | N7-- ** --NG N8-- 1* --NH N9-- 1* --NJ}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Set supr mal H-reg S=0 00+02=02 ------------------- 02^02=00 Block IPL L for IJ trap}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}P funct trap ltch Supr A-reg Set L-reg for CA of D resets with no set Set L to 08}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ------------------- to stop on mch check blocks IPL trap supr A-reg chk}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 10 --- 0302 | error. R5=0 Sel trap 00 --- 0380 latch}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} --| | | from B04 | | }{\f0\fs14\lang1033{\*\listtag0} Priority Mch IPL Frce Wrap Prot Stop Sel Mpx}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} A SP+0>Z | | Stop on ZT A SP+0>Z | }{\f0\fs14\lang1033{\*\listtag0} Chk IJ}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Q | |*- ----| |*---}{\f0\fs14\lang1033{\*\listtag0} H-reg cntrl X 0 4 2 3 X 5 5+6}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | |}{\f0\fs14\lang1033{\*\listtag0} Trap order 1 2 3 4 5 6 7 8}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | |}{\f0\fs14\lang1033{\*\listtag0} Addr of B B B B B B 3 B}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 1,0 02R | R 0,0 80R |}{\f0\fs14\lang1033{\*\listtag0} Diag trap 0 0 0 2 4 8 0 1}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q1-- 10 --QA | Q4-- 00 --QD |}{\f0\fs14\lang1033{\*\listtag0} 4 2 1 0 0 0 B 0}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} IPL trap in | Stop trap in |}{\f0\fs14\lang1033{\*\listtag0} L for trap 00 02 08 07 06 05 0A 01}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R module 3 | module 3 |}{\f0\fs14\lang1033{\*\listtag0} Set L to 02 08 07 * 05 ** 0B 01 00}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}{\f0\fs14\lang1033{\*\listtag0} L for loop 02 07 -- * 05 ** 0B 01 00}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} -----------------------}{\f0\fs14\lang1033{\*\listtag0} Note * Note **}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 06 for Ver 006 0A for Ver 014}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S}{\f0\fs14\lang1033{\*\listtag0} 05 for Ver 000 01 for Ver 000}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} B}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 8}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 0 | 128056 04/18/66 | Mach 2030 | Date 11/07/67 Sheet 1 QB801 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 1 | 128058 06/21/66 | Name | Log 2046 Version |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 128065 07/26/67 | Mode Manual | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | P.N. 837440 | Priority Controls Test |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | IBM Corp. | ID 3347 |}
\par\pard\plain\ltrpar\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}}}
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