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ibm2030.IBM2030/CLD/qc001.rtf
Lawrence Wilkinson bf39525f5f Add CLD files in RTF format
2021-07-23 21:56:41 +02:00

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\pard\plain\ltrpar\s19\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}QC001 0 1 2 3 4 5 6 7 8 9}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} This is the beginning of all IO execute cyucles for all This micro-routine begins the final decoding of the four}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} IO channels. Entry into the routine if from the I-cycles IO ops, (Start-IO,Test-IO,Halt-IO,and Test-Channel). The}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}A micro-program For RS ops at entry T is set to 4A, the final decode is effected by inspection of the two low}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} address of the 2nd byte of the CAW in main storage, the order op bits found in G5 and G7 at entry from I cycles.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} exit from RS I cycles leaves S1=0 if the IO instruction Inspection of the channel address (found in U5,U6,andU7)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} is being performed in the main instruction stream and is also undertaken to direct the initiation of the oper-}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S1=1 if the instruction is being executed by an execute ation to the proper channel. An entry from the hardware}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} instruction. If S1=2, the IC and any impending wrap con- forced interrupt routine also shares this entry routine.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B ditions have already been stored temporarily in LS-A9-AA.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 01 --- 031D 00 --- 05EC 11 --- XXX}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} K 1001,0 | K 0010,0 | | Go to |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} A 0+0+1>L | A 0+KL>L | | QA879.CAE |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C QA091.NFE-------------------------------O--*S *B9 LS S---- ----------------------------------------------------------------------S WRITE |*--O---| |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (01,11) | C 0>S4,S5 | | | C 0>S6 | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} I-O ops | | | | | | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} -any I-O | R 1,0 AAR | | R 1,CA01>W 46R | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} instruction | C2-- 10 --CB | | C8-- 11 --CH | C9-- 11 --CJ}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} T is set | B9-Mem Prot. | | Problem State | Prg Int}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D to 4A | and Supervisor | | IO not allowed |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | ----------------------------------------- |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 11 --- 031F | 10 --- 03AA 01 --- 0571 | | 01 --- 05ED 11 --- 0583 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 1001,0 | | K 0101,1 | K 0001,1 | | --K 1100 | K 0010,1 | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A 0+0+1>L | | A RL.LL>Z | A I>R | | | | A J>R | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}E ----S *B9 LS S*--O---S WRITE K>W R*--O---S *A9 LS S*--O---S STORE |*--O---S *AA LS S*- |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C 0>S4,S5 | C LZ>S5 | | C 1>S6 | C 0>S6 | | C 0>S2 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | C Y>WRAP | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 1,0 AAR R S1,1 71R | R 0,S5 ECR R S6,1 81R | R 0,1 EDR |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} E2-- 10 --EB E3-- *1 --EC | E4-- 0* --ED E5-- *1 --EE | E6-- 01 --EF |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} From checking BR on execute | Not execute Store IC-- | Access AA for |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F mask in D reg Chk Sys mode | Start IJ store I in A9-J in AA | J storage |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ----------------------+-------------------------------------------- |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 01 --- 0581 | 11 --- 0573 10 --- 05EE |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 0100,0 | ----K 0111 | K 0010,0 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A GXL!KH>R | A G.KL>G | A 0+KL>L | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G ----S *8C LS S*------S STORE |*--O---------------------------------------------------------------------S WRITE |----}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | C 0>S2 | | C 0>S6 | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 1,1 73R R 1,S5 EER | R 1,CA01>W 46R }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} G3-- 11 --GC G4-- 1* --GD | G8-- 11 --GH }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 8C-ILC + PSW G=0000 00XX | Problem State}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H bit storage BR on Sys mode | IO not allowed}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} -------------------------------------------------------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 11 --- 05EF 01 --- 0505 10 --- 0586 10 --- 0506 00 --- 0588 00 004 0508 01 --- 0509}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | K 0010 | | | K 0111 | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A T+0+1>T | A R>I | A T.-KL>T | A R>J | A R.KL>S | A I+0>ZC | A T-0>T |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}J ----S T>MN MS S*--O---S WRITE |*--O---S T>MN MS S*------S WRITE |*------| |*------S T>MN MS S*------S WRITE |*-----------------------------------QC011------JHE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | | | | C ANSNZ>S2 | | | | | (10,11) EF,CB}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | | | | | | | 004V | | CAW handling}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R G6,1 05R | R 1,G7 86R | R 1,0 06R R 0,0 88R R 0,0 08R R 0,1 09R R 1,S3 8AR routine for}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} J2-- *1 --JB | J3-- 1* --JC | J4-- 10 --JD J5-- 00 --JE J6-- 00 --JF J7-- 01 --JG J8-- 1* --JH Start IO}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 4A-CAW byte 2 | Stt IO or TIO | 4B-CAW byte 3 Nxt CCW addr Check lo 3 bits 49-CAW byte 1 BR on addr err}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K partial decode | Finish decode | T set to 49 now in IJ reg of addr for NZ Chk CCW addr T set to 48}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | S=0000 0000 for too big S3=1=error}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 11 --- 0587 if all ok Addr too big}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | ----K 0111 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A U.KL>Z |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}L QA901.LJE----------------------------------------------------+------------------------*| |*---------------------------------------------------------------------------------------------------------------------------QC011------LDE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (11) | C ANSNZ>S2 | (01)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Interrupt | | | Interrupt or}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} entry to | R 0,1 89R TIO initial}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} cause CSW | L4-- *1 --LD}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} storage | TIO (G3=0) or}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}M | interrupt (G3=1)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 11 --- 0507 10 --- 050E 00 --- 0574}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 0111 | K 1001,0 | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A U.KL>S | A 0-0>L | A VH+0+1>S |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}N ----S WRITE |*--O---| |*--O---| |*-----------------------------------------------------------------------------------------------------QC041------NEE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C ANSNZ>S2 | | C K>FB | | | | (10) EC}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | | | | Halt IO cmd}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 1,G7 0ER | R S2,0 74R | R 1,0 3AR to Mplx Chnl}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} N3-- 1* --NC | N4-- *0 --ND | N5-- 10 --NE --Enter UCW}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} HIO or TC | HIO-L=FF | Set S with hi addr formation}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}P Finish decode | XH,XL=00 | 4 un addr bits routine}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S=0000 0000 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} if Mpx cnl addr | 11 --- 050F | 10 014 0576}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 0001 | ----K 1001,1 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A FT.KL>Z | A UL>S |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Q ----| |*--O---| K>W R*-----------------------------------------------------------------------------------------------------QD011------QEE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | (01)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | 014V Sel Ch I/O}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 1,Z=0 76R | R 0,1 19R commands}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q4-- 1* --QD | Q5-- 01 --QE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Test Channel | Sel Ch Hlt or}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R BR on chnl | Tets Channel}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 11 --- 0577}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Version for system | K 1011,1 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} with at least one | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S selector channel ----S *BB LS S*-----------------------------------------------------------------------------------------------------QC151------SEE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} and 64k main storage | | (00,01) NF,QF}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q | | Test Channel}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C R 0,Z=0 D0R cmd-Mplx}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 0 S5-- 0* --SE channel}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 0 | 128015 10/11/65 | Mach 2030 | Date 11/17/65 Sheet 1 QC001 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 1 | 128045 11/17/65 | Name | Log 2046 Version A02 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 128065 07/26/67 | Mode Manual | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | P.N. 837405 | All channel operation decode |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | IBM Corp. | and execute initiation |}
\par\pard\plain\ltrpar\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}}}
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