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296 lines
13 KiB
VHDL
296 lines
13 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-03C.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- Clock Start & Stop control
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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-- Revision 1.1 2012-04-07
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-- Change PROC_STOP_LOOP condition to make STOP/START buttons happier
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY ClockStartStop IS
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port
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(
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-- Switches
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SW_START,SW_LOAD,SW_SET_IC,SW_STOP : IN std_logic;
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SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
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SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
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SW_PWR_OFF : IN std_logic;
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-- Other inputs
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ALLOW_MAN_OPER : IN std_logic;
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FT3_MPX_SHARE_REQ : IN std_logic;
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M_CONV_OSC : IN std_logic;
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SEL_ROS_REQ : IN std_logic;
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MACH_RST_3 : IN std_logic;
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CLOCK_ON : IN std_logic;
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SAR_DLYD_STOP_SW : IN std_logic;
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MATCH : IN std_logic;
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SALS : IN SALS_Bus;
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FORCE_IJ_REQ : IN std_logic;
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MACH_START_RST : IN std_logic;
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MACH_RST_SW : IN std_logic;
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USE_BASIC_CA_DECO : IN std_logic;
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S_REG_1_DLYD : IN std_logic;
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INTERRUPT : IN std_logic;
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END_OF_E_CY_LCH : IN std_logic;
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ANY_PRIORITY_PULSE : IN std_logic;
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FORCE_IJ_REQ_LCH : IN std_logic;
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P_CONV_OSC : IN std_logic;
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MAN_OPERATION : IN std_logic;
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ALLOW_WRITE : IN std_logic;
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MACH_CHK_PULSE : IN std_logic;
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MACH_CHK_RST : IN std_logic;
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HZ_DEST_RST : IN std_logic;
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FIRST_MACH_CHK : IN std_logic;
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CHK_OR_DIAG_STOP_SW : IN std_logic;
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ANY_MACH_CHK : IN std_logic;
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MATCH_LCH : IN std_logic;
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EARLY_ROAR_STOP_SW : IN std_logic;
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ALU_CHK : IN std_logic;
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DIAGNOSTIC_SW : IN std_logic;
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CS_DECODE_X001 : IN std_logic;
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BASIC_CS0 : IN std_logic;
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SUPPR_MACH_CHK_TRAP : IN std_logic;
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Z_BUS_0 : IN std_logic;
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SAR_STOP_SW : IN std_logic;
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ROAR_STOP_SW : IN std_logic;
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ANY_PRIORITY_PULSE_PWR : IN std_logic;
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GT_CK_DECODE : IN std_logic;
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SX1_SHARE_CYCLE,SX2_SHARE_CYCLE : IN std_logic;
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SEL_T4 : IN std_logic;
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SEL_SHARE_HOLD : IN std_logic;
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SEL_CONV_OSC : IN std_logic;
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SEL_BASIC_CLOCK_OFF : IN std_logic;
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GT_J_REG_TO_A_BUS : IN std_logic;
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M_CONV_OSC_2 : IN std_logic;
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MPX_SHARE_REQ : IN std_logic;
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SYSTEM_RESET_SW : IN std_logic;
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-- Outputs
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START_SW_RST : OUT std_logic;
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E_CY_STOP_SAMPLE : OUT std_logic;
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LOAD_KEY_SW : OUT std_logic;
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LOAD_KEY_INLK : OUT std_logic;
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SET_IC_ALLOWED : OUT std_logic;
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INH_ROSAR_SET : OUT std_logic;
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STOP_REQ : OUT std_logic;
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ROS_SCAN : OUT std_logic;
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ROS_CTRL_PROC_SW : OUT std_logic;
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FT_4_LD_IND : OUT std_logic;
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LOAD_REQ_LCH : OUT std_logic;
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LOAD_IND : OUT std_logic;
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RST_SEL_CHNL_DIAG_LCHS : OUT std_logic;
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RST_LOAD : OUT std_logic;
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CLOCK_START_LCH : OUT std_logic;
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PWR_OFF_SW : OUT std_logic;
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N2ND_ERROR_STOP : OUT std_logic;
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SEL_CHNL_CPU_CLOCK_STOP : OUT std_logic;
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CLOCK_START : OUT std_logic;
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EARLY_ROAR_STOP : OUT std_logic;
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HARD_STOP_LCH : OUT std_logic;
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-- CLOCK_RST : OUT std_logic;
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-- CLOCK_STOP : OUT std_logic;
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DEBUG : OUT std_logic;
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-- Clocks
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T2,T3,T4 : IN std_logic;
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P1 : IN std_logic;
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clk : IN std_logic
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);
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END ClockStartStop;
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ARCHITECTURE slt OF ClockStartStop IS
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signal STT_RST_INLK : std_logic := '1';
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signal CLK_STT_CTRL : std_logic := '0';
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signal SET_IC_START : std_logic;
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signal SET_IC_INLK : std_logic := '1';
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signal PROCESS_STOP : std_logic := '0';
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signal PROC_STOP_LOOP_ACTIVE : std_logic;
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signal LOAD_KEY : std_logic := '0';
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signal CF100T4 : std_logic;
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signal CF_STOP : std_logic := '0';
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signal INSTRUCTION_STEP_SW : std_logic;
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signal SINGLE_CYCLE_SW : std_logic;
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signal HS_MACH_CHK, HS_ALU_CHK, HS_DIAG, HS_MATCH, HS_INSTR : std_logic;
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signal LOAD_REQ : std_logic;
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signal PWR_OFF : std_logic := '0';
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signal sSTART_SW_RST : std_logic := '0';
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signal sE_CY_STOP_SAMPLE : std_logic := '0';
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signal sLOAD_KEY_SW : std_logic;
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signal sLOAD_KEY_INLK : std_logic := '1';
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signal sSET_IC_ALLOWED : std_logic := '0';
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signal sROS_SCAN : std_logic;
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signal sLOAD_IND : std_logic := '0';
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signal sRST_SEL_CHNL_DIAG_LCHS : std_logic;
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signal sRST_LOAD : std_logic;
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signal sCLOCK_START_LCH : std_logic := '0';
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signal sPWR_OFF_SW : std_logic;
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signal sN2ND_ERROR_STOP : std_logic := '0';
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signal sSEL_CHNL_CPU_CLOCK_STOP : std_logic;
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signal sCLOCK_START : std_logic;
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signal sEARLY_ROAR_STOP : std_logic;
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signal sHARD_STOP_LCH : std_logic := '0';
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signal sCLOCK_RST : std_logic;
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signal sCLOCK_STOP : std_logic;
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signal HS_DIAG_DEGLITCHED : std_logic;
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-- The following signals are required to allow the FL components to instantiate
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signal CSC_LCH_Set,SSR_LCH_Set,SSR_LCH_Reset,ECS_LCH_Set,ECS_LCH_Reset,LKI_LCH_Set,
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LK_LCH_Set,LK_LCH_Reset,SI_LCH_Set,SI_LCH_Reset,SIA_LCH_Set,SIA_LCH_Reset,
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PS_LCH_Set,PS_LCH_Reset,CFS_LCH_Reset,CS_LCH_Set,CS_LCH_Reset,N2E_LCH_Set,N2E_LCH_Reset,
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PO_LCH_Set,HS_LCH_Set : std_logic;
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BEGIN
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-- Fig 5-03C
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-- STT RST INLK
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SRI_LCH: entity work.FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output
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-- STT RST
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SSR_LCH_Set <= ALLOW_MAN_OPER and STT_RST_INLK and not SW_START;
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SSR_LCH_Reset <= T2 or MACH_RST_SW;
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SSR_LCH: entity work.FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7
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START_SW_RST <= sSTART_SW_RST;
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-- CLK STT CTRL
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CSC_LCH_Set <= sCLOCK_RST or sE_CY_STOP_SAMPLE;
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CSC_LCH: entity work.FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5
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-- E CY STOP SAMPLE
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ECS_LCH_Set <= SET_IC_START or (FT3_MPX_SHARE_REQ and M_CONV_OSC and PROC_STOP_LOOP_ACTIVE) or
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(M_CONV_OSC and PROC_STOP_LOOP_ACTIVE and SEL_ROS_REQ) or
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(not SW_START and M_CONV_OSC and not CLK_STT_CTRL); -- "not CLK_STT_CTRL" ?? is CLK_STT_CTRL meant to be inverted?
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ECS_LCH_Reset <= MACH_RST_SW or T4;
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ECS_LCH: entity work.FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7
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E_CY_STOP_SAMPLE <= sE_CY_STOP_SAMPLE;
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-- LOAD KEY INLK
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LKI_LCH_Set <= (not SW_LOAD and MACH_RST_3) or LOAD_KEY;
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LKI_LCH: entity work.FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output
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LOAD_KEY_INLK <= sLOAD_KEY_INLK;
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-- LOAD KEY
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LK_LCH_Set <= not sLOAD_KEY_SW and sLOAD_KEY_INLK;
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LK_LCH_Reset <= T4 or sCLOCK_RST;
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LK_LCH: entity work.FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7
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sLOAD_KEY_SW <= SW_LOAD;
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LOAD_KEY_SW <= sLOAD_KEY_SW;
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-- SET IC INLK
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SI_LCH_Set <= (CLOCK_ON and SW_SET_IC) or MACH_RST_3 or sSET_IC_ALLOWED; -- MACH_RST_3 inverted??
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SI_LCH_Reset <= not SW_SET_IC; -- FMD is missing invert on switch output??
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SI_LCH: entity work.FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7
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-- SET IC
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SIA_LCH_Set <= ALLOW_MAN_OPER and not SET_IC_INLK and SW_SET_IC;
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SIA_LCH_Reset <= T2 or MACH_RST_SW;
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SIA_LCH: entity work.FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7
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SET_IC_ALLOWED <= sSET_IC_ALLOWED;
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SET_IC_START <= not FORCE_IJ_REQ_LCH and M_CONV_OSC and sSET_IC_ALLOWED; -- AC1D6
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-- PROCESS STOP
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PS_LCH_Set <= sSET_IC_ALLOWED or SW_STOP or (SAR_DLYD_STOP_SW and MATCH) or (INSTRUCTION_STEP_SW and T4);
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PS_LCH_Reset <= sSTART_SW_RST or '0'; -- ?? What is second reset input?
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PS_LCH: entity work.FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5
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DEBUG <= PROCESS_STOP; -- ?? DEBUG ??
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-- PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed??
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PROC_STOP_LOOP_ACTIVE <= ((USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed?? and inverter on AA2G5 removed??
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INH_ROSAR_SET <= PROC_STOP_LOOP_ACTIVE and not ANY_PRIORITY_PULSE; -- AC1D5
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STOP_REQ <= PROCESS_STOP and not S_REG_1_DLYD and not INTERRUPT and END_OF_E_CY_LCH; -- AC1H7
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-- CF STOP
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CF100T4 <= SALS.SALS_CF(0) and not SALS.SALS_CF(1) and not SALS.SALS_CF(2) and T4; -- AA2G5
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CFS_LCH_Reset <= (not CF100T4 and T4) or (not FORCE_IJ_REQ and not sROS_SCAN and not SW_PROC) or MACH_START_RST; -- AC1G5 AC1K6 AC1M5 AC1F2 ?? SW_INH_CF_STOP instead of SW_PROC ??
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CFS_LCH: entity work.FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5
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sROS_SCAN <= SW_SCAN;
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ROS_SCAN <= sROS_SCAN;
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ROS_CTRL_PROC_SW <= SW_PROC;
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SINGLE_CYCLE_SW <= SW_SINGLE_CYCLE;
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INSTRUCTION_STEP_SW <= SW_INSTRUCTION_STEP;
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-- LOAD REQ
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sRST_LOAD <= GT_CK_DECODE and SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3); -- AB3F7
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RST_LOAD <= sRST_LOAD;
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sRST_SEL_CHNL_DIAG_LCHS <= MACH_RST_3 or sRST_LOAD; -- AC1F5,AC1H6
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LOAD_REQ_FL: entity work.FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5
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RST_SEL_CHNL_DIAG_LCHS <= sRST_SEL_CHNL_DIAG_LCHS;
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LOAD_IND <= sLOAD_IND;
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LOAD_REQ <= sLOAD_IND;
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LOAD_REQ_LCH <= sLOAD_IND; -- AC1F2
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FT_4_LD_IND <= sLOAD_IND;
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-- CLOCK START
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CS_LCH_Set <= (LOAD_KEY and P_CONV_OSC) or (P_CONV_OSC and sE_CY_STOP_SAMPLE and not MAN_OPERATION);
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CS_LCH_Reset <= sCLOCK_RST or sCLOCK_STOP;
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CS_LCH: entity work.FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6
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CLOCK_START_LCH <= sCLOCK_START_LCH;
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sSEL_CHNL_CPU_CLOCK_STOP <= not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and T4) and
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not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_T4) and
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not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and not SEL_SHARE_HOLD) and
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not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_CONV_OSC and SEL_BASIC_CLOCK_OFF); -- AD1D2,AD1C4
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SEL_CHNL_CPU_CLOCK_STOP <= sSEL_CHNL_CPU_CLOCK_STOP;
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sCLOCK_START <= (not sSEL_CHNL_CPU_CLOCK_STOP and sCLOCK_START_LCH and not PWR_OFF) and ((GT_J_REG_TO_A_BUS or not CF_STOP) and sCLOCK_START_LCH); -- AC1E4,AC1G6 ?? CLOCK_START_LCH twice?
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CLOCK_START <= sCLOCK_START;
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-- 2ND ERR STP
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N2E_LCH_Set <= MACH_CHK_PULSE and P1;
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N2E_LCH_Reset <= MACH_CHK_RST or HZ_DEST_RST;
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N2E_LCH: entity work.FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4
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N2ND_ERROR_STOP <= sN2ND_ERROR_STOP;
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--PWR OFF
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sPWR_OFF_SW <= SW_PWR_OFF;
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PWR_OFF_SW <= sPWR_OFF_SW;
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PO_LCH_Set <= sPWR_OFF_SW and T3 and not ALLOW_WRITE;
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PO_LCH: entity work.FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4
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-- HARD STOP
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HS_MACH_CHK <= (sN2ND_ERROR_STOP and T4 and FIRST_MACH_CHK) or (CHK_OR_DIAG_STOP_SW and ANY_MACH_CHK); -- AB3F4
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sEARLY_ROAR_STOP <= MATCH_LCH and EARLY_ROAR_STOP_SW; -- AC1K5
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EARLY_ROAR_STOP <= sEARLY_ROAR_STOP;
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HS_ALU_CHK <= CHK_OR_DIAG_STOP_SW and ALU_CHK and T4; -- AB3H3
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-- Z0_DELAY: entity AR port map(Z_BUS_0,clk,Z_BUS_0_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
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-- T4_DELAY: entity AR port map(T4,clk,T4_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
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HS_DIAG <= T4 and DIAGNOSTIC_SW and CS_DECODE_X001 and BASIC_CS0 and SUPPR_MACH_CHK_TRAP and not Z_BUS_0; -- AC1J6
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-- DEGLITCH: entity DEGLITCH2 port map(HS_DIAG,clk,HS_DIAG_DEGLITCHED);
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HS_MATCH <= (SAR_STOP_SW and MATCH_LCH and T4) or (ROAR_STOP_SW and T4 and MATCH_LCH) or (T4 and SINGLE_CYCLE_SW);
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HS_INSTR <= T4 and INSTRUCTION_STEP_SW and ANY_PRIORITY_PULSE_PWR and sROS_SCAN; -- AB3H2
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HS_LCH_Set <= HS_MACH_CHK or sEARLY_ROAR_STOP or HS_ALU_CHK or HS_DIAG or HS_MATCH or HS_INSTR;
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HS_LCH: entity work.FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6
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HARD_STOP_LCH <= sHARD_STOP_LCH;
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sCLOCK_RST <= MACH_RST_3 or (sHARD_STOP_LCH and M_CONV_OSC_2) or (M_CONV_OSC_2 and not GT_J_REG_TO_A_BUS and CF_STOP); -- AC1F6,AC1G5
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-- CLOCK_RST <= sCLOCK_RST;
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sCLOCK_STOP <= (PROC_STOP_LOOP_ACTIVE and not SEL_ROS_REQ and not MPX_SHARE_REQ and T2) or (not LOAD_REQ and sLOAD_KEY_SW) or SYSTEM_RESET_SW; -- AC1H7,AC1J6,AC1J7
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-- CLOCK_STOP <= sCLOCK_STOP;
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END slt;
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