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https://github.com/ibm2030/IBM2030.git
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232 lines
8.9 KiB
VHDL
232 lines
8.9 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-05D.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- Read/Write Storage Clocks for 1st 32k
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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-- Revision 1.1 2012-04-07
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-- Changed for 64k storage: START_1ST_32K triggered for 1st *and* 2nd 32k
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY RWStgClk1st32k IS
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port
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(
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-- Inputs
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ALLOW_WRITE : IN STD_LOGIC; -- 03D
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CPU_READ_PWR : IN STD_LOGIC; -- 04D
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SEL_RD_CALL : IN STD_LOGIC; -- 12C
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MAN_RD_CALL : IN STD_LOGIC; -- 03D
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ROAR_RESTT_AND_STOR_BYPASS : IN STD_LOGIC; -- 04B
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SEL_WR_CALL : IN STD_LOGIC; -- 12C
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MAN_WR_CALL : IN STD_LOGIC; -- 03D
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CPU_WRITE_PWR : IN STD_LOGIC; -- 04D
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EARLY_LOCAL_STG : IN STD_LOGIC; -- 04D
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EARLY_M_REG_0 : IN STD_LOGIC; -- 07B
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M_REG_0 : IN STD_LOGIC; -- 07B
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MACH_RST_SW : IN STD_LOGIC; -- 03D
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-- Outputs
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READ_CALL : OUT STD_LOGIC; -- 03A,03B
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USE_LOCAL_MAIN_MEM : OUT STD_LOGIC; -- 06D
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USE_MAIN_MEMORY : OUT STD_LOGIC; -- 06D
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READ_ECHO_1, READ_ECHO_2 : OUT STD_LOGIC; -- 03D
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DATA_READY_1, DATA_READY_2 : OUT STD_LOGIC; -- 03A 03B
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WRITE_ECHO_1, WRITE_ECHO_2 : OUT STD_LOGIC; -- 03D
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-- Debug
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DEBUG1,DEBUG2,DEBUG3,DEBUG4 : OUT STD_LOGIC;
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DEBUG : OUT STD_LOGIC;
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DBG_TD1_1, DBG_TD1_2 : OUT STD_LOGIC_VECTOR(1 to 38);
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DBG_RD_OR_WR_SET1,DBG_RD_OR_WR_RST1 : OUT STD_LOGIC;
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-- Clocks
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T1,T2,T3,T4 : IN STD_LOGIC;
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CLK : IN STD_LOGIC -- 50MHz / 20ns
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);
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END RWStgClk1st32k;
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ARCHITECTURE FMD OF RWStgClk1st32k IS
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signal START_RD,START_WR : STD_LOGIC;
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signal START_1ST_32K, START_2ND_32K : STD_LOGIC;
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signal READ_CALL_TO_MEM,WRITE_CALL_TO_MEM : STD_LOGIC;
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signal sREAD_CALL : STD_LOGIC;
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signal sUSE_LOCAL_MAIN_MEM : STD_LOGIC;
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signal USE_LOCAL_Set,USE_LOCAL_Reset : STD_LOGIC;
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signal TD1 : STD_LOGIC_VECTOR(1 to 38) := (others=>'0'); -- 20ns steps 20 to 740ns
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signal RD_OR_WR_RST1, RD_OR_WR_SET1, nRD_OR_WR_SET1, CTRL_R_WIDTH1, TD1IN : STD_LOGIC;
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signal TD1_80, TD1_150, TD1_200, TD1_500, TD1_560, TD1_660, TD1_680, TD1_700 : STD_LOGIC;
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signal RD_OR_WR_SET1_RESET, dRD_OR_WR_SET1_RESET, CTRL_R_WIDTH1_RESET : STD_LOGIC;
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signal READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_2_RESET : STD_LOGIC;
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signal WRITE_ECHO_1_SET : STD_LOGIC;
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signal WRITE_ECHO_1_RESET : STD_LOGIC;
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signal READ_RST_SET1, READ_RST_SET2 : STD_LOGIC;
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signal READ_RST_RESET1, READ_RST_RESET2 : STD_LOGIC;
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signal RD_RST_CTRL1 : STD_LOGIC;
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signal WRITE_RST_SET1 : STD_LOGIC;
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signal WRITE_RST_RESET1 : STD_LOGIC;
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signal WR_RST_CTRL1 : STD_LOGIC;
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signal SET_READ_LCHS1 : STD_LOGIC;
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signal DATA_READY1_SET, DATA_READY1_RESET : STD_LOGIC;
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signal SET_READ_LCHS1_RESET : STD_LOGIC;
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signal dT1 : STD_LOGIC;
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signal sDATA_READY_1 : STD_LOGIC;
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BEGIN
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-- Fig 5-05D
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START_RD <= not ALLOW_WRITE and CPU_READ_PWR and T1; -- AA1K4
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START_WR <= ALLOW_WRITE and CPU_WRITE_PWR and T1; -- AA1K4
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sREAD_CALL <= START_RD or SEL_RD_CALL or MAN_RD_CALL; -- AA1J2
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READ_CALL <= sREAD_CALL;
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READ_CALL_TO_MEM <= sREAD_CALL and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J3,AA1C2
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WRITE_CALL_TO_MEM <= (MAN_WR_CALL or SEL_WR_CALL or START_WR) and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J2,AA1J3
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USE_LOCAL_Set <= EARLY_LOCAL_STG and READ_CALL_TO_MEM;
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USE_LOCAL_Reset <= not EARLY_LOCAL_STG and READ_CALL_TO_MEM;
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USE_LOCAL: entity work.FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2
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USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM;
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USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2
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-- START_1ST_32K <= (not EARLY_M_REG_0 and READ_CALL_TO_MEM) or (READ_CALL_TO_MEM and EARLY_LOCAL_STG) or (not M_REG_0 and WRITE_CALL_TO_MEM) or (WRITE_CALL_TO_MEM and sUSE_LOCAL_MAIN_MEM); -- CB1E2
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-- START_2ND_32K <= (READ_CALL_TO_MEM and EARLY_M_REG_0 and not sUSE_LOCAL_MAIN_MEM) or (WRITE_CALL_TO_MEM and M_REG_0 and not sUSE_LOCAL_MAIN_MEM); -- CB1E2
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START_1ST_32K <= READ_CALL_TO_MEM or WRITE_CALL_TO_MEM; -- CB1E2 combined 1st & 2nd 32k
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-- Generate timing signals relative to START_xxx_32K
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-- READ_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
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-- WRITE_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
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-- DATA_READY_n ON at 640ns OFF at 700ns (or MACH_RST_SW)
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-- First 32K
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TD1_80 <= TD1(4); -- 80ns
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TD1_150 <= TD1(8); -- 160ns
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TD1_200 <= TD1(10); -- 200ns
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TD1_500 <= TD1(25); -- 500ns
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TD1_560 <= TD1(28); -- 560ns
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TD1_660 <= TD1(33); -- 660ns
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TD1_680 <= TD1(34); -- 680ns
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TD1_700 <= TD1(35); -- 700ns
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nRD_OR_WR_SET1 <= not RD_OR_WR_SET1;
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RD_OR_WR_RST1_FL: entity work.FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1);
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RD_OR_WR_SET1_RESET <= RD_OR_WR_RST1 or MACH_RST_SW;
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-- The delay is to prevent a combinatorial loop:
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Delay_RD_OR_WR_SET1_RESET: AR port map (D=>RD_OR_WR_SET1_RESET, clk=>Clk, Q=>dRD_OR_WR_SET1_RESET);
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RD_OR_WR_SET1_FL: entity work.FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1);
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TD1IN <= not RD_OR_WR_RST1 and RD_OR_WR_SET1;
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-- READ CLOCK 0
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READ_ECHO_1_SET <= TD1_150 and SET_READ_LCHS1;
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READ_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and RD_RST_CTRL1);
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READ_ECHO_1_FL: entity work.FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns
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-- READ CLOCK 4
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DATA_READY1_SET <= TD1_560 and SET_READ_LCHS1;
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DATA_READY1_RESET <= MACH_RST_SW or (TD1_660 and RD_RST_CTRL1);
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DATA_READY1_FL: entity work.FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns
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DATA_READY_1 <= sDATA_READY_1;
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-- READ CLOCK 5
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READ_RST_SET1 <= TD1_500 and SET_READ_LCHS1;
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READ_RST_RESET1 <= MACH_RST_SW or TD1_700;
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READ_RST1_FL: entity work.FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns
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-- WRITE CLOCK 0
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WRITE_ECHO_1_SET <= TD1_150 and not SET_READ_LCHS1;
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WRITE_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and WR_RST_CTRL1);
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WRITE_ECHO_1_FL: entity work.FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns
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-- WRITE CLOCK 4
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SET_READ_LCHS1_RESET <= MACH_RST_SW or WRITE_CALL_TO_MEM; -- ??
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SET_READ_LCHS1_FL: entity work.FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL
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-- WRITE CLOCK 5
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WRITE_RST_SET1 <= TD1_500 and not SET_READ_LCHS1;
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WRITE_RST_RESET1 <= MACH_RST_SW or TD1_150; -- 150ns or 1050ns or 1500ns?
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WRITE_RST1_FL: entity work.FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns??
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-- Second 32K
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READ_ECHO_2 <= '0';
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DATA_READY_2 <= '0';
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WRITE_ECHO_2 <= '0';
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-- Debug
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DEBUG <= START_RD;
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DBG_TD1_1 <= TD1;
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DBG_RD_OR_WR_SET1 <= RD_OR_WR_SET1;
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DBG_RD_OR_WR_RST1 <= RD_OR_WR_RST1;
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delayLine: process(CLK)
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begin
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if (rising_edge(CLK)) then
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TD1 <= TD1IN & TD1(1 to TD1'right-1);
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end if;
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end process;
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-- Debug latch
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R_DEBUG: process (clk,T1,TD1IN)
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begin
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if rising_edge(clk) then
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if T1='1' and dT1='0' then
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DEBUG1 <= '0'; -- Reset on rising edge of T1
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else if (sDATA_READY_1 and T1)='1' then
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DEBUG1 <= '1'; -- Set on any DATA_READY
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end if;
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end if;
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if T1='1' and dT1='0' then
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DEBUG2 <= '0'; -- Reset on rising edge of T1
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else if (sDATA_READY_1 and T2)='1' then
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DEBUG2 <= '1'; -- Set on any DATA_READY
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end if;
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end if;
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if T1='1' and dT1='0' then
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DEBUG3 <= '0'; -- Reset on rising edge of T1
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else if (sDATA_READY_1 and T3)='1' then
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DEBUG3 <= '1'; -- Set on any DATA_READY
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end if;
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end if;
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if T1='1' and dT1='0' then
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DEBUG4 <= '0'; -- Reset on rising edge of T1
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else if (sDATA_READY_1 and T4)='1' then
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DEBUG4 <= '1'; -- Set on any DATA_READY
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end if;
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end if;
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dT1 <= T1;
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end if;
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end process;
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END FMD;
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