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154 lines
7.4 KiB
VHDL
154 lines
7.4 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-08B.vhd
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-- Creation Date: 21:55:54 27/01/2010
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-- Description:
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-- Q Register and Storage Protection
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE work.Gates_package.all;
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use work.PH;
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entity QReg_STP is
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Port (
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-- Inputs
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SA_REG : in STD_LOGIC_VECTOR (0 to 7); -- Stack address, F0-FF are MS storage keys, 00-EF are CCW storage keys
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Z_BUS : in STD_LOGIC_VECTOR (0 to 8); -- Z bus used to write to Q reg
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SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : in STD_LOGIC; -- Selector channel cycle inputs
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N_SEL_SHARE_HOLD : in STD_LOGIC; -- Selector channel share cycle
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MAIN_STG : in STD_LOGIC; -- Main Storage usage
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H_REG_5_PWR : in STD_LOGIC; -- Priority Reg from 04C
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FORCE_M_REG_123 : in STD_LOGIC; -- When setting M reg for LS, from 04D
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GT_LOCAL_STORAGE : in STD_LOGIC; -- Local Storage usage
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GT_T_REG_TO_MN, GT_CK_TO_MN : in STD_LOGIC; -- These operations inhibit storage protect when used with LS
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MAIN_STG_CP_1 : in STD_LOGIC; -- Main Storage clock pulse
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N_MEM_SELECT : in STD_LOGIC;
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N_STACK_MEMORY_SELECT : in STD_LOGIC; -- Indicates that Stack memory should be read/written
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STACK_RD_WR_CONTROL : in STD_LOGIC; -- T to indicate Stack is being Read, F to indicate Write
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E_SW_SEL_Q : in STD_LOGIC; -- E switch Q Reg selection
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MAN_STORE_PWR : in STD_LOGIC; -- Manual Store switch for setting Q Reg
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T4 : in STD_LOGIC; -- Main clock phase
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MACH_RST_2B : in STD_LOGIC; -- Main system reset
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Z_BUS_LO_DIG_PARITY : in STD_LOGIC; -- Parity of Z bus bits 4-7
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CD_REG : in STD_LOGIC_VECTOR (0 to 3); -- ALU destination - 0011 specifies Q Reg
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CLOCK_OFF : in STD_LOGIC; -- CPU clock stop
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GK, HK : in STD_LOGIC_VECTOR (0 to 3); -- Storage key from SX1, SX2
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CLK : in STD_LOGIC; -- 50MHz FPGA clock
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-- Outputs
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Q_REG_BUS : out STD_LOGIC_VECTOR (0 to 8); -- Q Reg output
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SEL_CPU_BUMP : out STD_LOGIC; -- Select usage of Aux Storage
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STACK_PC : out STD_LOGIC; -- Stack data Parity Check error
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MPX_CP : out STD_LOGIC; -- MPX clock pulse
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MAIN_STG_CP : out STD_LOGIC; -- MS clock pulse
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PROTECT_LOC_CPU_OR_MPX : out STD_LOGIC; -- Storage Protection check from CPU or MPX
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PROTECT_LOC_SEL_CHNL : out STD_LOGIC -- Storage Protection check from SX1 or SX2
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);
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end QReg_STP;
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architecture FMD of QReg_STP is
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signal Q_REG : STD_LOGIC_VECTOR(0 to 8);
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signal INH_STG_PROT : STD_LOGIC;
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signal sSTACK_PC : STD_LOGIC;
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signal UseQ : STD_LOGIC;
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signal SET_Q_HI, SET_Q_LO : STD_LOGIC;
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subtype stackData is STD_LOGIC_VECTOR(4 to 8);
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type stack is array(0 to 255) of stackData;
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signal STP_STACK : stack;
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signal STACK_DATA : stackData;
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signal Q0_GK0_HK0, Q1_GK1_HK1, Q2_GK2_HK2, Q3_GK3_HK3 : STD_LOGIC;
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signal STP : STD_LOGIC;
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signal HDWR_STG_KEYS_MAT : STD_LOGIC;
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signal CD0011 : STD_LOGIC;
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signal STACK_DATA_STROBE, READ_GATE, WRITE_GATE, INHIBIT_TIMING : STD_LOGIC;
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type delay is array(0 to 24) of std_logic;
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signal delayLine : delay := (others=>'0');
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signal setLatch, resetLatch : std_logic;
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signal latch : std_logic;
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signal INH_STG_PROT_PH_D : std_logic;
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signal Q47P_D : std_logic_vector(4 to 8);
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begin
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Q0_GK0_HK0 <= (HK(0) and SX2_SHARE_CYCLE) or (GK(0) and SX1_SHARE_CYCLE) or (Q_REG(0) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
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Q1_GK1_HK1 <= (HK(1) and SX2_SHARE_CYCLE) or (GK(1) and SX1_SHARE_CYCLE) or (Q_REG(1) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
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Q2_GK2_HK2 <= (HK(2) and SX2_SHARE_CYCLE) or (GK(2) and SX1_SHARE_CYCLE) or (Q_REG(2) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
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Q3_GK3_HK3 <= (HK(3) and SX2_SHARE_CYCLE) or (GK(3) and SX1_SHARE_CYCLE) or (Q_REG(3) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
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STP <= not INH_STG_PROT and MAIN_STG and (Q0_GK0_HK0 or Q1_GK1_HK1 or Q2_GK2_HK2 or Q3_GK3_HK3); -- BE3F4
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HDWR_STG_KEYS_MAT <= (Q0_GK0_HK0 xnor Q_REG(0)) and (Q1_GK1_HK1 xnor Q_REG(1)) and (Q2_GK2_HK2 xnor Q_REG(2)) and (Q3_GK3_HK3 xnor Q_REG(3)); -- BE3F3
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PROTECT_LOC_CPU_OR_MPX <= (not H_REG_5_PWR) and STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
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PROTECT_LOC_SEL_CHNL <= STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
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INH_STG_PROT_PH_D <= GT_T_REG_TO_MN or GT_CK_TO_MN;
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INH_STG_PROT_PH: entity PH port map(INH_STG_PROT_PH_D,GT_LOCAL_STORAGE,INH_STG_PROT); -- AA1F4
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SEL_CPU_BUMP_PH: entity PH port map(FORCE_M_REG_123,GT_LOCAL_STORAGE,SEL_CPU_BUMP); -- AA1F4
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STACK_PC <= sSTACK_PC;
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MPX_CP <= not MAIN_STG_CP_1; -- BE3D3 BE3G4
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MAIN_STG_CP <= MAIN_STG_CP_1; -- BE3G4
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CD0011 <= '1' when CD_REG="0011" else '0';
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UseQ <= (CD0011 and (N_SEL_SHARE_HOLD or (not CLOCK_OFF))) or (CLOCK_OFF and N_MEM_SELECT and N_SEL_SHARE_HOLD); -- BE3J3 BE3G4 BE3J3
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SET_Q_HI <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ); -- BE3J4
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SET_Q_LO <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ) or (STACK_RD_WR_CONTROL and STACK_DATA_STROBE); -- BE3J4
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Q03: PHV4 port map(Z_BUS(0 to 3),SET_Q_HI,Q_REG(0 to 3)); -- BE3H2
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Q47P_D <= ((Z_BUS(4 to 7) & Z_BUS_LO_DIG_PARITY) and (4 to 8 => UseQ)) or (STACK_DATA(4 to 8) and not (4 to 8 => UseQ));
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Q47P: PHV5 port map(Q47P_D, SET_Q_LO, Q_REG(4 to 8));
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Q_REG_BUS <= Q_REG;
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sSTACK_PC <= EvenParity(Q_REG(4 to 7));
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STP_FL: process(clk)
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begin
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if rising_edge(clk) then
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setLatch <= not N_STACK_MEMORY_SELECT;
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delayLine <= setLatch & delayLine(0 to 23);
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STACK_DATA_STROBE <= delayLine(7); -- 140ns
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resetLatch <= not delayLine(24);
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if (setLatch='1') then latch <= '1'; end if;
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if (resetLatch='1') then latch <= '0'; end if;
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READ_GATE <= latch and STACK_RD_WR_CONTROL;
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WRITE_GATE <= latch and not STACK_RD_WR_CONTROL;
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INHIBIT_TIMING <= latch and not READ_GATE;
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if WRITE_GATE='1' then
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STP_STACK(Conv_Integer(SA_REG)) <= Q_REG(4 to 8);
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elsif READ_GATE='1' then
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STACK_DATA <= STP_STACK(Conv_Integer(SA_REG));
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end if;
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end if;
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end process;
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end FMD;
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