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https://github.com/ibm2030/IBM2030.git
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166 lines
6.4 KiB
VHDL
166 lines
6.4 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-08C.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- Multiplexor Channel registers FO & FB
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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-- Revision 1.1 2012-04-07
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-- Revise XH & XL BU latches amd MPX_INTRPT signal
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---------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.PH;
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use work.FLVL;
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entity MpxFOFB is
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Port ( MPX_ROS_LCH : in STD_LOGIC;
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S_REG_0 : in STD_LOGIC;
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SET_FW : in STD_LOGIC;
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S_REG_1 : in STD_LOGIC;
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S_REG_2 : in STD_LOGIC;
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T3 : in STD_LOGIC;
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CK_SALS : in STD_LOGIC_VECTOR (0 to 3);
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PK_SALS : in STD_LOGIC;
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FBK_T2 : in STD_LOGIC;
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MACH_RST_SET_LCH : in STD_LOGIC;
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SALS_CS : in STD_LOGIC_VECTOR (0 to 3);
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SALS_SA : in STD_LOGIC;
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CK_0_PWR : in STD_LOGIC;
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R_REG : in STD_LOGIC_VECTOR (0 to 8);
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T1,T2 : in STD_LOGIC;
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XXH : out STD_LOGIC;
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XH : out STD_LOGIC;
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XL : out STD_LOGIC;
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FT_7_BIT_MPX_CHNL_INTRP : out STD_LOGIC;
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FT_2_BIT_MPX_OPN_LCH : out STD_LOGIC;
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SUPPR_CTRL_LCH : out STD_LOGIC;
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OP_OUT_SIG : out STD_LOGIC;
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MPX_OPN_LT_GATE : out STD_LOGIC;
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MACH_RST_MPX : out STD_LOGIC;
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MPX_INTRPT : out STD_LOGIC;
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SX1_MASK : out STD_LOGIC;
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EXT_TRAP_MASK_ON : out STD_LOGIC;
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SX2_MASK : out STD_LOGIC;
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FAK : out STD_LOGIC;
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SET_BUS_O_CTRL_LCH : out STD_LOGIC;
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MPX_BUS_O_REG : out STD_LOGIC_VECTOR (0 to 8);
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clk : in STD_LOGIC);
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end MpxFOFB;
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architecture FMD of MpxFOFB is
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signal sXXH,sXH,sXL,T3SET,X_SET : STD_LOGIC;
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signal XXH_IN,XH_IN,XL_IN : STD_LOGIC;
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signal XXHBU,XHBU,XLBU : STD_LOGIC;
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signal sMACH_RST_MPX : STD_LOGIC;
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signal CK11XX, CKX11X,CKX1X1,CK1X1X,CKXX11 : STD_LOGIC;
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signal CHNL_L,OPN_L,SUPPR_L,OUT_L : STD_LOGIC;
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signal notOP_OUT_SIG,MpxMask : STD_LOGIC;
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alias KP is PK_SALS;
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signal sFAK,sSET_BUS_O_CTRL : STD_LOGIC;
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signal BusO_Set,BusO_Reset : STD_LOGIC_VECTOR (0 to 8);
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signal sFT_7_BIT_MPX_CHNL_INTRP,sFT_2_BIT_MPX_OPN_LCH,sSUPPR_CTRL_LCH : STD_LOGIC;
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begin
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-- XL, XH and XXL bits and backup
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XXH_BU: entity PH port map (D=>sXXH, L=>SET_FW, Q=> XXHBU);
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XXH_IN <= (XXHBU and MPX_ROS_LCH) or (S_REG_0 and not MPX_ROS_LCH);
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X_SET <= T3SET or sMACH_RST_MPX;
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XXH_PH: entity PH port map (D=>XXH_IN, L=>X_SET, Q=> sXXH);
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XXH <= sXXH;
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XH_BU: entity PH port map (D=>sXH, L=>SET_FW, Q=> XHBU);
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-- XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH);
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XH_IN <= (XHBU and MPX_ROS_LCH) or (S_REG_1 and not MPX_ROS_LCH);
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XH_PH: entity PH port map (D=>XH_IN, L=>X_SET, Q=>sXH);
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XH <= sXH;
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XL_BU: entity PH port map (D=>sXL, L=>SET_FW, Q=> XLBU);
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-- XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH);
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XL_IN <= (XLBU and MPX_ROS_LCH) or (S_REG_2 and not MPX_ROS_LCH);
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XL_PH: entity PH port map (D=>XL_IN, L=>X_SET, Q=>sXL);
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XL <= sXL;
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-- MPX Flags
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T3SET <= (MPX_ROS_LCH and T3) or (FBK_T2 and CK_SALS(0) and CK_SALS(3));
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sMACH_RST_MPX <= MACH_RST_SET_LCH;
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MACH_RST_MPX <= sMACH_RST_MPX;
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CK11XX <= CK_SALS(0) and CK_SALS(1) and FBK_T2;
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CHNL_L <= sMACH_RST_MPX or CK11XX;
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MPX_CHNL: entity PH port map (D=>KP,L=>CHNL_L,Q=>sFT_7_BIT_MPX_CHNL_INTRP);
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FT_7_BIT_MPX_CHNL_INTRP <= sFT_7_BIT_MPX_CHNL_INTRP;
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CKX11X <= CK_SALS(1) and CK_SALS(2) and FBK_T2;
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OPN_L <= sMACH_RST_MPX or CKX11X;
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MPX_OPN: entity PH port map (D=>KP,L=>OPN_L,Q=>sFT_2_BIT_MPX_OPN_LCH);
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FT_2_BIT_MPX_OPN_LCH <= sFT_2_BIT_MPX_OPN_LCH;
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CK1X1X <= CK_SALS(0) and CK_SALS(2) and FBK_T2;
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SUPPR_L <= sMACH_RST_MPX or CK1X1X;
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SUPPR_CTRL: entity PH port map (D=>KP,L=>SUPPR_L,Q=>sSUPPR_CTRL_LCH);
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SUPPR_CTRL_LCH <= sSUPPR_CTRL_LCH;
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CKX1X1 <= CK_SALS(1) and CK_SALS(3) and FBK_T2;
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OUT_L <= sMACH_RST_MPX or CKX1X1;
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OP_OUT_CTRL: entity PH port map (D=>KP,L=>OUT_L,Q=>notOP_OUT_SIG);
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OP_OUT_SIG <= not notOP_OUT_SIG;
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MPX_OPN_LT_GATE <= CKX11X;
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-- External Interrupt Masks
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-- ?? Should the R_REG bits be inverted before use?
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CKXX11 <= CK_SALS(2) and CK_SALS(3) and FBK_T2;
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MPX_MASK: entity PH port map (D=>R_REG(0),L=>CKXX11,Q=>MPXMask);
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MPX_INTRPT <= sFT_7_BIT_MPX_CHNL_INTRP and MPXMask;
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SX1MASK: entity PH port map (D=>R_REG(1),L=>CKXX11,Q=>SX1_MASK);
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EXT_MASK: entity PH port map (D=>R_REG(7),L=>CKXX11,Q=>EXT_TRAP_MASK_ON);
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SX2MASK: entity PH port map (D=>R_REG(2),L=>CKXX11,Q=>SX2_MASK);
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-- MPX BUS OUT REGISTER
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sFAK <= SALS_CS(0) and SALS_CS(1) and SALS_CS(2) and SALS_CS(3) and not SALS_SA;
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FAK <= sFAK;
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sSET_BUS_O_CTRL <= sFAK and CK_0_PWR;
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SET_BUS_O_CTRL_LCH <= sSET_BUS_O_CTRL;
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BusO_Set <= R_REG and (0 to 8=>(sSET_BUS_O_CTRL and T2)); -- ??? "and T2" added to prevent incorrect setting of BUS_O
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BusO_Reset <= (0 to 8=>sSET_BUS_O_CTRL and T1);
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MPX_BUSO: entity FLVL port map (S=>BusO_Set,R=>BusO_Reset,Q=>MPX_BUS_O_REG);
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end FMD;
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