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240 lines
10 KiB
VHDL
240 lines
10 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-08D.vhd
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-- Creation Date: 21:39:37 03/22/2010
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-- Description:
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-- Multiplexor Channel Controls - FA Register - Indicators
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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-- Revision 1.1 2012-04-07
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-- Revise Mpx and 1050 signals
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---------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE work.Gates_package.all;
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USE work.Buses_package.all;
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USE work.FLL;
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entity MpxFA is
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Port ( BUS_O_REG : in STD_LOGIC_VECTOR (0 to 8);
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DIAG_SW : in STD_LOGIC;
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-- External MPX connections:
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MPX_BUS_OUT_BITS : out STD_LOGIC_VECTOR (0 to 8);
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MPX_BUS_IN_BITS : in STD_LOGIC_VECTOR (0 to 8);
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TAGS_OUT : out MPX_TAGS_OUT;
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TAGS_IN : in MPX_TAGS_IN;
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--
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FI : out STD_LOGIC_VECTOR(0 to 8); -- Mpx Bus In to CPU
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FAK : in STD_LOGIC;
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RECYCLE_RST : in STD_LOGIC;
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CK_P_BIT : in STD_LOGIC;
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ALU_CHK_LCH : in STD_LOGIC;
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CHK_SW_PROC_SW : in STD_LOGIC;
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N1050_REQ_IN : in STD_LOGIC;
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ROS_SCAN : in STD_LOGIC;
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FBK_T2 : in STD_LOGIC;
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FT5_BIT_SEL_IN : out STD_LOGIC;
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SERV_IN_SIGNAL : out STD_LOGIC;
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STATUS_IN_SIGNAL : out STD_LOGIC;
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FT3_BIT_MPX_SHARE_REQ : out STD_LOGIC;
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MPX_SHARE_REQ : out STD_LOGIC;
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T1,T2,T3 : in STD_LOGIC;
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ANY_PRIORITY_LCH : in STD_LOGIC;
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CK_SALS_PWR : in STD_LOGIC_VECTOR (0 to 3);
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SET_BUS_O_CTRL_LCH : in STD_LOGIC;
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N1401_MODE : in STD_LOGIC;
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N1050_OP_IN : in STD_LOGIC;
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N1050_CE_MODE : in STD_LOGIC;
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MPX_METERING_IN : out STD_LOGIC;
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FT7_MPX_CHNL_IN : in STD_LOGIC;
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LOAD_IND : in STD_LOGIC;
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SUPPR_CTRL_LCH : in STD_LOGIC;
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OP_OUT_SIGNAL : in STD_LOGIC;
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OP_OUT_SIG : in STD_LOGIC;
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SEL_O_FT6 : out STD_LOGIC;
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N1050_SEL_IN : out STD_LOGIC;
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n1050_SEL_O : in STD_LOGIC;
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P_1050_SEL_IN : out STD_LOGIC;
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P_1050_SEL_OUT : out STD_LOGIC;
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N1050_INSTALLED : in STD_LOGIC;
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SUPPR_O : out STD_LOGIC;
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DEBUG : inout DEBUG_BUS;
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METERING_OUT : in STD_LOGIC;
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CLOCK_OUT : in STD_LOGIC;
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CLK : in STD_LOGIC;
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-- Mpx Indicators
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OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN,
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SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT,
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SUPPRESS_OUT : out std_logic); -- 08A
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end MpxFA;
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architecture FMD of MpxFA is
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signal sSERV_IN_SIGNAL, sSTATUS_IN_SIGNAL, sADDR_OUT, sSUPPR_O, sOP_OUT : STD_LOGIC;
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signal SIS1,SIS2,SIS3 : STD_LOGIC;
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signal OP_INLK_SET, OP_INLK : STD_LOGIC;
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signal SERV_OUT, CMD_OUT : STD_LOGIC;
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signal sTAGS_OUT : MPX_TAGS_OUT;
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signal sTAGS_IN : MPX_TAGS_IN;
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signal sFT5_BIT_SEL_IN, Reset_SELO : STD_LOGIC;
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signal sn1050_SEL_OUT : STD_LOGIC;
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signal sn1050_SEL_IN : STD_LOGIC;
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signal CMD_STT_Set, RST_CMD_RSTT_ADDR_OUT, CMD_STT : STD_LOGIC;
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signal sFT3_BIT_MPX_SHARE_REQ, sSEL_O_FT6, sSUPPR_O_FT0 : STD_LOGIC;
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signal FAK_T2 : STD_LOGIC;
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signal SetAdrO2, ADDR_OUT_2, SetAdrOut, SetCmdO, RstCmdO, SetSrvO, RstSrvO : STD_LOGIC;
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signal SetCUBusyInlk, ResetCUBusyInlk, CUBusy, RST_STT_SEL_OUT : STD_LOGIC;
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signal ResetBusOCtrl, BUSOCtrl : STD_LOGIC;
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signal SetStartSelO, ResetStartSelO, StartSelO : STD_LOGIC;
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signal NO_1050_SEL_O : STD_LOGIC;
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signal SetSelReq, ResetSelReq, SetSelOInlk, SelOInlk : STD_LOGIC;
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signal SS_RECYCLE_RST : STD_LOGIC;
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signal NOT_OPL_IN : STD_LOGIC;
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begin
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STATUS_IN <= sTAGS_IN.STA_IN;
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SERVICE_IN <= sTAGS_IN.SRV_IN;
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ADDR_IN <= sTAGS_IN.ADR_IN; -- AA3F3
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OPNL_IN <= sTAGS_IN.OPL_IN; -- AA3F2 AA3F5
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SIS1 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.SRV_IN) or OP_INLK; -- AA3F2 AA3E2
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sSERV_IN_SIGNAL <= SIS1 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit
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SERV_IN_SIGNAL <= sSERV_IN_SIGNAL;
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SIS3 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.STA_IN) or (OP_INLK and not sTAGS_OUT.ADR_OUT); -- AA3D7 AA3E2
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sSTATUS_IN_SIGNAL <= SIS3 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit
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STATUS_IN_SIGNAL <= sSTATUS_IN_SIGNAL;
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OP_INLK_SET <= not sTAGS_IN.OPL_IN and T2;
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OP_INLK_FL: entity FLL port map (S=>OP_INLK_SET, R=> T1, Q=>OP_INLK); -- AA3E4 ?? R=> NOT T1 ??
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sn1050_SEL_IN <= sTAGS_IN.SEL_IN;
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n1050_SEL_IN <= sn1050_SEL_IN;
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sFT5_BIT_SEL_IN <= (sn1050_SEL_IN and not n1050_INSTALLED) or sn1050_SEL_IN; -- AA3E5 AA3E2
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FT5_BIT_SEL_IN <= sFT5_BIT_SEL_IN;
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Reset_SELO <= RECYCLE_RST or FBK_T2 or sFT5_BIT_SEL_IN; -- AA3D7 AA3E7
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CMD_STT_Set <= CK_P_BIT and FAK_T2; -- ?? FMD has FAK not FAK_T2
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RST_CMD_RSTT_ADDR_OUT <= (FAK and T1) or RECYCLE_RST; -- AA3E6 AA3E2
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CMD_STT_FL: entity FLL port map (S=>CMD_STT_Set, R=>RST_CMD_RSTT_ADDR_OUT, Q=>CMD_STT); -- AA3D7 AA3E7
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sFT3_BIT_MPX_SHARE_REQ <= (ROS_SCAN or not CMD_STT) and (N1050_REQ_IN or sTAGS_IN.REQ_IN or (ALU_CHK_LCH and CHK_SW_PROC_SW) or sTAGS_IN.OPL_IN); -- AA3F2 AA3E5 AA3G4
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MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ;
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FT3_BIT_MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ;
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sTAGS_IN.OPL_IN <= TAGS_IN.OPL_IN or (DIAG_SW and BUS_O_REG(7)); -- AA3B4
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sTAGS_IN.ADR_IN <= TAGS_IN.ADR_IN or (DIAG_SW and BUS_O_REG(6)); -- AA3B4
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sTAGS_IN.STA_IN <= TAGS_IN.STA_IN or (DIAG_SW and BUS_O_REG(4)); -- AA3B4
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sTAGS_IN.SRV_IN <= TAGS_IN.SRV_IN or (DIAG_SW and BUS_O_REG(5)); -- AA3B4
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sTAGS_IN.SEL_IN <= TAGS_IN.SEL_IN or (DIAG_SW and BUS_O_REG(0)); -- AA3B4
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sTAGS_IN.REQ_IN <= TAGS_IN.REQ_IN;
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sTAGS_IN.MTR_IN <= TAGS_IN.MTR_IN;
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MPX_BUS_OUT_BITS <= BUS_O_REG;
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FAK_T2 <= FAK and (T2 and not ANY_PRIORITY_LCH); -- AA3B7 AA3F4 AA3E6
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SetAdrO2 <= T3 and sADDR_OUT;
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ADDR_OUT_2_FL: entity FLL port map (S=>SetAdrO2, R=>RST_CMD_RSTT_ADDR_OUT, Q=>ADDR_OUT_2); -- AA3E4
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SetAdrOut <= FAK_T2 and CK_SALS_PWR(1);
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ADDR_OUT_FL: entity FLL port map (S=>SetAdrOut, R=>RST_CMD_RSTT_ADDR_OUT, Q=>sADDR_OUT); -- AA3D7 AA3E7
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ADDR_OUT <= sADDR_OUT;
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SetCmdO <= FAK_T2 and CK_SALS_PWR(2);
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RstCmdO <= not sTAGS_IN.ADR_IN and not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN;
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CMD_O: entity FLL port map (S=>SetCmdO, R=>RstCmdO, Q=>CMD_OUT); -- AA3E4 AA3E5
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sTAGS_OUT.CMD_OUT <= CMD_OUT;
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SetSrvO <= FAK_T2 and CK_SALS_PWR(3);
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RstSrvO <= not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN;
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SRV_O: entity FLL port map (S=>SetSrvO, R=>RstSrvO, Q=>SERV_OUT); -- AA3C7
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SetCUBusyInlk <= sTAGS_IN.STA_IN and ADDR_OUT_2 and FBK_T2;
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ResetCUBusyInlk <= not sADDR_OUT and T2;
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CU_BUSY_INLK: entity FLL port map (S=>SetCUBusyInlk, R=>ResetCUBusyInlk, Q=>CUBusy); -- AA3B5
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RST_STT_SEL_OUT <= not OP_OUT_SIG or CUBusy; -- AA3F7
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ResetBusOCtrl <= not sADDR_OUT and not CMD_OUT and not SERV_OUT; -- AA3D7
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BUS_O_CTRL: entity FLL port map (S=>SET_BUS_O_CTRL_LCH, R=>ResetBusOCtrl, Q=>BUSOCtrl); -- AA3J5
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SetStartSelO <= ADDR_OUT_2 and T2 and BUSOCtrl; -- AA3E6
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ResetStartSelO <= RST_STT_SEL_OUT or (not N1401_MODE and sTAGS_IN.ADR_IN) or (not ADDR_OUT_2 and Reset_SelO); -- AA3F5 AA3K3
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START_SEL_O: entity FLL port map (S=>SetStartSelO, R=>ResetStartSelO, Q=>StartSelO); -- AA3L4 AA3E7
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sSEL_O_FT6 <= not CUBusy and (StartSelO or NO_1050_SEL_O or sN1050_SEL_OUT); -- AA3E5
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SEL_O_FT6 <= sSEL_O_FT6;
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NO_1050_SEL_O <= not N1050_INSTALLED and n1050_SEL_O; -- AA3D2
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SetSelReq <= not SelOInlk and T2 and sFT3_BIT_MPX_SHARE_REQ;
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ResetSelReq <= SelOInlk or not sFT3_BIT_MPX_SHARE_REQ;
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SEL_REQ: entity FLL port map (S=>SetSelReq, R=>ResetSelReq, Q=>sN1050_SEL_OUT); -- AA3F4
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-- To Select Out Propagation in 10B
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P_1050_SEL_OUT <= sN1050_SEL_OUT;
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SetSelOInlk <= (sTAGS_IN.ADR_IN and sTAGS_IN.OPL_IN) or (N1050_OP_IN and not N1050_CE_MODE); -- AA3B7
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NOT_OPL_IN <= not sTAGS_IN.OPL_IN;
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SEL_O_INLK: entity FLL port map (S=>SetSelOInlk, R=>NOT_OPL_IN, Q=>SelOInlk); -- AA3C7
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-- sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) or not LOAD_IND or SUPPR_CTRL_LCH; -- AA3C7 AA3E5
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sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) and not LOAD_IND and SUPPR_CTRL_LCH; -- AA3C7 AA3E5 ?? AA3C7 shown as 'OR'
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SUPPR_O <= sSUPPR_O;
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SS_RECYCLE_RST <= RECYCLE_RST; -- AA3G3 Single Shot ??
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sOP_OUT <= OP_OUT_SIGNAL and not SS_RECYCLE_RST; -- AA3D6
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sTAGS_OUT.ADR_OUT2 <= ADDR_OUT_2;
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sTAGS_OUT.ADR_OUT <= sADDR_OUT;
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-- sTAGS_OUT.CMD_OUT <= CMD_OUT;
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sTAGS_OUT.SRV_OUT <= SERV_OUT;
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sTAGS_OUT.SEL_OUT <= sSEL_O_FT6; -- ??
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sTAGS_OUT.MTR_OUT <= METERING_OUT;
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sTAGS_OUT.CLK_OUT <= CLOCK_OUT;
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sTAGS_OUT.SUP_OUT <= sSUPPR_O;
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sTAGS_OUT.OPL_OUT <= sOP_OUT;
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-- sTAGS_OUT.SEL_OUT <= '0'; -- ??
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sTAGS_OUT.STA_OUT <= '0'; -- ??
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sTAGS_OUT.HLD_OUT <= '0'; -- ??
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TAGS_OUT <= sTAGS_OUT;
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FI <= MPX_BUS_IN_BITS;
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-- Output tag indicators not really shown
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SELECT_OUT <= sSEL_O_FT6;
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ADDR_OUT <= sADDR_OUT;
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COMMAND_OUT <= CMD_OUT;
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SERVICE_OUT <= SERV_OUT;
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SUPPRESS_OUT <= sSUPPR_O;
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end FMD;
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