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233 lines
8.7 KiB
VHDL
233 lines
8.7 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-10D.vhd
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-- Creation Date:
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-- Description:
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-- 1050 Typewriter Console attachment and CE section
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2012-04-07
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-- Initial release
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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use work.all;
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ENTITY n1050_ATTACH IS
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port
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(
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-- Inputs
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-- CE Cable
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CE_CABLE_IN : IN CE_IN := ("00000000",'0','0','0','0','0','0','0','0','0','0');
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-- CE DATA BUS From 1050 DATA section
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PTT_BITS : IN STD_LOGIC_VECTOR(0 to 6);
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DATA_REG : IN STD_LOGIC_VECTOR(0 to 7);
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NPL_BITS : IN STD_LOGIC_VECTOR(0 to 7);
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-- Other stuff
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TE_LCH : IN STD_LOGIC; -- 10CB5
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WRITE_UC : IN STD_LOGIC; -- 09CD6
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XLATE_UC : IN STD_LOGIC; -- 09CB6
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CPU_REQUEST_IN : IN STD_LOGIC; -- 10BD6
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n1050_OP_IN : IN STD_LOGIC; -- 10BB5
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HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3
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RDR_ON_LCH : IN STD_LOGIC; -- 10BD3
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MICRO_SHARE_LCH : IN STD_LOGIC; -- 10BC3
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PROCEED_LCH : IN STD_LOGIC; -- 10BC3
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TA_REG_POS_4 : IN STD_LOGIC; -- 10BE3
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CR_LF : IN STD_LOGIC; -- 10BE3
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TA_REG_POS_6 : IN STD_LOGIC; -- 10BE3
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n1050_RST : IN STD_LOGIC; -- 10BE2
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GT_WR_REG : IN STD_LOGIC; -- 10CB6
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FORCE_LC_SHIFT : IN STD_LOGIC; -- 10CC6
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FORCE_SHIFT_CHAR : IN STD_LOGIC; -- 10CC6
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WR_STROBE : IN STD_LOGIC; -- 09CD2
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PCH_1_HOME : IN STD_LOGIC; -- 09CD6
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HOME_RDR_STOP : IN STD_LOGIC; -- 10BB3
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TT2_POS_END : IN STD_LOGIC; -- 09CB5 - NOT IN FMD
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TT5_POS_INTRV_REQ : IN STD_LOGIC; -- 10CD5
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TT6_POS_ATTN : IN STD_LOGIC; -- 10BD6
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CPU_LINES_ENTRY : IN CONN_1050; -- 10BE3
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-- Outputs
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-- CE Cable
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CE_CABLE_OUT : OUT CE_OUT;
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-- CE DATA BUS to 10C (1050 DATA)
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CE_GT_TA_OR_TE : OUT STD_LOGIC; -- 10C
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CE_DATA_ENTER_GT : OUT STD_LOGIC; -- 10BB1 10CA4 10C
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CE_TE_DECODE : OUT STD_LOGIC; -- 10CA4 10C
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CE_MODE_AND_TE_LCH : OUT STD_LOGIC;
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n1050_CE_MODE : OUT STD_LOGIC; -- 10CB3 10BD5
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-- Other stuff
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CE_SEL_OUT : OUT STD_LOGIC; -- 10BD5
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CE_TI_DECODE : OUT STD_LOGIC; -- 09CC5
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CE_RUN_MODE : OUT STD_LOGIC; -- 09CC5
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CE_TA_DECODE : OUT STD_LOGIC; -- 10BB1
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CE_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 10C
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EXIT_MPLX_SHARE : OUT STD_LOGIC; -- 10BB5
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CE_DATA_ENTER_NC : OUT STD_LOGIC;
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-- TT3_POS_1050_OPER : OUT STD_LOGIC; -- 10BE2 10BB2 10BE2 10CE5 Moved to TT_BUS(3)
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-- TT4_POS_HOME_STT : OUT STD_LOGIC; -- 10CD2 Moved to TT_BUS(4)
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OUTPUT_SEL_AND_RDY : OUT STD_LOGIC; -- 10CD4
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n1050_OPER : OUT STD_LOGIC; -- 10CC4 10CE4
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PUNCH_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- 10CE1
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READ_INTLK_RST : OUT STD_LOGIC; -- 10BA1
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PUNCH_1_CLUTCH : OUT STD_LOGIC; -- 10CE1 10AC1
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-- PCH_1_CLUTCH_1050 : OUT STD_LOGIC; -- 09CE1 10BA1 09CD5
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REQUEST_KEY : OUT STD_LOGIC; -- 10BE4
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RDR_1_CLUTCH : OUT STD_LOGIC;
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-- In/Out TT bus
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TT_BUS : INOUT STD_LOGIC_VECTOR(0 to 7);
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GTD_TT3 : IN STD_LOGIC;
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-- Hardware Serial Port
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serialInput : in Serial_Input_Lines;
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serialOutput : out Serial_Output_Lines;
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-- Clocks
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T1,T2,T3,T4 : IN STD_LOGIC;
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P1,P2,P3,P4 : IN STD_LOGIC;
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clk : IN STD_LOGIC
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);
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END n1050_ATTACH;
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ARCHITECTURE FMD OF n1050_ATTACH IS
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signal sCE_TA_DECODE, sCE_TE_DECODE : STD_LOGIC;
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signal sCE_DATA_ENTER_GT : STD_LOGIC;
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signal sn1050_CE_MODE : STD_LOGIC;
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signal sPUNCH_1_CLUTCH : STD_LOGIC;
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signal sRDR_1_CLUTCH : STD_LOGIC;
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signal sOUTPUT_SEL_AND_RDY : STD_LOGIC;
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signal TT1_POS_RDR_2_RDY, sTT3_POS_1050_OPER, sTT4_POS_HOME_STT : STD_LOGIC;
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signal PCH_CONN_ENTRY : PCH_CONN;
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signal RDR_1_CONN_EXIT : RDR_CONN;
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signal CPU_LINES_EXIT : CONN_1050;
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BEGIN
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-- Fig 5-10D
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sCE_TA_DECODE <= CE_CABLE_IN.CE_TA_DECODE;
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CE_TA_DECODE <= sCE_TA_DECODE;
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CE_GT_TA_OR_TE <= (CE_CABLE_IN.CE_TA_DECODE and sCE_DATA_ENTER_GT) or (sCE_TE_DECODE and sCE_DATA_ENTER_GT); -- AC2G5
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sCE_DATA_ENTER_GT <= CE_CABLE_IN.CE_TI_OR_TE_RUN_MODE;
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CE_DATA_ENTER_GT <= sCE_DATA_ENTER_GT;
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-- CE cable entry
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CE_BUS <= CE_CABLE_IN.CE_BIT; -- AC2M3
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sCE_TE_DECODE <= CE_CABLE_IN.CE_TE_DECODE; -- AC2M2
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CE_TE_DECODE <= sCE_TE_DECODE;
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CE_SEL_OUT <= CE_CABLE_IN.CE_SEL_OUT; -- AC2M2
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CE_TI_DECODE <= CE_CABLE_IN.CE_TI_DECODE; -- AC2M2
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CE_RUN_MODE <= not CE_CABLE_IN.CE_MODE; -- AC2M2
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CE_MODE_AND_TE_LCH <= (TE_LCH and sn1050_CE_MODE) or CE_CABLE_IN.CE_SEL_OUT; -- AC2E7
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sn1050_CE_MODE <= CE_CABLE_IN.CE_MODE;
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n1050_CE_MODE <= sn1050_CE_MODE;
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EXIT_MPLX_SHARE <= CE_CABLE_IN.CE_EXIT_MPLX_SHARE;
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CE_DATA_ENTER_NC <= CE_CABLE_IN.CE_DATA_ENTER_NC;
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-- CE cable exit
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CE_CABLE_OUT.PTT_BITS <= PTT_BITS;
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CE_CABLE_OUT.DATA_REG <= DATA_REG;
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CE_CABLE_OUT.RDR_1_CLUTCH <= sRDR_1_CLUTCH;
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CE_CABLE_OUT.WRITE_UC <= WRITE_UC;
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CE_CABLE_OUT.XLATE_UC <= XLATE_UC;
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CE_CABLE_OUT.PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
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CE_CABLE_OUT.NPL <= NPL_BITS;
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CE_CABLE_OUT.OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
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CE_CABLE_OUT.TT <= TT_BUS(0 to 2) & GTD_TT3 & TT_BUS(4 to 7);
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CE_CABLE_OUT.CPU_REQUEST_IN <= CPU_REQUEST_IN;
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CE_CABLE_OUT.n1050_OP_IN <= n1050_OP_IN;
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CE_CABLE_OUT.HOME_RDR_STT_LCH <= HOME_RDR_STT_LCH;
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CE_CABLE_OUT.RDR_ON_LCH <= RDR_ON_LCH;
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CE_CABLE_OUT.MICRO_SHARE_LCH <= MICRO_SHARE_LCH;
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CE_CABLE_OUT.PROCEED_LCH <= PROCEED_LCH;
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CE_CABLE_OUT.TA_REG_POS_4 <= TA_REG_POS_4;
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CE_CABLE_OUT.CR_LF <= CR_LF;
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CE_CABLE_OUT.TA_REG_POS_6 <= TA_REG_POS_6;
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CE_CABLE_OUT.n1050_RST <= n1050_RST;
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-- RDR connection (output)
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-- FORCE_LC_SHIFT and FORCE_SHIFT_CHAR makes 0111110 (downshift)
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-- FORCE_SHIFT_CHAR makes 0001110 (upshift)
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-- We remove this in favour of simple ASCII on the output
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-- RDR_1_CONN_EXIT.RDR_BITS <= (PTT_BITS(0) and GT_WR_REG) -- C
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-- & ((PTT_BITS(1) and GT_WR_REG) or FORCE_LC_SHIFT) -- B
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-- & ((PTT_BITS(2) and GT_WR_REG) or FORCE_LC_SHIFT) -- A
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-- & ((PTT_BITS(3) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 8
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-- & ((PTT_BITS(4) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 4
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-- & ((PTT_BITS(5) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 2
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-- & (PTT_BITS(6) and GT_WR_REG); -- 1
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RDR_1_CONN_EXIT.RDR_BITS <= PTT_BITS;
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RDR_1_CONN_EXIT.RD_STROBE <= WR_STROBE;
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CPU_LINES_EXIT <= CPU_LINES_ENTRY;
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-- TT Bus
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TT_BUS(1) <= TT1_POS_RDR_2_RDY;
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TT_BUS(2) <= TT2_POS_END;
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TT_BUS(3) <= sTT3_POS_1050_OPER;
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-- TT3_POS_1050_OPER <= sTT3_POS_1050_OPER;
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TT_BUS(4) <= sTT4_POS_HOME_STT;
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-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
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TT_BUS(5) <= TT5_POS_INTRV_REQ;
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TT_BUS(6) <= TT6_POS_ATTN;
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-- PCH connections (input)
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PUNCH_BITS <= PCH_CONN_ENTRY.PCH_BITS; -- AC2L4
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READ_INTLK_RST <= '1' when PCH_CONN_ENTRY.PCH_BITS="0000000" else '0'; -- AC2E3
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sPUNCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050; -- AC2M2 AC2J7
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PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
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-- PCH_1_CLUTCH_1050 <= sPUNCH_1_CLUTCH;
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TT1_POS_RDR_2_RDY <= PCH_CONN_ENTRY.RDR_2_READY; -- AC2M5 AC2L5
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sTT3_POS_1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- AC2J5
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sTT4_POS_HOME_STT <= PCH_CONN_ENTRY.HOME_RDR_STT_LCH; -- AC2M5 AC2L5
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-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
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sOUTPUT_SEL_AND_RDY <= PCH_CONN_ENTRY.HOME_OUTPUT_DEV_RDY;
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OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
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sRDR_1_CLUTCH <= PCH_CONN_ENTRY.RDR_1_CLUTCH_1050; -- AC2M4
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RDR_1_CLUTCH <= sRDR_1_CLUTCH;
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n1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- FA1D4
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REQUEST_KEY <=PCH_CONN_ENTRY.REQ_KEY; -- FA1D4
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console : entity ibm1050 port map(
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SerialIn => PCH_CONN_ENTRY,
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SerialOut => RDR_1_CONN_EXIT,
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SerialControl => CPU_LINES_EXIT,
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serialInput => serialInput,
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serialOutput => serialOutput,
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clk => clk);
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END FMD;
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