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109 lines
4.0 KiB
VHDL
109 lines
4.0 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-05A.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- R Reg (MSDR) Indicators and Checks
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY RIndsChks IS
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port
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(
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-- Inputs
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TEST_LAMP : IN STD_LOGIC; -- 04A
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R_REG_BUS : IN STD_LOGIC_VECTOR(0 to 7);
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R_REG_BUS_P : IN STD_LOGIC;
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G_REG_1 : IN STD_LOGIC;
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V_REG_6,V_REG_7 : IN STD_LOGIC;
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GM_WM_DETECTED : IN STD_LOGIC; -- 06C
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CARRY_1_LCHD : IN STD_LOGIC; -- 06A
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S_REG_1 : IN STD_LOGIC; -- 07B
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W3_TO_MATCH : IN STD_LOGIC; -- 01B
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ROS_SCAN : IN STD_LOGIC; -- 03C
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GT_SW_MACH_RST : IN STD_LOGIC; -- 03A
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-- Outputs
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IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
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IND_MSDR_P : OUT STD_LOGIC;
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R_REG_PC : OUT STD_LOGIC; -- 07A
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R_REG_VALID_DEC_DIGIT : OUT STD_LOGIC; -- 02A
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N1BC_OR_R1 : OUT STD_LOGIC; -- 02A
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S_REG_1_OR_R_REG_2 : OUT STD_LOGIC; -- 02A
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G_REG_1_OR_R_REG_3 : OUT STD_LOGIC; -- 02A
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V67_00_OR_GM_WM : OUT STD_LOGIC; -- 02A
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N1401_MODE : OUT STD_LOGIC; -- 05B,06C,07A,01B,04D,13C
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-- Clocks
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T2 : IN STD_LOGIC;
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CLK : IN STD_LOGIC
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);
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END RIndsChks;
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ARCHITECTURE FMD OF RIndsChks IS
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signal V67_EQUALS_00 : STD_LOGIC;
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signal N1401_MODE_SET,N1401_MODE_RESET : STD_LOGIC;
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signal sN1401_MODE : STD_LOGIC;
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BEGIN
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-- Fig 5-05A
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IND_MSDR <= R_REG_BUS or (0 to 7 => TEST_LAMP);
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IND_MSDR_P <= R_REG_BUS_P or TEST_LAMP;
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R_REG_PC <= EvenParity(R_REG_BUS & R_REG_BUS_P); -- AA1K6
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R_REG_VALID_DEC_DIGIT <= ((not R_REG_BUS(0) or not R_REG_BUS(1)) and (not R_REG_BUS(0) or not R_REG_BUS(2))) and
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((not R_REG_BUS(4) or not R_REG_BUS(5)) and (not R_REG_BUS(4) or not R_REG_BUS(6))); -- ?? *and* or *or* as per MDM?
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N1401_MODE_SET <= W3_TO_MATCH and not ROS_SCAN; -- AC1C4
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N1401_MODE_RESET <= T2 or GT_SW_MACH_RST;
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MODE1401: entity work.FLL port map(N1401_MODE_SET,N1401_MODE_RESET,sN1401_MODE); -- AB2B2,AB1B3,AB2C2
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N1401_MODE <= sN1401_MODE;
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V67_EQUALS_00 <= not V_REG_6 and not V_REG_7; -- AA1H6
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-- AB2C2,AB2B2:
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N1BC_OR_R1 <= (not sN1401_MODE or R_REG_BUS(1)) and ((CARRY_1_LCHD and not sN1401_MODE) or sN1401_MODE);
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S_REG_1_OR_R_REG_2 <= (not sN1401_MODE or R_REG_BUS(2)) and (sN1401_MODE or S_REG_1);
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G_REG_1_OR_R_REG_3 <= (not sN1401_MODE or R_REG_BUS(3)) and (sN1401_MODE or (not sN1401_MODE and G_REG_1));
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V67_00_OR_GM_WM <= (not sN1401_MODE or GM_WM_DETECTED) and ((not sN1401_MODE and V67_EQUALS_00) or sN1401_MODE);
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END FMD;
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