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140 lines
5.9 KiB
VHDL
140 lines
5.9 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-07B2.vhd
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-- Creation Date: 01/11/09
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-- Description:
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-- S Register
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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-- Revision 1.1 2012-04-07
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-- Change GT_CS_OPT to level-triggered latch
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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-- use work.all;
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ENTITY SReg IS
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port
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(
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SA : IN STD_LOGIC; -- 01C
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CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
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CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
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N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
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Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B
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GT_CARRY_TO_S3 : IN STD_LOGIC;
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S : OUT STD_LOGIC_VECTOR(0 to 7);
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GT_Z_BUS_TO_S : OUT STD_LOGIC;
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S_REG_RST : OUT STD_LOGIC;
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CTRL_REG_RST : IN STD_LOGIC; -- 01C
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MAN_STOR_PWR : IN STD_LOGIC; -- 03D
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STORE_S_REG_RST : IN STD_LOGIC; -- 03D
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E_SW_SEL_S : IN STD_LOGIC; -- 04C
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MACH_RST_2C : IN STD_LOGIC; -- 06B
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T_REQUEST : IN STD_LOGIC; -- 10BC6
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FB_K_T2_PULSE : OUT STD_LOGIC;
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CS_DECODE_X001 : OUT STD_LOGIC; -- 03C
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BASIC_CS_0 : OUT STD_LOGIC; -- 03C
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P1, T1, T2, T3, T4 : IN STD_LOGIC;
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clk : IN STD_LOGIC
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);
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END SReg;
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ARCHITECTURE FMD OF SReg IS
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signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7);
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signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC;
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signal CD_0110 : STD_LOGIC;
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signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC;
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signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC;
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signal sGT_Z_BUS_TO_S : STD_LOGIC;
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signal sS_REG_RST : STD_LOGIC;
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signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC;
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signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7);
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BEGIN
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-- Fig 5-07B
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CS_X000 <= '1' when CS(1 to 3)="000" else '0';
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CS_X001 <= '1' when CS(1 to 3)="001" else '0';
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CS_DECODE_X001 <= CS_X001;
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CS_X010 <= '1' when CS(1 to 3)="010" else '0';
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CS_X011 <= '1' when CS(1 to 3)="011" else '0';
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CS_X100 <= '1' when CS(1 to 3)="100" else '0';
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CS_X101 <= '1' when CS(1 to 3)="101" else '0';
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CS_X110 <= '1' when CS(1 to 3)="110" else '0';
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CS_X111 <= '1' when CS(1 to 3)="111" else '0';
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CS_X01X <= '1' when CS(1 to 2)="01" else '0';
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CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0';
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CS_0XXX <= '1' when CS(0)='0' else '0';
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CS_1XXX <= '1' when CS(0)='1' else '0';
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GT_CS_OPT_Set <= SA and P1;
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GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
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-- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
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GT_CS_OPT: entity work.FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5
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GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
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BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
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sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
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BASIC_CS_0 <= sBASIC_CS_0;
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FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3
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CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6
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sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
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GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S;
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sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
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S_REG_RST <= sS_REG_RST;
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SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7
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SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7
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SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7
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SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7
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SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7
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SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7
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SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7
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SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7
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RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7
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RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7
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RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7
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RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7
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RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
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RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
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RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
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RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
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S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
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S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
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S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
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END FMD;
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