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37 lines
711 B
VHDL
37 lines
711 B
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15:34:05 06/17/2015
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-- Design Name:
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-- Module Name: PH - slt
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Simple PH (polarity hold) latch
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entity PH is port( D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end;
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architecture slt of PH is
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begin
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process(L,D)
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begin
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if (L='1') then
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Q <= D;
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end if;
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end process;
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end slt;
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