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ibm2030.IBM2030/CLD/qb681.rtf
Lawrence Wilkinson bf39525f5f Add CLD files in RTF format
2021-07-23 21:56:41 +02:00

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\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Reg contents Machine Check Reg 0 1 2 3 4 5 6 7 Micro trace}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S CC A B MN CR SAL ROS R ALU BA7 B6F BF3 B8A B71 B73 BB0 B60 BB1 B8A}
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\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 00 (invalid) BB1 B8A B71 B73 BB0 B60 BB1 B8A B71 B73}
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\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} I 00}{\f0\fs14\lang1033{\*\listtag0} B6C BAB*}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B J FF}{\f0\fs14\lang1033{\*\listtag0} *}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} U 00}{\f0\fs14\lang1033{\*\listtag0} *ABF when in system reset start}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} V 99}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} H 00}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} -----------------------------------------------------------------------------------------------------------------------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D}{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 11 --- 0BA7 11 --- 0B6F 11 --- 0BF3 | 10 --- 0B8A 01 --- 0B71 11 --- 0B73 00 --- 0BB0 00 --- 0B60 01 --- 0BB1 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} K 1000,0 | K 1101,0 | K 0011,0 | --K 1000,0 DECA K 1011,0 | K 1000,0 | K 0101,0 | K 1101,0B | K 1111,0 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} A 0^DL>Z | A 0-0>T | A MCL^KL>Z | A G0+-L0>Z | A 0^L0>J | A 0!L>R | A J^R>Z | A L+L>LC | A MC^K>G | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}E QB671.LJE------------*S UV>MN MPX S*------S WRITE |*------S UV>MN MS S*------S STORE |*--O---S UV>MN MPX S*------| |*------S WRITE |*--O---S IJ>MN MS S*------S WRITE |*---}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (11) | | | | | | C TREQ>S1 | | | | | | C 1>S0 | | C 1>S0 | C 0>S0 | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} More MC C 1>OE | C 0>LOAD | R WRAP>X6 | C 1>OE | | C 0>MC | C 1>OE | R ACFORCE | | C 0>LOAD | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 1,1 6FR R 1,1 F3R R 1,0 8AR R 0,Z=0 71R | R 1,1 73R ------R 0,0 B0R R 0,S3 60R | R 0,1 B1R R 1,0 8AR}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} E1-- 11 --EA E2-- 11 --EB E3-- 10 --EC E4-- 0* --ED | E5-- 11 --EE | E6-- 00 --EF E7-- 0* --EG | E8-- 01 --EH E9-- 10 --EJ}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Set even latch Restore byte Check for ALU Set even latch | Reset MC-reg | Set ALU chk lat Detect stor | L=02,04,08,10 FF^FF=00}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F}{\f0\fs14\lang1033{\*\listtag0} Causes Z4 pos from UCW to and stor data | Store even | R=01,02,04,08 data. A-B reg | 20,40,80,00.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} ALU check. address 0099. checks, | parity char. | 10,20,40,80,00. checks. | Reset ALU chk}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} OE=1 may Load resets test wrap may | in J-reg. | Each position AC force may | latch. I-reg}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} cause ASCII even latch reset MC-reg. | | must cause reset ALU chk | causes stor}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} branch to | | ALU check. mch ck latch. | adr. check}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G}{\f0\fs14\lang1033{\*\listtag0} B6D | | | Incorrect}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | micro word}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | causes CN,CR}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | and ROS addr ck}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ------------------------------------------------------------------+-------------------+----------------------------------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H}{\f0\fs14\lang1033{\*\listtag0} | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 00 --- 0B70 | 11 --- 0ABF}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | K 1011,0 | | K 1011,0 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | A SP+0+1>L | | A G+0>S |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}J | ----S UV>MN MPX S*- ----S WRITE |*-------------------------------------------------------------------------------QA951------JFE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | C ANSNZ>S2 | (11,10)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | C 0>MC | | C 0>MC |}{\f0\fs14\lang1033{\*\listtag0} To System}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | R 1,1 73R | R 1,1BC BAR}{\f0\fs14\lang1033{\*\listtag0} Reset}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | J5-- 11 --JE | J6-- 1* --JF}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 1BC branches}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K}{\f0\fs14\lang1033{\*\listtag0} | | after 128 pass}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 01 --- 0B61 00 --- 0B6C 00 --- 0BA8 11 --- 0BAB | 01 --- 0ABD 00 --- 0ABC 10 --- 0B62}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 1011,0 | K 0001,0 | K 1011,0 DECA K 1101,1 | | | | K 1011,0 DECA K 1011,0 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A 0+L0>VC | A MC^KL>G | A DH.+-L0>Z | A 0+R+1>R | | A FTL^0>R | A FI^+-0>Z | A 0-0>Z |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}L ----| |*------S T>MN MPX S*--O---S WRITE |*- ----| |*--O---| |*------S WRITE K>W R*------| |*-----------------------------------QB611------LHE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C 0>S6 | C 0>S6 | | C 1>S7 | | | | | | | C 0>S7 | C ANSNZ>S2 | (11)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ----C 0>MC | ----| | | C 0>MC | | | C 0>LOAD | | | | | C 0>MC |}{\f0\fs14\lang1033{\*\listtag0} Repeat test}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | R 0,0 6CR | R S6,S7 A8R | R 0,G7 6CR | | R R0,CA0A>W BDR R 0,0 BCR R 1,0 62R R 1,1 07R}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | L2-- 00 --LB | L3-- ** --LC | L4-- 0* --LD | | L5-- *1 --LE L6-- 00 --LF L7-- 10 --LG L8-- 11 --LH}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | Reset MC reg | | 08.+-00=22 | | R0=1 when R5 is set to 1 Reset ALU check Reset MC-reg}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}M}{\f0\fs14\lang1033{\*\listtag0} | Carry 0 causes | | Sum 0 position | | test run from if FT5 is used latch. Zero test stop}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | ALU chk. | | causes ALU chk | | syst rst or IPL. to loop test Set supr. malf. must occur if}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | Reset MC-reg | | R is increment trap latch if supr malf trap}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | | | to cause test R5=0 to stop latch on with}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | | | to repeat 128 on A-reg chk addr B07}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}N}{\f0\fs14\lang1033{\*\listtag0} | | O-------------------+-- times caused by indicated.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | | blank mpx bus 1.Press Start}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | |}{\f0\fs14\lang1033{\*\listtag0} in. ALU chk to repeat test}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | |}{\f0\fs14\lang1033{\*\listtag0} must be indic.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | |}{\f0\fs14\lang1033{\*\listtag0} from BA9.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | O---------------------+-------------------O}{\f0\fs14\lang1033{\*\listtag0} 1.Press Chk}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}P}{\f0\fs14\lang1033{\*\listtag0} | | | |}{\f0\fs14\lang1033{\*\listtag0} Reset.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }{\f0\fs14\lang1033{\*\listtag0} | | | | 2.Press Start.}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 01 --- 0B6D | 01 --- 0BA9 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | K 1011,0 DECA |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | A SP^0>Z | | A DL.+-L0>Z | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Q | ----| |*- ----S WRITE |--}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | C 0>S7 | | C 1>S6 | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | C 0>MC | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | R 0,1 61R | R 0,G7 6CR }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | Q3-- 01 --QC | Q4-- 0* --QD }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 80.+-00=22}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R}{\f0\fs14\lang1033{\*\listtag0} | | Reset MC-reg}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | Sum 4 position}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | causes ALU chk}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} -------------------------------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}
\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} B}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 6}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 8 | 128056 04/27/66 | Mach 2030 | Date 06/28/66 Sheet 1 QB681 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 1 | 128058 06/09/66 | Name | Log 2182 Version |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | Mode Manual | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | P.N. 837122 | Diagnostic test-basic Machine |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | IBM Corp. | Checks (continued) ID 3345 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}}}
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