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ibm2030.IBM2030/CLD/qd161.rtf
Lawrence Wilkinson bf39525f5f Add CLD files in RTF format
2021-07-23 21:56:41 +02:00

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\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} This routine is used by all interface control checks that}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} are detected by the microprogram.Machine check traps that}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}A occur when H5=1,and when channel status is not zero}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} during Unit Selection status routine,if not Test I-O,this}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} routine then goes to the error routine log out.}
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\par}\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}B QD071.CDE----------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (11) |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr Ch no | 11 --- 091F 00 --- 0928 11 --- 0928 }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} response test | K 0011 | K 1001 | K 1001,1 | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A 0+KH>R | A 0+KH>R | | | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}C QD081.ECE---------O----------------------------------------------*| |*--O---| |*--O---| |*-----------------------------------------------------------------------------------------------------QD011------CEE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (11) C 0>S4,S5 | | | | | C K>GB | (11)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr Ch no C 014V | C 014V | C 014V Selr Ch}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} response test R S4,0 28R | R 1,S7 2AR | R 1,1 13R Device not}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C3-- *0 --CC | C4-- 1* --CD | C5-- 11 --CE available}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S4=0=Sel In | Sel In is up | Rst chnl}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}D | S7=0=CC |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | ---------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 00 --- 0938 01 --- 0959 | | 10 --- 092A 11 --- 0973 00 --- 0950 01 --- 0901 }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} K 1100,0 | K 0100,0 | | --K 1111,0 | K 0110,0 | -----*K 1000 | K 1000 | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | | A SL>S | | | | A FTX+KH>Z | A 0+KH+1>U | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}E QD071.CGE-------O--------------------------*| |*------| |---O---| |*------| |*+-----| |*------| |*--O------------------------------------------------------QD181------EGE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (00) | C K>GB | C K>GA | C K>GB | C K>GB | | | | | | | (10)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr Ch | C 014V C 014V -----*C 014V ----| 014V | C 014V C 014V | Selr Ch}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Addr mismatch | R 0,1 59R R 1,0 28R | R 1,1 73R | R 0,0 50R | R 0,1 01R R AC,0 5CR | IPL Error stop}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | E2-- 01 --EB E3-- *0 --EC | E4-- 11 --ED | E5-- 00 --EE | E6-- 01 --EF E7-- *0 --EG |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} QD081.NDE-------- Reset Sel Out Addr Out | Set Infc | GR=zero | Test IPL U=1000 0001 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}F (00) Infc disconnect | Ctrl Chk | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr Ch | S=0000 XXXX | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Addr mismatch | 10 --- 0082 | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 0101,1 | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A 0+KH>S | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}G QA961.ECE-------------------------------------------------------------------------+----*| |*--- | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (10) | C K>GB | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Error in Selr | C 014V | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} ROS request | R 1,CA09>W 73R | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | G4-- 11 --GD | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | Set Chnl Ctrl Chk | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}H | S=0101-0000 | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} QD091.GDE-------------------------------------------------------------------------+-------------------------------------------- |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (00) | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr CH | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Ch status | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}J not zero | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}K | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}L | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} QD031.GCE---------O---------------------------------------------------------------- |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (10) | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | ---------------------------------------------------------------------------------------------------------------}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}M QD061.LJE---------O |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (10) | | ----------------------O--------------------------------QD171------NGE}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | 00 --- 095C 11 --- 0977 01 --- 096D 11 --- 09D7 | 10 --- 096E | (11)}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | K 1100,1 | | | K 0100 | K 1000 | | K 0100 | | Selr Ch}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | A MC>R | A GS.KL>Z | A 0+K+1>T | | A T-KL+1>T | | Error routine}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}N QD081.EGE---------O ----| |*--O---| |*------------------------O---| |*------| |*--O---| |*--- Log Out}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (10) | C K>GB | | | | | | | C 0>S2 | | | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} QD101.GEE---------- C 014V | C 014V --------------------+---C 014V C 014V C 014V }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} (10) R S1,1 75R | R 0,1 6DR | | R 1,1 D7R R 1,Z=0 6ER R 1,1 6FR }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Selr Ch N3-- *1 --NC | N4-- 01 --ND | | N6-- 11 --NF N7-- 1* --NG N8-- 1* --NH }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Infc Ctrl Chk Not IPL | Mach Chk trap | | Test Ch T=89 Ch1 T=85}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}P Type 1 Reset Sel Out | R=Mach Chk reg | | 1 or Ch 2}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S1=Mach Chk | so it can be logged | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 01 --- 0975 | 00 --- 096C |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | K 0100 | | | | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | A U+KH>U | | A T>V | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}Q ----| |*----O-| |----}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | | | }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} C 014V C 014V }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} R 0,S7 6CR R 0,1 6DR }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q4-- 0* --QD Q5-- 01 --QE }
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Not Mach T is stored in V so}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}R Chk Trap the T-reg can be used}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} U=1100 0001 to addr storage for}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} S7=0=CC the Log Out to prevent}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} storage protect checks}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} T is restored when the}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}S Selr Ch restores the}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} CPU and ROSAR}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} Q}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} D}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 1}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 6 | 128015 09/07/65 | Mach 2030 | Date 03/01/66 Sheet 1 QD161 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} 1 | 128045 11/17/65 | Name | Log 2072 Version 014 |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 128051 01/12/66 | Mode Manual | |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | 128053 02/18/66 | P.N. 837203 | Selr Channel Error ROutine |}
\par\pard\plain\ltrpar\s25\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0} | | IBM Corp. | Assembly + Initialization |}
\par\pard\plain\ltrpar\sl240\slmult1{\f0\fs14\lang1033{\*\listtag0}}}
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