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199 lines
9.5 KiB
VHDL
199 lines
9.5 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-09C.vhd
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-- Creation Date:
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-- Description:
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-- 1050 Typewriter Console input and output translation circuitry and
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-- Control Character detection
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2012-04-07
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-- Initial release
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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use work.FLL;
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ENTITY n1050_TRANSLATE IS
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port
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(
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-- Inputs
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DATA_REG_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 10C
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RDR_ON_LCH : IN STD_LOGIC; -- 10BD3
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PUNCH_1_CLUTCH_1050 : IN STD_LOGIC; -- 10DD5 aka PCH_1_CLUTCH_1050
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HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3
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CLOCK_STT_RST : IN STD_LOGIC; -- 10AC2
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RST_ATTACH : IN STD_LOGIC; -- 10BC2
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W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX
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n1050_RST : IN STD_LOGIC; -- 10BA3
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ALLOW_STROBE : IN STD_LOGIC; -- 10CB6
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PROCEED_LCH : IN STD_LOGIC; -- 10BC3
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SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6
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CE_RUN_MODE : IN STD_LOGIC; -- 10DB2
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CE_TI_DECODE : IN STD_LOGIC; -- 10DB2
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SET_LOWER_CASE : IN STD_LOGIC; -- 10CC5
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n1050_RST_LCH : IN STD_LOGIC; -- 10BA3
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READY_SHARE : IN STD_LOGIC; -- 10CE6
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-- Outputs
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TT2_POS_END : OUT STD_LOGIC; -- 10BD3
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XLATE_UC : OUT STD_LOGIC; -- 10C
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RD_SHARE_REQ_LCH : OUT STD_LOGIC; -- 10CD4 10BC3 10BD4
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READ_SHARE_REQ : OUT STD_LOGIC; -- 10BD3
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WRITE_UC : OUT STD_LOGIC; -- 10DD2
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SET_SHIFT_LCH : OUT STD_LOGIC; -- 10CC4
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PCH_1_HOME : OUT STD_LOGIC; -- 10DC5
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RUN : OUT STD_LOGIC; -- 10BB3 10CC3 10BD1 10CE4 10CD2
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UNGATED_RUN : OUT STD_LOGIC; -- 10BC4
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READ : OUT STD_LOGIC; -- 10CD4
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READ_INQ : OUT STD_LOGIC; -- 10CD4
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LC_CHARACTER, UC_CHARACTER : OUT STD_LOGIC; -- 10CC5
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WRITE_LCH : OUT STD_LOGIC; -- 10BD3 10AC1 10AA2 10BB1 10CA5 10CC3
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WRITE_MODE : OUT STD_LOGIC; -- 10CD4
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WRITE_STROBE : OUT STD_LOGIC; -- 10DC5
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WRITE_LCH_RST : OUT STD_LOGIC; -- 10BA1
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RD_OR_RD_INQ : OUT STD_LOGIC;
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DEBUG : INOUT DEBUG_BUS
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-- Clocks
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-- T1,T2,T3,T4 : IN STD_LOGIC;
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-- P1,P2,P3,P4 : IN STD_LOGIC
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);
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END n1050_TRANSLATE;
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ARCHITECTURE FMD OF n1050_TRANSLATE IS
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signal sLC_CHARACTER, sUC_CHARACTER : STD_LOGIC;
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signal DataReg4511, DataReg23not00 : STD_LOGIC;
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signal EndCode : STD_LOGIC;
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signal DataRegSpecial1, DataRegSpecial2, DataRegSpecial3, DataRegSpecial : STD_LOGIC;
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signal XLATE_UC_SET, XLATE_UC_RESET : STD_LOGIC;
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signal RD_SHARE_REQ_SET, RD_SHARE_REQ_RESET : STD_LOGIC;
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signal PREFIX_SET,PREFIX_RESET,PREFIX : STD_LOGIC;
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signal BLOCK_SHIFT_SET,BLOCK_SHIFT : STD_LOGIC;
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signal sWRITE_LCH : STD_LOGIC;
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signal UPPER_CASE_DECODE, LOWER_CASE_DECODE : STD_LOGIC;
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signal sRD_SHARE_REQ_LCH : STD_LOGIC;
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signal sREAD, sREAD_INQ, sRD_OR_RD_INQ : STD_LOGIC;
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signal DataReg01xxxxxx, DataRegLCA, DataRegLCB, DataRegLCC, DataRegLCD, DataRegLCE : STD_LOGIC;
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signal DataRegLC, DataRegUC : STD_LOGIC;
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signal PRT_IN_UC_SET, PRT_IN_UC_RESET, PRT_IN_UC : STD_LOGIC;
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signal WRITE_SET, WRITE_RESET : STD_LOGIC;
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signal sUNGATED_RUN : STD_LOGIC;
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BEGIN
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-- Fig 5-09C
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-- Incoming character handling (keyboard codes AB8421 = 234567)
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DataReg4511 <= DATA_REG_BUS(4) and DATA_REG_BUS(5); -- AC3F4 AC3D4 XX11XX
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DataReg23not00 <= DATA_REG_BUS(2) or DATA_REG_BUS(3); -- AC3B6 01XXXX 10XXXX 11XXXX
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-- EndCode <= DATA_REG_BUS(1) and DataReg4511 and not DATA_REG_BUS(2) and DATA_REG_BUS(6); -- 10x111x = EOB
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EndCode <= '1' when DATA_REG_BUS="0000100" else '0'; -- End is 04=Ctrl+D
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TT2_POS_END <= (EndCode and sRD_SHARE_REQ_LCH) or READY_SHARE; -- AC3F7 AC3F2 AC3C7 ?? *or* READY_SHARE ??
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-- UPPER_CASE_DECODE <= not DATA_REG_BUS(7) and DATA_REG_BUS(6) and DataReg4511 and not DataReg23not00; -- AC3E2 AB8421=001110=Upshift
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UPPER_CASE_DECODE <= '0';
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-- LOWER_CASE_DECODE <= DATA_REG_BUS(6) and not DATA_REG_BUS(7) and DATA_REG_BUS(2) and DATA_REG_BUS(3) and DataReg4511; -- AC3F7 AB8421=111110=Downshift
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LOWER_CASE_DECODE <= '0';
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-- The following three lines are probably wrong
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DataRegSpecial1 <= DataReg23not00 and DataReg4511 and DATA_REG_BUS(6) and DATA_REG_BUS(7); -- AC3E2 "xx1111" but not "111111"
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DataRegSpecial2 <= DataReg4511 and DATA_REG_BUS(7) and not DataReg23not00 and not DATA_REG_BUS(6); -- AC3E2 "101101" = Return
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DataRegSpecial3 <= DataReg4511 and not DATA_REG_BUS(6) and not DATA_REG_BUS(7); -- AC3B6 "xx1100"
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-- DataRegSpecial <= DataRegSpecial1 or DataRegSpecial2 or DataRegSpecial3;
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DataRegSpecial <= '0'; -- Ignore for now
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XLATE_UC_SET <= UPPER_CASE_DECODE and X_TIME; -- AC3F2
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XLATE_UC_RESET <= SET_LOWER_CASE or (X_TIME and LOWER_CASE_DECODE); -- AC3F2
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XLATE_UC_FL: entity FLL port map (S=>XLATE_UC_SET, R=>XLATE_UC_RESET, Q=>XLATE_UC); -- ?????
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RD_SHARE_REQ_SET <= not DataRegSpecial and not UPPER_CASE_DECODE and not LOWER_CASE_DECODE and sRD_OR_RD_INQ and Y_TIME;
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RD_SHARE_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH or (CE_RUN_MODE and CE_TI_DECODE);
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RD_SHARE_REQ_FL: entity FLL port map(S=>RD_SHARE_REQ_SET, R=>RD_SHARE_REQ_RESET, Q=>sRD_SHARE_REQ_LCH); -- AC3F5 AC3C7
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RD_SHARE_REQ_LCH <= sRD_SHARE_REQ_LCH;
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READ_SHARE_REQ <= sRD_SHARE_REQ_LCH and not Y_TIME; -- AC3E3
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sREAD <= HOME_RDR_STT_LCH and RDR_ON_LCH and not sWRITE_LCH; -- AC2G7
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READ <= sREAD;
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sREAD_INQ <= not sWRITE_LCH and RDR_ON_LCH and PROCEED_LCH; -- AC2G7
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READ_INQ <= sREAD_INQ;
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sRD_OR_RD_INQ <= sREAD or sREAD_INQ;
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RD_OR_RD_INQ <= sRD_OR_RD_INQ;
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PCH_1_HOME <= PUNCH_1_CLUTCH_1050 or sREAD or sREAD_INQ; -- AC2G3
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-- Outgoing character handling
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-- Prefix is 0x100111 i.e. 27 or 67
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PREFIX_SET <= not DATA_REG_BUS(0) and DATA_REG_BUS(2) and not DATA_REG_BUS(3)
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and not DATA_REG_BUS(4) and DATA_REG_BUS(5) and DATA_REG_BUS(6) and DATA_REG_BUS(7) and Z_TIME; -- AC3B7 AC3F2 AC3D6
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PREFIX_FL: entity FLL port map(S=>PREFIX_SET,R=>Y_TIME,Q=>PREFIX); -- AC3F2 AC3G5
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-- Block Shift prevents the shift mechanism from being triggered
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BLOCK_SHIFT_SET <= PREFIX and X_TIME;
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BLOCK_SHIFT_FL: entity FLL port map(S=>BLOCK_SHIFT_SET,R=>W_TIME,Q=>BLOCK_SHIFT); -- AC3F2 AC3C6
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DataReg01xxxxxx <= not DATA_REG_BUS(0) and DATA_REG_BUS(1); -- AC3D5 AC3B4
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DataRegLCA <= not DATA_REG_BUS(5) and DATA_REG_BUS(7) and DataReg01xxxxxx; -- 01xxx0x1 = 01xx0001 "/" 01xx0011 01xx1001 01xx1011 ".$,#"
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DataRegLCB <= not DATA_REG_BUS(4) and not DATA_REG_BUS(6) and DataReg01xxxxxx; -- 01xx0x0x = 01xx0000 "-&" 01xx0001 "/" 01xx0100 01xx0101
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DataRegLCC <= DATA_REG_BUS(0) and DATA_REG_BUS(1) and DATA_REG_BUS(2) and DATA_REG_BUS(3); -- AC3F5 1111xxxx = 0-9 = LC
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DataRegLCD <= DATA_REG_BUS(2) and DATA_REG_BUS(3) and not DATA_REG_BUS(6) and not DATA_REG_BUS(7)
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and DataReg01xxxxxx; -- AC3B7 0111xx00 = 01110000 01110100 01111000 01111100 "@"
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DataRegLCE <= DATA_REG_BUS(0) and not DATA_REG_BUS(1); -- AC3E5 10xxxxxx = LC
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DataRegLC <= DataRegLCA or DataRegLCB or DataRegLCC or DataRegLCD or DataRegLCE;
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DataRegUC <= not DataRegLC and DATA_REG_BUS(1);
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sLC_CHARACTER <= DataRegLC and not BLOCK_SHIFT;
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LC_CHARACTER <= sLC_CHARACTER;
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sUC_CHARACTER <= DataRegUC and not BLOCK_SHIFT;
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UC_CHARACTER <= sUC_CHARACTER;
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-- PRT_IN_UC remembers whether the printer is already in UC mode
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PRT_IN_UC_SET <= sUC_CHARACTER and Z_TIME and ALLOW_STROBE;
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PRT_IN_UC_RESET <= (sLC_CHARACTER and Z_TIME and ALLOW_STROBE) or SET_LOWER_CASE; -- AC3F4
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PRINT_IN_UC_FL: entity FLL port map(S=>PRT_IN_UC_SET,R=>PRT_IN_UC_RESET,Q=>PRT_IN_UC); -- ?????
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WRITE_UC <= PRT_IN_UC;
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-- For now the SHIFT function is disabled as it is not required for ASCII output
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-- SET_SHIFT_LCH <= not ((PRT_IN_UC and sLC_CHARACTER and sWRITE_LCH) or (sUC_CHARACTER and sWRITE_LCH and not PRT_IN_UC)); -- AC2E5 AC3D4
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SET_SHIFT_LCH <= '0';
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WRITE_SET <= not RDR_ON_LCH and not PUNCH_1_CLUTCH_1050 and HOME_RDR_STT_LCH; -- AC2G7
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WRITE_RESET <= CLOCK_STT_RST or RST_ATTACH;
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WRITE_FL : entity FLL port map(S=>WRITE_SET,R=>WRITE_RESET,Q=>sWRITE_LCH); -- AC2J5 AC2H6
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WRITE_LCH <= sWRITE_LCH;
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WRITE_LCH_RST <= sWRITE_LCH;
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WRITE_MODE <= WRITE_SET and not n1050_RST; -- AC2D7
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WRITE_STROBE <= Z_TIME and ALLOW_STROBE and sWRITE_LCH; -- AC2K6
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-- Stuff common to input and output
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sUNGATED_RUN <= sREAD_INQ or sREAD or sWRITE_LCH; -- AC2G3
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UNGATED_RUN <= sUNGATED_RUN;
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RUN <= sUNGATED_RUN and not n1050_RST_LCH; -- AC2K5 AC2H6
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END FMD;
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