github.com/j-core.j-core-ice40
1
0
Fork 0
mirror of https://github.com/j-core/j-core-ice40.git synced 2026-01-11 23:52:49 +00:00
Code Issues Releases Wiki Activity

Clean up data and instruction bus, and decoders. Hand hacked, should be auto gen

Browse Source
This commit is contained in:
J 2019-04-02 22:23:49 -04:00
parent 3ca89bdbd0
commit 23c9b785f2
3 changed files with 32 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
cpu_lattice.vhd
View File

@ -100,7 +100,7 @@ begin
data_slaves_i(DEV_SPI) <= loopback_bus(data_slaves_o(DEV_SPI));
data_slaves_i(DEV_UART0) <= loopback_bus(data_slaves_o(DEV_UART0));
data_slaves_i(DEV_DDR) <= loopback_bus(data_slaves_o(DEV_DDR));
data_slaves_i(DEV_BRAM) <= loopback_bus(data_slaves_o(DEV_BRAM));
pio_data_i.d <= (others => '0');
pio_data_i.ack <= pio_data_o.en;
@ -119,8 +119,8 @@ begin
INSERT when "10",
CONTINUE when others;
splice_instr_data_bus(instr_slaves_o(DEV_DDR), instr_slaves_i(DEV_DDR),
instrd_slaves_o(DEV_DDR), instrd_slaves_i(DEV_DDR));
splice_instr_data_bus(instr_slaves_o(DEV_BRAM), instr_slaves_i(DEV_BRAM),
instrd_slaves_o(DEV_BRAM), instrd_slaves_i(DEV_BRAM));
cpu1: cpu
port map(clk => clk, rst => rst,

34
cpu_up5k_42s.vhd
View File

@ -150,7 +150,7 @@ begin
-- data_slaves_i(DEV_SPI) <= loopback_bus(data_slaves_o(DEV_SPI));
data_slaves_i(DEV_UART0) <= loopback_bus(data_slaves_o(DEV_UART0));
-- data_slaves_i(DEV_DDR) <= loopback_bus(data_slaves_o(DEV_DDR));
-- data_slaves_i(DEV_BRAM) <= loopback_bus(data_slaves_o(DEV_BRAM));
-- Keyboard readback
pio_data_i.d(31 downto 8) <= (others => '0');
@ -172,8 +172,8 @@ begin
INSERT when "10",
CONTINUE when others;
-- splice_instr_data_bus(instr_slaves_o(DEV_DDR), instr_slaves_i(DEV_DDR),
-- instrd_slaves_o(DEV_DDR), instrd_slaves_i(DEV_DDR));
-- splice_instr_data_bus(instr_slaves_o(DEV_BRAM), instr_slaves_i(DEV_BRAM),
-- instrd_slaves_o(DEV_BRAM), instrd_slaves_i(DEV_BRAM));
cpu1: cpu
port map(clk => clk, rst => rst,
@ -191,10 +191,10 @@ begin
bram : entity work.cpu_bulk_sram
port map(clk => clk,
ibus_i => instr_slaves_o(DEV_DDR),
ibus_o => instr_slaves_i(DEV_DDR),
db_i => data_slaves_o(DEV_DDR),
db_o => data_slaves_i(DEV_DDR));
ibus_i => instr_slaves_o(DEV_BRAM),
ibus_o => instr_slaves_i(DEV_BRAM),
db_i => data_slaves_o(DEV_BRAM),
db_o => data_slaves_i(DEV_BRAM));
lcd : disp_drv port map (clk => clk, rst => rst, a => lcd_d_i, y => lcd_d_o, yl => lcd_o);
lcd_d_i.d <= data_slaves_o(DEV_SPI).d;
@ -247,22 +247,22 @@ begin
end if;
end if;
if data_slaves_o(DEV_DDR).en = '1' then
if data_slaves_o(DEV_DDR).wr = '1' then
if data_slaves_o(DEV_BRAM).en = '1' then
if data_slaves_o(DEV_BRAM).wr = '1' then
write(l, string'("SPRAM: Write:"));
write(l, to_hex_string(data_slaves_o(DEV_DDR).a));
write(l, to_hex_string(data_slaves_o(DEV_BRAM).a));
write(l, string'(" <= "));
write(l, to_hex_string(data_slaves_o(DEV_DDR).d));
write(l, to_hex_string(data_slaves_o(DEV_BRAM).d));
write(l, string'(" "));
if data_slaves_o(DEV_DDR).we(3) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
if data_slaves_o(DEV_DDR).we(2) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
if data_slaves_o(DEV_DDR).we(1) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
if data_slaves_o(DEV_DDR).we(0) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
if data_slaves_o(DEV_BRAM).we(3) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
if data_slaves_o(DEV_BRAM).we(2) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
if data_slaves_o(DEV_BRAM).we(1) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
if data_slaves_o(DEV_BRAM).we(0) = '1' then write(l, string'("1")); else write(l, string'("0")); end if;
else
write(l, string'("SPRAM: Read :"));
write(l, to_hex_string(data_slaves_o(DEV_DDR).a));
write(l, to_hex_string(data_slaves_o(DEV_BRAM).a));
write(l, string'(" => "));
write(l, to_hex_string(data_slaves_i(DEV_DDR).d));
write(l, to_hex_string(data_slaves_i(DEV_BRAM).d));
end if;
writeline(output, l);
end if;

54
data_bus_pkg.vhd
View File

@ -7,48 +7,28 @@ package data_bus_pkg is
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_UART0
,DEV_BRAM
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type data_bus_i_t is array(data_bus_device_t'left to data_bus_device_t'right) of cpu_data_i_t;
type data_bus_o_t is array(data_bus_device_t'left to data_bus_device_t'right) of cpu_data_o_t;
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
);
type ext_irq_device_t is (
DEV_EMAC,
DEV_I2C,
DEV_1PPS,
DEV_EXT
DEV_PIO,
DEV_SPI
);
type ext_to_int_data_bus_t is array(ext_bus_device_t'left to ext_bus_device_t'right) of data_bus_device_t;
type ext_to_int_irq_t is array(ext_irq_device_t'left to ext_irq_device_t'right) of integer range 0 to 7;
-- arrays for mapping mcu_lib's data bus and irq ports to the internal versions
constant ext_to_int_data : ext_to_int_data_bus_t := (
DEV_BL0 => DEV_BL0,
DEV_EMAC => DEV_EMAC,
DEV_I2C => DEV_I2C,
DEV_DDR => DEV_NONE
);
constant ext_to_int_irq : ext_to_int_irq_t := (
DEV_EMAC => 0,
DEV_I2C => 7,
DEV_1PPS => 5,
DEV_EXT => 3
DEV_PIO => 1,
DEV_SPI => 2
);
-- TODO: Should instruction bus have a DEV_NONE? Depends on if all reads
-- outside DDR should be mapped to SRAM.
type instr_bus_device_t is (
DEV_DDR,
DEV_BRAM,
DEV_SRAM);
type instr_bus_i_t is array(instr_bus_device_t'left to instr_bus_device_t'right) of cpu_instruction_i_t;
type instr_bus_o_t is array(instr_bus_device_t'left to instr_bus_device_t'right) of cpu_instruction_o_t;
@ -105,7 +85,7 @@ package body data_bus_pkg is
begin
case addr(31 downto 28) is
when x"1" =>
return DEV_DDR;
return DEV_BRAM;
when x"a" =>
case addr(27 downto 16) is
when x"bcd" =>
@ -116,8 +96,6 @@ package body data_bus_pkg is
return DEV_PIO;
when "01" =>
return DEV_SPI;
when "10" =>
return DEV_I2C;
when others =>
return DEV_NONE;
end case;
@ -125,17 +103,9 @@ package body data_bus_pkg is
return DEV_UART0;
when x"02" =>
return DEV_AIC;
when x"03" =>
return DEV_UART1;
when x"04" =>
return DEV_UARTGPS;
when others =>
return DEV_NONE;
end case;
when x"bce" =>
return DEV_EMAC;
when x"bd0" =>
return DEV_BL0;
when others =>
return DEV_NONE;
end case;
@ -189,7 +159,7 @@ package body data_bus_pkg is
return instr_bus_device_t is
begin
if is_prefix(addr, x"1") then
return DEV_DDR;
return DEV_BRAM;
else
-- TODO: Should we have a DEV_NONE here and explicitly check for SRAM's
-- prefix of zeros?