From dfd7c38c98164022187936a364d2d0e80904ec6f Mon Sep 17 00:00:00 2001 From: J Date: Fri, 8 Mar 2019 01:09:52 -0500 Subject: [PATCH] Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk --- cpu_lattice.vhd | 25 ++----------------------- lattice_tb.vhd | 11 +---------- nvc_lattice.sh | 10 +++++++--- ram.img | Bin 4672 -> 4672 bytes ram_init.vhd | 18 +++++++++--------- up5k.pcf | 26 ++++++++++++++++++-------- 6 files changed, 37 insertions(+), 53 deletions(-) diff --git a/cpu_lattice.vhd b/cpu_lattice.vhd index bef48c8..8b902e5 100644 --- a/cpu_lattice.vhd +++ b/cpu_lattice.vhd @@ -55,14 +55,6 @@ architecture behaviour of cpu_lattice is begin rst <= '1', '0' after 10 ns; --- clk_gen : process --- begin --- clk <= '0'; --- wait for 10 ns; --- clk <= '1'; --- wait for 10 ns; --- end process; - vh <= '1'; ck: SB_HFOSC generic map (clkhf_div => "0b10") @@ -132,20 +124,7 @@ begin -- intercept and print PIO and UART writes - led(7 downto 3) <= le(7 downto 3); - - rgb: SB_RGBA_DRV generic map ( CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000001", - RGB1_CURRENT => "0b000001", - RGB2_CURRENT => "0b000001") - port map ( curren => '1', - rgbleden => '1', - rgb0pwm => le(0), - rgb1pwm => le(1), - rgb2pwm => le(2), - rgb0 => led(0), - rgb1 => led(1), - rgb2 => led(2)); + led <= le; l0: process(clk) variable uart_line : line; @@ -157,7 +136,7 @@ begin -- write(l, string'("LED: Write ")); -- write(l, " at " & time'image(now)); -- writeline(output, l); - le <= pio_data_o.d(7 downto 0); + le <= pio_data_o.d(7 downto 0); end if; if data_slaves_o(DEV_UART0).wr = '1' and data_slaves_o(DEV_UART0).a = x"ABCD0104" then -- c := character'val(to_integer(unsigned(data_slaves_o(DEV_UART0).d(7 downto 0)))); diff --git a/lattice_tb.vhd b/lattice_tb.vhd index 385d9b5..9f2f2c1 100644 --- a/lattice_tb.vhd +++ b/lattice_tb.vhd @@ -20,21 +20,12 @@ architecture beh of lattice_tb is return ret; end to_hex_string; - signal clk : std_logic; signal led : std_logic_vector(7 downto 0) := x"00"; signal ol : std_logic_vector(7 downto 0) := x"00"; begin - c0: process - begin - clk <= '0'; - wait for 10 ns; - clk <= '1'; - wait for 10 ns; - end process; - fp: entity work.cpu_lattice - port map(clk => clk, led => led); + port map(led => led); p0: process(led) variable l : line; diff --git a/nvc_lattice.sh b/nvc_lattice.sh index 1c1b91e..61fe322 100644 --- a/nvc_lattice.sh +++ b/nvc_lattice.sh @@ -1,9 +1,13 @@ #!/bin/sh +rm -r work sb_ice40_components_syn + nvc -a cpu2j0_pkg.vhd components_pkg.vhd mult_pkg.vhd decode_pkg.vhd decode_body.vhd datapath_pkg.vhd cpu.vhd decode.vhd decode_core.vhd decode_table.vhd decode_table_reverse.vhd datapath.vhd register_file.vhd mult.vhd -nvc -a data_bus_pkg.vhd monitor_pkg.vhd ram_init.vhd lattice_ebr.vhd bus_monitor.vhd timeout_cnt.vhd cpu_simple_sram.vhd cpu_lattice.vhd +nvc -a data_bus_pkg.vhd monitor_pkg.vhd ram_init.vhd lattice_ebr.vhd bus_monitor.vhd timeout_cnt.vhd cpu_simple_sram.vhd -nvc -a lattice_tb.vhd +nvc --work=sb_ice40_components_syn -a clk_sim.vhd -nvc -e -V lattice_tb +nvc -L . -a cpu_lattice.vhd lattice_tb.vhd + +nvc -L . -e -V lattice_tb diff --git a/ram.img b/ram.img index 3f8d9d4eec47bec52741087b49c12f527068dcfd..f970b1611022051c783c247803e4e33bf599d3ae 100755 GIT binary patch delta 61 zcmX@0azJGRw~(oYRicHNg;|nWvZax!Ay-mqW=@KgLP$obf^TAxf`Yk%k&zV;nVKlL P28SpZ85mk}F)#oC8SM{g delta 61 zcmX@0azJGRw~(osRjOr5nt@T0v7wP!3RhBTW=@KgLP%+