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38 lines
1.4 KiB
VHDL
38 lines
1.4 KiB
VHDL
-- ******************************************************************
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-- ******************************************************************
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-- ******************************************************************
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-- This file is generated. Changing this file directly is probably
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-- not what you want to do. Any changes will be overwritten next time
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-- the generator is run.
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-- ******************************************************************
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-- ******************************************************************
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-- ******************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.decode_pack.all;
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use work.cpu2j0_components_pack.all;
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use work.mult_pkg.all;
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entity decode_table is
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port (
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clk : in std_logic;
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next_id_stall : in std_logic;
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op : in operation_t;
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t_bcc : in std_logic;
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debug : out std_logic;
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delay_jump : out std_logic;
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dispatch : out std_logic;
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event_ack_0 : out std_logic;
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ex : out pipeline_ex_t;
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ex_stall : out pipeline_ex_stall_t;
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id : out pipeline_id_t;
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ilevel_cap : out std_logic;
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mac_s_latch : out std_logic;
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mac_stall_sense : out std_logic;
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maskint_next : out std_logic;
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slp : out std_logic;
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wb : out pipeline_wb_t;
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wb_stall : out pipeline_wb_stall_t
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);
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end;
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