mirror of
https://github.com/j-core/j-core-ice40.git
synced 2026-02-26 16:54:02 +00:00
83 lines
2.9 KiB
Plaintext
83 lines
2.9 KiB
Plaintext
#-- Synopsys, Inc.
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#-- Project file /home/jeff/upd2/upd2_syn.prj
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#project files
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add_file -vhdl -lib work "../work/J1/jcore-j1/bus_monitor.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/components_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/cpu.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/cpu2j0_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/cpu_simple_sram.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/cpu_bulk_sram.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/cpu_up5k_42s.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/data_bus_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/datapath_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/datapath.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/decode.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/decode_body.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/decode_core.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/decode_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/decode_table.vhd"
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#add_file -vhdl -lib work "../work/J1/jcore-j1/decode_table_reverse.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/decode_table_rom.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/lattice_ebr.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/lattice_spr_wrap.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/monitor_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/mult.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/mult_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/register_file_sync.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/ram_init.vhd"
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add_file -vhdl -lib work "../work/J1/jcore-j1/timeout_cnt.vhd"
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add_file -vhdl -lib work "../work/J1/disp_drv/disp_drv_pkg.vhd"
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add_file -vhdl -lib work "../work/J1/disp_drv/disp_drv.vhd"
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#implementation: "upd2_Implmnt"
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impl -add upd2_Implmnt -type fpga
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#implementation attributes
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set_option -vlog_std v2001
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set_option -project_relative_includes 1
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#device options
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set_option -technology SBTiCE40UP
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set_option -part iCE40UP5K
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set_option -package SG48
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set_option -speed_grade
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set_option -part_companion ""
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#compilation/mapping options
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# mapper_options
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set_option -frequency auto
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set_option -write_verilog 0
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set_option -write_vhdl 0
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# Silicon Blue iCE40UP
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set_option -maxfan 10000
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set_option -disable_io_insertion 0
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set_option -pipe 1
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set_option -retiming 0
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set_option -update_models_cp 0
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set_option -fixgatedclocks 2
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set_option -fixgeneratedclocks 0
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# NFilter
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set_option -popfeed 0
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set_option -constprop 0
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set_option -createhierarchy 0
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# sequential_optimization_options
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set_option -symbolic_fsm_compiler 1
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# Compiler Options
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set_option -compiler_compatible 0
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set_option -resource_sharing 1
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_format "edif"
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project -result_file ./upd2_Implmnt/upd2.edf
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project -log_file "./upd2_Implmnt/upd2.srr"
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impl -active "upd2_Implmnt"
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project -run synthesis -clean
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