mirror of
https://github.com/j-core/j-core-ice40.git
synced 2026-03-03 10:06:04 +00:00
81 lines
2.8 KiB
VHDL
81 lines
2.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use work.cpu2j0_pack.all;
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use work.decode_pack.all;
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use work.cpu2j0_components_pack.all;
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use work.datapath_pack.all;
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use work.mult_pkg.all;
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entity cpu is port (
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clk : in std_logic;
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rst : in std_logic;
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db_o : out cpu_data_o_t;
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db_lock : out std_logic;
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db_i : in cpu_data_i_t;
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inst_o : out cpu_instruction_o_t;
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inst_i : in cpu_instruction_i_t;
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debug_o : out cpu_debug_o_t;
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debug_i : in cpu_debug_i_t;
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event_o : out cpu_event_o_t;
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event_i : in cpu_event_i_t);
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end entity cpu;
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architecture stru of cpu is
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signal slot, if_stall : std_logic;
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signal mac_i : mult_i_t;
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signal mac_o : mult_o_t;
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signal reg : reg_ctrl_t;
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signal func : func_ctrl_t;
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signal mem : mem_ctrl_t;
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signal instr : instr_ctrl_t;
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signal mac : mac_ctrl_t;
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signal pc : pc_ctrl_t;
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signal buses : buses_ctrl_t;
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signal t_bcc : std_logic;
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signal ibit : std_logic_vector(3 downto 0);
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signal if_dr : std_logic_vector(15 downto 0);
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signal enter_debug, debug, mask_int : std_logic;
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signal event_ack : std_logic;
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signal slp_o : std_logic;
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signal sr : sr_ctrl_t;
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signal illegal_delay_slot : std_logic;
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signal illegal_instr : std_logic;
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begin
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event_o.ack <= event_ack;
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event_o.lvl <= ibit;
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event_o.slp <= slp_o;
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event_o.dbg <= debug;
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u_decode: decode
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port map (clk => clk, rst => rst, slot => slot,
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enter_debug => enter_debug, debug => debug,
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if_dr => if_dr, if_stall => if_stall,
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illegal_delay_slot => illegal_delay_slot,
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illegal_instr => illegal_instr,
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mac_busy => mac_o.busy,
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reg => reg, func => func, sr => sr, mac => mac, mem => mem, instr => instr, pc => pc,
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buses => buses,
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t_bcc => t_bcc,
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event_i => event_i, event_ack => event_ack,
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ibit => ibit,
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slp => slp_o,
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mask_int => mask_int);
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u_mult : mult port map (clk => clk, rst => rst, slot => slot, a => mac_i, y => mac_o);
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mac_i.wr_m1 <= mac.com1; mac_i.command <= mac.com2;
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mac_i.wr_mach <= mac.wrmach; mac_i.wr_macl <= mac.wrmacl;
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u_datapath : datapath port map (clk => clk, rst => rst, slot => slot,
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debug => debug, enter_debug => enter_debug,
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db_lock => db_lock, db_o => db_o, db_i => db_i, inst_o => inst_o, inst_i => inst_i,
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debug_o => debug_o, debug_i => debug_i,
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reg => reg, func => func, sr_ctrl => sr, mac => mac, mem => mem, pc_ctrl => pc,
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buses => buses, instr => instr,
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macin1 => mac_i.in1, macin2 => mac_i.in2, mach => mac_o.mach, macl => mac_o.macl,
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mac_s => mac_i.s,
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t_bcc => t_bcc, ibit => ibit, if_dr => if_dr, if_stall => if_stall,
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mask_int => mask_int,
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illegal_delay_slot => illegal_delay_slot,
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illegal_instr => illegal_instr);
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end architecture stru;
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