mirror of
https://github.com/j-core/j-core-ice40.git
synced 2026-03-03 18:16:04 +00:00
116 lines
4.4 KiB
VHDL
116 lines
4.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package mult_pkg is
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type mult_state_t is (NOP, DMULSL, DMULSL1, DMULSL2, DMULUL, DMULUL1, DMULUL2, MACL, MACL1, MACL2, MACW, MACW1, MACWS, MACWS1, MULL, MULL1, MULL2, MULSW, MULSW1, MULUW, MULUW1);
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type mult_result_op_t is (IDENTITY, SATURATE32, SATURATE64);
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type mult_sela_t is ( M1, MB );
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type mult_size_t is ( B16, B32 );
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constant P48MAX : std_logic_vector(63 downto 0) := x"00007fffffffffff";
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constant N48MAX : std_logic_vector(63 downto 0) := x"ffff800000000000";
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constant P32MAX : std_logic_vector(63 downto 0) := x"000000007fffffff";
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constant N32MAX : std_logic_vector(63 downto 0) := x"ffffffff80000000";
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type mult_codeline_t is record
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state : mult_state_t;
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busy : std_logic;
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sela : mult_sela_t;
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shift : std_logic;
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sign : integer range 0 to 1;
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size : mult_size_t;
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mach_en : std_logic;
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macl_en : std_logic;
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use_h : std_logic;
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end record;
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type mult_microcode_t is array (mult_state_t) of mult_codeline_t;
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constant MULT_CODE : mult_microcode_t := (
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-- state busy sela shft sign size h_en l_en use_h
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( NOP, '0', M1, '0', 0, B16, '0', '0', '1' ), -- NOP
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( DMULSL1, '1', M1, '0', 1, B32, '0', '0', '1' ), -- DMULSL
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( DMULSL2, '1', M1, '1', 1, B32, '1', '1', '1' ), -- DMULSL1
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( NOP, '0', M1, '1', 1, B32, '1', '1', '1' ), -- DMULSL2
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( DMULUL1, '1', M1, '0', 0, B32, '0', '0', '1' ), -- DMULUL
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( DMULUL2, '1', M1, '1', 0, B32, '1', '1', '1' ), -- DMULUL1
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( NOP, '0', M1, '1', 0, B32, '1', '1', '1' ), -- DMULUL2
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( MACL1, '1', MB, '0', 1, B32, '0', '0', '1' ), -- MACL
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( MACL2, '1', MB, '1', 1, B32, '1', '1', '1' ), -- MACL1
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( NOP, '0', MB, '1', 1, B32, '1', '1', '1' ), -- MACL2
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( MACW1, '1', M1, '0', 1, B16, '0', '0', '1' ), -- MACW
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( NOP, '0', M1, '0', 1, B16, '1', '1', '1' ), -- MACW1
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( MACWS1, '1', M1, '0', 1, B16, '0', '0', '0' ), -- MACWS
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( NOP, '0', M1, '0', 1, B16, '0', '1', '0' ), -- MACWS1
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( MULL1, '1', M1, '0', 1, B32, '0', '0', '0' ), -- MULL
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( MULL2, '1', M1, '1', 1, B32, '0', '1', '0' ), -- MULL1
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( NOP, '0', M1, '1', 1, B32, '0', '1', '0' ), -- MULL2
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( MULSW1, '1', M1, '0', 1, B16, '0', '0', '0' ), -- MULSW
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( NOP, '0', M1, '0', 1, B16, '0', '1', '0' ), -- MULSW1
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( MULUW1, '1', M1, '0', 0, B16, '0', '0', '0' ), -- MULUW
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( NOP, '0', M1, '0', 0, B16, '0', '1', '0' ) -- MULUW1
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);
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type mult_i_t is record
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wr_m1 : std_logic;
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command : mult_state_t;
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s : std_logic;
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wr_mach : std_logic;
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wr_macl : std_logic;
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in1 : std_logic_vector(31 downto 0);
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in2 : std_logic_vector(31 downto 0);
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end record;
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type mult_o_t is record
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mach : std_logic_vector(31 downto 0);
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macl : std_logic_vector(31 downto 0);
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busy : std_logic;
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end record;
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type mult_reg_t is record
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state : mult_state_t;
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result_op : mult_result_op_t;
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m1, m2, mb : std_logic_vector(31 downto 0);
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p23 : std_logic_vector(31 downto 0);
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mach, macl : std_logic_vector(31 downto 0);
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shift : std_logic;
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abh : std_logic_vector(46 downto 0);
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end record;
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constant MULT_RESET : mult_reg_t := (state => NOP,
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result_op => IDENTITY,
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m1 => (others => '0'),
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m2 => (others => '0'),
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mb => (others => '0'),
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p23 => (others => '0'),
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mach => (others => '0'),
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macl => (others => '0'),
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shift => '0',
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abh => (others => '0')
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);
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component mult is
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port (
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clk : in std_logic;
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rst : in std_logic;
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slot : in std_logic;
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a : in mult_i_t;
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y : out mult_o_t);
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end component mult;
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function to_slv(b : std_logic; s : integer) return std_logic_vector;
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end package;
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package body mult_pkg is
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function to_slv(b : std_logic; s : integer) return std_logic_vector is
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variable r : std_logic_vector(s-1 downto 0);
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begin
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r := (others => b);
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return r;
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end function to_slv;
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end package body;
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