mirror of
https://github.com/j-core/j-core-ice40.git
synced 2026-01-11 23:52:49 +00:00
47 lines
2.0 KiB
Bash
Executable File
47 lines
2.0 KiB
Bash
Executable File
#!/bin/sh
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# Compile+simulate j1 processor for ICE 40 using https://github.com/ghdl/ghdl
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# clean files from last build (if any)
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rm -f *.o *.cf *.ghw
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# Convert VHDL source into Abstract Syntax Tree in database
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echo Analyze...
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# General CPU plumbing, not architecture specific
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ghdl -a cpu2j0_pkg.vhd components_pkg.vhd mult_pkg.vhd decode_pkg.vhd predecode_pkg.vhd datapath_pkg.vhd
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ghdl -a cpu.vhd decode.vhd decode_core.vhd decode_table.vhd datapath.vhd register_file_sync.vhd mult.vhd
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# Using the "staircase" version of the instruction decoder. The 2 other
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# versions started life as generated code from the same microcode spreadsheet,
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# are here for historical reasons and regression testing.
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#ghdl -a decode_table_reverse.vhd
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#ghdl -a decode_table_rom.vhd
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ghdl -a decode_table_simple.vhd
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# ICE40 FPGA macro block simulations and SOC plumbing
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ghdl -a data_bus_pkg.vhd ram_init.vhd lattice_ebr.vhd cpu_simple_sram.vhd
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# A simulated version of a lattice library component needs to use the same
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# library name as the lattice library.
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ghdl -a --work=sb_ice40_components_syn clk_sim.vhd
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ghdl -a cpu_lattice.vhd lattice_tb.vhd
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# Done loading source into database. Now optimize & convert AST into a netlist.
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echo Elaborate...
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ghdl -e lattice_tb
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# the ghdl "mcode" version is a bytecode interpreter / jit run via ghdl -r,
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# the llvm backend creates standalone binaries runnable as ./lattice_tb
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# it's otherwise the same command line arguments
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echo Create waveforms
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# Run briefly creating waveform outputs for use by gtkwave
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# (this is very slow, so we only do a little of it)
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ghdl -r lattice_tb --stop-time=3000ns --wave=out.ghw --ieee-asserts=disable-at-0 --activity=all > /dev/null
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# Run longer test (faster, no waveforms) allowing CPU test to complete.
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# Produces debug output from the LED driver (lattice_tb.vhd has debug
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# printfs that only work in the simulator, optimized out on real hardware).
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echo Run test ROM in processor simulation
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ghdl -r lattice_tb --stop-time=1ms --ieee-asserts=disable-at-0
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