diff --git a/PSNee/BIOS_patching.h b/PSNee/BIOS_patching.h index ff958b7..3ed7c7f 100644 --- a/PSNee/BIOS_patching.h +++ b/PSNee/BIOS_patching.h @@ -296,3 +296,94 @@ #endif +// #ifdef BIOS_PATCH + +// // Shared variables between ISR and main loop +// volatile uint8_t pulse_counter = 0; +// volatile uint8_t patch_done = 0; + +// // --- Utility function for a CPU cycle delay (NOP) --- +// static inline void delay_cycles(uint8_t cycles) { +// while(cycles--) { +// asm volatile("nop"); +// } +// } + +// // --- MAIN INTERRUPT SERVICE ROUTINE (ADDRESS AX) --- +// ISR(PIN_AX_INTERRUPT_VECTOR) { +// if (--pulse_counter == 0) { +// // --- PHASE 4: Precision Bit Alignment --- +// delay_cycles(BIT_OFFSET_CYCLES); + +// // --- PHASE 5: Data Bus Overdrive (Patch applied on DX) --- +// #ifdef INTERRUPT_RISING_HIGH_PATCH +// PIN_DX_SET; // Pre-set HIGH if needed for this variant +// #endif + +// PIN_DX_OUTPUT; // Take control of the data bus +// delay_cycles(OVERRIDE_CYCLES); + +// #ifdef INTERRUPT_RISING_HIGH_PATCH +// PIN_DX_CLEAR; // Release HIGH state +// #endif + +// PIN_DX_INPUT; // Immediately release the data bus +// PIN_AX_INTERRUPT_DISABLE; +// patch_done = 1; // Signal completion of stage 1 +// } +// } + +// // --- SECONDARY ISR (ADDRESS AY, HIGH_PATCH variant) --- +// #ifdef INTERRUPT_RISING_HIGH_PATCH +// ISR(PIN_AY_INTERRUPT_VECTOR) { +// if (--pulse_counter == 0) { +// delay_cycles(BIT_OFFSET_2_CYCLES); +// PIN_DX_OUTPUT; +// delay_cycles(OVERRIDE_2_CYCLES); +// PIN_DX_INPUT; +// PIN_AY_INTERRUPT_DISABLE; +// patch_done = 2; // Signal completion of stage 2 +// } +// } +// #endif + +// // --- BIOS Patching Main Function --- +// void Bios_Patching(void) { +// // --- PHASE 1: Signal Stabilization & Alignment (AX) --- +// if (PIN_AX_READ != 0) { // Case: Power-on, line is high +// while (PIN_AX_READ != 0); // Wait for falling edge +// while (PIN_AX_READ == 0); // Wait for next rising edge to sync +// } else { // Case: Reset, line is low +// while (PIN_AX_READ == 0); // Wait for first rising edge +// } + +// // --- PHASE 2: Reaching the Target Memory Window --- +// _delay_ms(BOOT_OFFSET_MS); + +// // --- Prepare pulse counter and patch status flag --- +// pulse_counter = PULSE_COUNT; +// patch_done = 0; + +// // --- Dynamic interrupt configuration --- +// #if defined(INTERRUPT_RISING) || defined(INTERRUPT_RISING_HIGH_PATCH) +// PIN_AX_INTERRUPT_RISING; +// #elif defined(INTERRUPT_FALLING) +// PIN_AX_INTERRUPT_FALLING; +// #endif + +// PIN_AX_INTERRUPT_ENABLE; +// while (patch_done != 1); // Wait until stage 1 is completed + +// // --- Optional secondary patch phase for HIGH_PATCH --- +// #ifdef INTERRUPT_RISING_HIGH_PATCH +// while (PIN_AY_READ != 0); // Ensure AY line is low before arming +// _delay_ms(FOLLOWUP_OFFSET_MS); + +// pulse_counter = PULSE_COUNT_2; // Reload counter for AY pulses +// PIN_AY_INTERRUPT_RISING; +// PIN_AY_INTERRUPT_ENABLE; +// while (patch_done != 2); // Wait until stage 2 is completed +// #endif +// } + +// #endif \ No newline at end of file diff --git a/PSNee/MCU.h b/PSNee/MCU.h index ed7e31f..fcbe013 100644 --- a/PSNee/MCU.h +++ b/PSNee/MCU.h @@ -260,10 +260,12 @@ #include // Global interrupt control settings - #define GLOBAL_INTERRUPT_ENABLE SREG |= (1 << 7) // Set the I-bit (bit 7) in the Status Register to enable global interrupts - #define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1 << 7) // Clear the I-bit (bit 7) in the Status Register to disable global interrupts + #define GLOBAL_INTERRUPT_ENABLE sei() + #define GLOBAL_INTERRUPT_DISABLE cli() + // #define GLOBAL_INTERRUPT_ENABLE SREG |= (1 << 7) // Set the I-bit (bit 7) in the Status Register to enable global interrupts + // #define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1 << 7) // Clear the I-bit (bit 7) in the Status Register to disable global interrupts - // Main pin configuration for input and output + // Main pin configuration // Define the main pins as inputs #define PIN_DATA_INPUT DDRB &= ~(1 << DDB0) // Set DDRB register to configure PINB0 as input diff --git a/PSNee/settings.h b/PSNee/settings.h index 41554f3..039f131 100644 --- a/PSNee/settings.h +++ b/PSNee/settings.h @@ -115,6 +115,186 @@ #define OVERRIDE_2 0.15 #endif + +// // -------- SCPH 102 -------- +// #ifdef SCPH_102 +// #define BIOS_PATCH_2 +// #define INTERRUPT_RISING + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 84 +// #define PULSE_COUNT 48 +// #define BIT_OFFSET_CYCLES 26 // 3.25us / 0.125us ≈ 26 cycles +// #define OVERRIDE_CYCLES 2 // 0.2us / 0.125us ≈ 2 cycles +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 84 +// #define PULSE_COUNT 48 +// #define BIT_OFFSET_CYCLES 52 // 3.25 / 0.0625 ≈ 52 cycles +// #define OVERRIDE_CYCLES 3 // 0.2 / 0.0625 ≈ 3 cycles +// #endif +// #endif + +// // -------- SCPH 100 -------- +// #ifdef SCPH_100 +// #define BIOS_PATCH +// #define INTERRUPT_RISING + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 84 +// #define PULSE_COUNT 48 +// #define BIT_OFFSET_CYCLES 22 // 2.75 / 0.125 ≈ 22 cycles +// #define OVERRIDE_CYCLES 2 // 0.2 / 0.125 ≈ 2 cycles +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 84 +// #define PULSE_COUNT 48 +// #define BIT_OFFSET_CYCLES 44 // 2.75 / 0.0625 ≈ 44 cycles +// #define OVERRIDE_CYCLES 3 // 0.2 / 0.0625 ≈ 3 cycles +// #endif +// #endif + +// // -------- SCPH 7500 / 9000 -------- +// #ifdef SCPH_7500_9000 +// #define BIOS_PATCH +// #define INTERRUPT_RISING + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 16 +// #define BIT_OFFSET_CYCLES 22 // 2.8 / 0.125 ≈ 22 cycles +// #define OVERRIDE_CYCLES 2 // 0.2 / 0.125 ≈ 2 cycles +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 16 +// #define BIT_OFFSET_CYCLES 45 // 2.8 / 0.0625 ≈ 45 cycles +// #define OVERRIDE_CYCLES 3 // 0.2 / 0.0625 ≈ 3 cycles +// #endif +// #endif + +// // -------- SCPH 7000 -------- +// #ifdef SCPH_7000 +// #define BIOS_PATCH +// #define INTERRUPT_RISING + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 16 +// #define BIT_OFFSET_CYCLES 22 +// #define OVERRIDE_CYCLES 2 +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 16 +// #define BIT_OFFSET_CYCLES 45 +// #define OVERRIDE_CYCLES 3 +// #endif +// #endif + +// // -------- SCPH 5500 -------- +// #ifdef SCPH_5500 +// #define BIOS_PATCH +// #define INTERRUPT_FALLING + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 76 +// #define PULSE_COUNT 21 +// #define BIT_OFFSET_CYCLES 22 +// #define OVERRIDE_CYCLES 2 +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 76 +// #define PULSE_COUNT 21 +// #define BIT_OFFSET_CYCLES 45 +// #define OVERRIDE_CYCLES 3 +// #endif +// #endif + +// // -------- SCPH 5000 -------- +// #ifdef SCPH_5000 +// #define BIOS_PATCH +// #define INTERRUPT_FALLING + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 21 +// #define BIT_OFFSET_CYCLES 22 +// #define OVERRIDE_CYCLES 1 +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 21 +// #define BIT_OFFSET_CYCLES 45 +// #define OVERRIDE_CYCLES 2 +// #endif +// #endif + +// // -------- SCPH 3500 -------- +// #ifdef SCPH_3500 +// #define BIOS_PATCH +// #define INTERRUPT_FALLING + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 21 +// #define BIT_OFFSET_CYCLES 22 +// #define OVERRIDE_CYCLES 2 +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 75 +// #define PULSE_COUNT 21 +// #define BIT_OFFSET_CYCLES 44 +// #define OVERRIDE_CYCLES 3 +// #endif +// #endif + +// // -------- SCPH 3000 -------- +// #ifdef SCPH_3000 +// #define BIOS_PATCH +// #define INTERRUPT_RISING_HIGH_PATCH +// #define HIGH_PATCH + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 83 +// #define PULSE_COUNT 60 +// #define BIT_OFFSET_CYCLES 22 +// #define OVERRIDE_CYCLES 1 +// #define FOLLOWUP_OFFSET_MS 253 +// #define PULSE_COUNT_2 43 +// #define BIT_OFFSET_2_CYCLES 23 +// #define OVERRIDE_2_CYCLES 1 +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 83 +// #define PULSE_COUNT 60 +// #define BIT_OFFSET_CYCLES 43 +// #define OVERRIDE_CYCLES 2 +// #define FOLLOWUP_OFFSET_MS 253 +// #define PULSE_COUNT_2 43 +// #define BIT_OFFSET_2_CYCLES 46 +// #define OVERRIDE_2_CYCLES 2 +// #endif +// #endif + +// // -------- SCPH 1000 -------- +// #ifdef SCPH_1000 +// #define BIOS_PATCH +// #define INTERRUPT_RISING_HIGH_PATCH +// #define HIGH_PATCH + +// #ifdef F_CPU_8MHZ +// #define BOOT_OFFSET_MS 83 +// #define PULSE_COUNT 92 +// #define BIT_OFFSET_CYCLES 21 +// #define OVERRIDE_CYCLES 1 +// #define FOLLOWUP_OFFSET_MS 273 +// #define PULSE_COUNT_2 71 +// #define BIT_OFFSET_2_CYCLES 23 +// #define OVERRIDE_2_CYCLES 1 +// #elif defined(F_CPU_16MHZ) +// #define BOOT_OFFSET_MS 83 +// #define PULSE_COUNT 92 +// #define BIT_OFFSET_CYCLES 42 +// #define OVERRIDE_CYCLES 2 +// #define FOLLOWUP_OFFSET_MS 273 +// #define PULSE_COUNT_2 71 +// #define BIT_OFFSET_2_CYCLES 46 +// #define OVERRIDE_2_CYCLES 2 +// #endif +// #endif /*------------------------------------------------------------------------------------------------ Region Settings Section ------------------------------------------------------------------------------------------------*/