From 045a7ca53207c5b02418934a4f8db6cd4d6c184e Mon Sep 17 00:00:00 2001 From: kalymos Date: Wed, 18 Feb 2026 21:39:48 +0100 Subject: [PATCH] BIOS patch neo SCPH-5000 SCPH-3500 --- PSNee/BIOS_patching.h | 141 +++++++++++++----------------------------- PSNee/PSNee.ino | 4 +- PSNee/settings.h | 27 +++++--- 3 files changed, 65 insertions(+), 107 deletions(-) diff --git a/PSNee/BIOS_patching.h b/PSNee/BIOS_patching.h index fde3186..ff1914a 100644 --- a/PSNee/BIOS_patching.h +++ b/PSNee/BIOS_patching.h @@ -75,122 +75,64 @@ #endif + #ifdef HIGH_PATCH_A - #ifdef INTERRUPT_RISING - ISR(PIN_AX_INTERRUPT_VECTOR) { - /* - * PHASE 3: Pulse Counting (Inside ISR) - * The hardware Interrupt Service Routine (ISR) now takes over. - * It counts the exact number of incoming pulses on PIN_AX until it - * matches the PULSE_COUNT value. - */ + ISR(PIN_AY_INTERRUPT_VECTOR){ + pulse_counter++; - if (pulse_counter == PULSE_COUNT){ // If pulse_counter reaches the value defined by PULSE_COUNT - /* - * PHASE 4: Precision Bit Alignment - * Once the PULSE_COUNT is reached, a micro-delay (BIT_OFFSET) is applied. - * This shifts the timing from the clock edge to the exact bit position - * within the data stream that needs modification. - */ - _delay_us(BIT_OFFSET); - /* - * PHASE 5: Data Bus Overdrive (The Patch) - * Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit. - * This effectively overwrites the BIOS data on-the-fly - * before reverting the pin to INPUT to release the bus. - */ - PIN_DX_OUTPUT; - _delay_us (OVERRIDE); - PIN_DX_INPUT; - PIN_AX_INTERRUPT_DISABLE; - - pulse_counter = 0; - patch_done = 1; // patch_done is set to 1, indicating that the first patch is completed. - } - PIN_LED_ON; - PIN_LED_OFF; - } - - void Bios_Patching(){ - /* - * PHASE 1: Signal Stabilization & Alignment - * Detects the startup state (Cold Boot vs. Reset). - * If the line is already HIGH (Cold Boot), we wait for a full LOW-to-HIGH transition - * to ensure we are aligned with the start of a clean clock cycle. - */ - - if (PIN_AX_READ != 0) // Case: Power-on / Line high (---__-_-_) + if (pulse_counter == PULSE_COUNT_2) { - while (PIN_AX_READ != 0); // Wait for falling edge - while (PIN_AX_READ == 0); // Wait for next rising edge to sync - } - else // Case: Reset / Line low (_____-_-_) - { - while (PIN_AX_READ == 0); // Wait for the very first rising edge - } - - /* - * PHASE 2: Address Bus Window Alignment - * Introduces a BOOT_OFFSET delay to skip initial noise. - * This aligns the execution window with a - * known "idle gap" in the address bus activity, positioned - * immediately before the target memory-access cycle. - * - * BOOT_OFFSET: |---------//---------| - * AX LINE: -_-_-_-//-_-_-_-__________-_-_-_ - * BUS IDLE: |--------| - */ - _delay_ms(BOOT_OFFSET); - - // Armed for hardware detectio - EIFR |=(1 << INTF0); - PIN_AX_INTERRUPT_RISING; - PIN_AX_INTERRUPT_ENABLE; - - while (patch_done != 1); // Wait for the first stage of the patch to complete: + _delay_us (BIT_OFFSET_2); + PIN_DX_OUTPUT; + _delay_us (OVERRIDE_2); + PIN_DX_INPUT; + PIN_AY_INTERRUPT_DISABLE; - } - - #endif - - #ifdef INTERRUPT_FALLING - - ISR(PIN_AX_INTERRUPT_VECTOR) { - pulse_counter++; - if (pulse_counter == PULSE_COUNT){ - _delay_us (BIT_OFFSET); - PIN_DX_OUTPUT; - _delay_us (OVERRIDE); - PIN_DX_INPUT; - PIN_AX_INTERRUPT_DISABLE; - - pulse_counter = 0; - patch_done = 1; + patch_done = 2; } } void Bios_Patching(){ - - if (PIN_AX_READ != 0) + PIN_DX_INPUT; + cli(); // Disable interrupts for timing integrity + + if (PIN_AX_READ != 0) { while (PIN_AX_READ != 0); - while (PIN_AX_READ == 0); + while (PIN_AX_READ == 0); } else { while (PIN_AX_READ == 0); } - - _delay_ms(BOOT_OFFSET); / + - PIN_AX_INTERRUPT_FALLING; - PIN_AX_INTERRUPT_ENABLE; + _delay_ms(BOOT_OFFSET); + PIN_LED_ON; + _delay_us(BIT_OFFSET); + + PIN_DX_OUTPUT; // Force line (Low/High-Z override) + _delay_us(OVERRIDE); + PIN_DX_INPUT; // Release bus immediately + PIN_LED_OFF; + sei(); // Restore global interrupts + - while (patch_done != 1); + while (patch_done != 1); + PIN_LED_OFF; + while (PIN_AY_READ != 0); + + _delay_ms(FOLLOWUP_OFFSET); + + PIN_AY_INTERRUPT_RISING; + PIN_AY_INTERRUPT_ENABLE; + while (patch_done != 2); + } #endif + #ifdef INTERRUPT_RISING_HIGH_PATCH @@ -236,14 +178,17 @@ { while (PIN_AX_READ == 0); } - - _delay_ms(BOOT_OFFSET); + + _delay_ms(BOOT_OFFSET); + PIN_LED_ON; PIN_AX_INTERRUPT_RISING; PIN_AX_INTERRUPT_ENABLE; - while (patch_done != 1); + + while (patch_done != 1); + PIN_LED_OFF; while (PIN_AY_READ != 0); _delay_ms(FOLLOWUP_OFFSET); diff --git a/PSNee/PSNee.ino b/PSNee/PSNee.ino index d87faa7..63a4c8c 100644 --- a/PSNee/PSNee.ino +++ b/PSNee/PSNee.ino @@ -47,10 +47,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //#define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B //#define SCPH_7500_9000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 //#define SCPH_7000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 Enables hardware support for disabling BIOS patching. -#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C +//#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C //#define SCPH_5000 // DX - D0 | AX - A5 | AX - A4 | 2.2j - CRC 24FC7E17 //#define SCPH_3500 // DX - D0 | AX - A5 | AX - A4 | 2.1j - CRC BC190209 -//#define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6 +#define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6 //#define SCPH_1000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.0j - CRC 3B601FC8 /*------------------------------------------------------------------------------------------------ diff --git a/PSNee/settings.h b/PSNee/settings.h index 3303612..daec0ea 100644 --- a/PSNee/settings.h +++ b/PSNee/settings.h @@ -85,22 +85,35 @@ #ifdef SCPH_5000 #define BIOS_PATCH -#define INTERRUPT_FALLING +#define TEST_BIOS +#define LOW_TRIGGER #define BOOT_OFFSET 75.2 //75.12 - 75.27 -#define PULSE_COUNT 21 -#define BIT_OFFSET 2.8 //2.7 - 2.85 -#define OVERRIDE 0.1 +#define BIT_OFFSET 95.65 +#define OVERRIDE 0.2 #endif #ifdef SCPH_3500 #define BIOS_PATCH -#define INTERRUPT_FALLING +#define TEST_BIOS +#define LOW_TRIGGER #define BOOT_OFFSET 75.2 //75.12 - 75.27 -#define PULSE_COUNT 21 -#define BIT_OFFSET 2.75 //2.65 - 2.85 +#define BIT_OFFSET 95.4 #define OVERRIDE 0.2 #endif +// #ifdef SCPH_3000 +// #define BIOS_PATCH +// #define HIGH_PATCH_A +// #define BOOT_OFFSET 82.9 //82.65 - 83.26 +// #define BIT_OFFSET 278.65 +// #define OVERRIDE 0.15 +// #define HIGH_PATCH +// #define FOLLOWUP_OFFSET 253.3 +// #define PULSE_COUNT_2 43 +// #define BIT_OFFSET_2 2.88 +// #define OVERRIDE_2 0.15 +// #endif + #ifdef SCPH_3000 #define BIOS_PATCH #define INTERRUPT_RISING_HIGH_PATCH