diff --git a/PSNee/BIOS_patching.h b/PSNee/BIOS_patching.h index 9b7108b..fde3186 100644 --- a/PSNee/BIOS_patching.h +++ b/PSNee/BIOS_patching.h @@ -43,7 +43,11 @@ * Edge Triger: | * AX: _-_-_-_-_-________________-_-_-_-_-_-__ */ + #ifdef LOW_TRIGGER + while (PIN_AX_READ); + #else while (! PIN_AX_READ); + #endif /* * PHASE 4: Precision Bit Alignment diff --git a/PSNee/PSNee.ino b/PSNee/PSNee.ino index b394d96..d87faa7 100644 --- a/PSNee/PSNee.ino +++ b/PSNee/PSNee.ino @@ -43,11 +43,11 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX | Adres pin | SCPH model number // Data pin | 32-pin BIOS | 40-pin BIOS | BIOS version -------------------------------------------------------------------------------------------------*/ -#define SCPH_102 // DX - D0 | AX - A7 | | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5 +//#define SCPH_102 // DX - D0 | AX - A7 | | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5 //#define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B //#define SCPH_7500_9000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 //#define SCPH_7000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 Enables hardware support for disabling BIOS patching. -//#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C +#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C //#define SCPH_5000 // DX - D0 | AX - A5 | AX - A4 | 2.2j - CRC 24FC7E17 //#define SCPH_3500 // DX - D0 | AX - A5 | AX - A4 | 2.1j - CRC BC190209 //#define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6 diff --git a/PSNee/settings.h b/PSNee/settings.h index c21db59..3303612 100644 --- a/PSNee/settings.h +++ b/PSNee/settings.h @@ -60,29 +60,26 @@ #ifdef SCPH_7500_9000 #define BIOS_PATCH -#define INTERRUPT_RISING -#define BOOT_OFFSET 75.2 //74.95 - 75.55 -#define PULSE_COUNT 16 -#define BIT_OFFSET 2.8 +#define TEST_BIOS +#define BOOT_OFFSET 75.2 +#define BIT_OFFSET 71.5 #define OVERRIDE 0.2 #endif #ifdef SCPH_7000 -//#define PATCH_SWITCH #define BIOS_PATCH -#define INTERRUPT_RISING -#define BOOT_OFFSET 75.2 //75.3 -#define PULSE_COUNT 16 -#define BIT_OFFSET 2.8 +#define TEST_BIOS +#define BOOT_OFFSET 75.2 +#define BIT_OFFSET 71.5 #define OVERRIDE 0.2 #endif #ifdef SCPH_5500 #define BIOS_PATCH -#define INTERRUPT_FALLING +#define TEST_BIOS +#define LOW_TRIGGER #define BOOT_OFFSET 76.07 //75.99 - 76.14 -#define PULSE_COUNT 21 -#define BIT_OFFSET 2.8 +#define BIT_OFFSET 95.6 #define OVERRIDE 0.2 #endif