diff --git a/PSNee/MCU.h b/PSNee/MCU.h index 1b563ac..96e85a4 100644 --- a/PSNee/MCU.h +++ b/PSNee/MCU.h @@ -234,9 +234,9 @@ // --- BIOS Patching Configuration --- #if defined(SCPH_102) || \ defined(SCPH_100) || \ - defined(SCPH_7500_9000) || \ + defined(SCPH_7000_7500_9000) || \ defined(SCPH_7000) || \ - defined(SCPH_3500_5500) || \ + defined(SCPH_3500_5000_5500) || \ defined(SCPH_3000) || \ defined(SCPH_1000) @@ -274,7 +274,7 @@ #endif // Hardware Bypass Switch (On-the-fly deactivation) - #if defined(SCPH_7000) + #ifdef PATCH_SWITCHE #define PIN_SWITCH_INPUT DDRD &= ~(1 << DDD5) // Configure PIND5 as input for switch #define PIN_SWITCH_SET PORTD |= (1 << PD5) // Set PIND5 high (enable pull-up) #define PIN_SWITCH_READ (!!(PIND & (1 << PIND5))) // Read the state of PIND5 (switch input) @@ -295,47 +295,62 @@ #if defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U2__) #define IS_32U4_FAMILY - static inline void OptimizePeripherals(void) { - // 1. Global Interrupt Disable during hardware reconfiguration - cli(); + void OptimizePeripherals(void) __attribute__((naked, section(".init3"))); + + void OptimizePeripherals(void) { - // 2. Analog Front-End Shutdown - ADCSRA &= ~(1 << ADEN); // Disable ADC - ACSR |= (1 << ACD); // Disable Analog Comparator + // Ultra-Fast Boot (Clock & Watchdog) + CLKPR = 0x80; + CLKPR = 0x00; + MCUSR = 0; - // 3. Digital Input Buffer Disable (DIDR0 & DIDR2) - // 32U4 has more analog channels (ADC0-ADC7 and ADC8-ADC13) - DIDR0 = 0xFF; // Disable digital buffers on F0-F7 - //DIDR2 = 0x3F; // Disable digital buffers on D4, D6, D7, B4, B5, B6 + // Global Interrupt Disable during hardware reconfiguration + cli(); - // 4. GPIO Strategy (Unused pins to Pull-up) - // On 32U4, Port C is small (only PC6/PC7). Adjusting to cover most unused pins. - PORTC |= 0xFF; - PORTE |= 0xFF; // Extra port on 32U4 + // USB Hard-Shutdown (Kills USB Serial, use Hardware UART RX1/TX1 instead) + USBCON &= ~(1 << USBE); + USBCON &= ~(1 << OTGPADE); + UHWCON &= ~(1 << UVREGE); + PLLCSR &= ~(1 << PLLE); + UDINT = 0; - // 5. Power Reduction Registers (PRR0 & PRR1) - // PRR0 handles TWI, SPI, Timers 0, 1 and ADC. - PRR0 = (1 << PRTWI) | // I2C Off - (1 << PRSPI) | // SPI Off - (1 << PRTIM0) | // Timer 0 Off - (1 << PRTIM1) | // Timer 1 Off - (1 << PRADC); // ADC Clock Off - - // PRR1 handles Timer 3, Timer 4 and USB. - // We KEEP PRUSART1 (Serial1) and PRUSB active for communication. - PRR1 = (1 << PRUSB) | // Disable USB Controller (Stops SOF interrupts) - (1 << PRTIM3) | // Timer 3 Off - (1 << 4) | // Timer 4 Off (High speed timer) - (0 << PRUSART1); // KEEP SERIAL1 ACTIVE (PD1/TX1) - Must be 0 + // Analog Front-End Shutdown + ADCSRA &= ~(1 << ADEN); // Disable ADC + ACSR |= (1 << ACD); // Disable Analog Comparator - // 6. Double Security for Timer 0 (Redundancy) - TCCR0B = 0; - TIMSK0 = 0; - TCCR1B = 0; - TIMSK1 = 0; - TCCR3B = 0; - TIMSK3 = 0; - TCCR4B = 0; + // Digital Input Buffer Disable (DIDR0 & DIDR2) + // 32U4 has more analog channels (ADC0-ADC7 and ADC8-ADC13) + DIDR0 = 0xFF; // Disable digital buffers on F0-F7 + //DIDR2 = 0x3F; // Disable digital buffers on D4, D6, D7, B4, B5, B6 + + // GPIO Strategy (Unused pins to Pull-up) + // On 32U4, Port C is small (only PC6/PC7). Adjusting to cover most unused pins. + PORTC |= 0xFF; + PORTE |= 0xFF; // Extra port on 32U4 + + // Power Reduction Registers (PRR0 & PRR1) + // PRR0 handles TWI, SPI, Timers 0, 1 and ADC. + PRR0 = (1 << PRTWI) | // I2C Off + (1 << PRSPI) | // SPI Off + (1 << PRTIM0) | // Timer 0 Off + (1 << PRTIM1) | // Timer 1 Off + (1 << PRADC); // ADC Clock Off + + // PRR1 handles Timer 3, Timer 4 and USB. + // We KEEP PRUSART1 (Serial1) and PRUSB active for communication. + PRR1 = (1 << PRUSB) | // Disable USB Controller (Stops SOF interrupts) + (1 << PRTIM3) | // Timer 3 Off + // (1 << PRTIM4) | // Timer 4 Off (High speed timer) + (0 << PRUSART1); // KEEP SERIAL1 ACTIVE (PD1/TX1) - Must be 0 + + // Double Security for Timer 0 (Redundancy) + TCCR0B = 0; + TIMSK0 = 0; + TCCR1B = 0; + TIMSK1 = 0; + TCCR3B = 0; + TIMSK3 = 0; + TCCR4B = 0; } @@ -383,9 +398,8 @@ #if defined(SCPH_102) || \ defined(SCPH_100) || \ - defined(SCPH_7500_9000) || \ - defined(SCPH_7000) || \ - defined(SCPH_3500_5500) || \ + defined(SCPH_7000_7500_9000) || \ + defined(SCPH_3500_5000_5500) || \ defined(SCPH_3000) || \ defined(SCPH_1000) @@ -426,7 +440,7 @@ #endif // Hardware Bypass Switch (On-the-fly deactivation) - #ifdef SCPH_7000 + #ifdef PATCH_SWITCHE #define PIN_SWITCH_INPUT DDRC &= ~(1 << DDC6) // Bypass on PC6 #define PIN_SWITCH_SET PORTC |= (1 << PC6) // Enable pull-up #define PIN_SWITCH_READ (!!(PINC & (1 << PINC6))) @@ -439,35 +453,40 @@ #if defined(__AVR_ATtiny85__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny25__) #define IS_ATTINY_FAMILY - static inline void OptimizePeripherals(void) { - // 1. Global Interrupt Disable during reconfiguration - cli(); + void OptimizePeripherals(void) __attribute__((naked, section(".init3"))); - // 2. Analog Modules Shutdown - ADCSRA = 0; // Power off ADC completely - ACSR |= (1 << ACD); // Disable Analog Comparator + void OptimizePeripherals(void) { - // 3. Digital Input Buffer Disable (DIDR0) - // Disconnects digital buffers on PB0-PB5 to prevent leakage - DIDR0 = 0x00; + // Ultra-Fast Boot (Clock & Watchdog) + // Forced 8MHz is mandatory for stable SoftwareSerial baudrate + CLKPR = 0x80; + CLKPR = 0x00; + MCUSR = 0; - // 4. Power Reduction Register (PRR) - // Shuts down clocks to ADC and Timer 0. - // We KEEP USI or Timer 1 if required for specific logic. - PRR |= (1 << PRADC) | \ - (1 << PRTIM0)| \ - (1 << PRUSI); + //Global Interrupt Disable during reconfiguration + cli(); - // 5. Timer 0 Specific Shutdown (Hardware Redundancy) - TCCR0B = 0; - TCCR0B = 0; - //TIMSK &= ~((1 << OCIE0A) | (1 << OCIE0B) | (1 << TOIE0)); // Disable Timer 0 interrupts - TIMSK = 0; // Disable ALL timer interrupts (OCIE0A, OCIE0B, TOIE0, etc.) + // Analog Modules Shutdown + ADCSRA = 0; // Power off ADC completely + ACSR |= (1 << ACD); // Disable Analog Comparator - // 6. Watchdog: Ensure it's disabled to prevent random resets - MCUSR &= ~(1 << WDRF); - WDTCR |= (1 << WDCE) | (1 << WDE); - WDTCR = 0x00; + // Power Reduction Register (PRR) + // Shuts down clocks to ADC and Timer 0. + // We KEEP USI or Timer 1 if required for specific logic. + PRR |= (1 << PRADC) | + (0 << PRTIM0) | // KEEP TIMER 0 FOR SOFTWARE SERIAL + (1 << PRTIM1) | + (1 << PRUSI); + + // Timer 0 Specific Shutdown (Hardware Redundancy) + TCCR0B = 0; + TCCR0B = 0; + TIMSK = 0; // Disable ALL timer interrupts (OCIE0A, OCIE0B, TOIE0, etc.) + + // Watchdog: Ensure it's disabled to prevent random resets + MCUSR &= ~(1 << WDRF); + WDTCR |= (1 << WDCE) | (1 << WDE); + WDTCR = 0x00; } @@ -519,14 +538,12 @@ #endif // --- Safety Check: BIOS Patch Compatibility --- - #if defined(SCPH_1000) || \ - defined(SCPH_3000) || \ - defined(SCPH_3500_5000) || \ - defined(SCPH_5500) || \ - defined(SCPH_7000) || \ - defined(SCPH_7500_9000) || \ - defined(SCPH_100) || \ - defined(SCPH_102) + #if defined(SCPH_1000) || \ + defined(SCPH_3000) || \ + defined(SCPH_3500_5000_5500) || \ + defined(SCPH_7000_7500_9000) || \ + defined(SCPH_100) || \ + defined(SCPH_102) #error "ATtiny85/45/25 architecture is not compatible with the BIOS patch feature." #endif #endif diff --git a/PSNee/PSNee.ino b/PSNee/PSNee.ino index 5457210..6db3deb 100644 --- a/PSNee/PSNee.ino +++ b/PSNee/PSNee.ino @@ -27,16 +27,15 @@ * Note: BIOS version is more critical than the SCPH number for patch success. *------------------------------------------------------------------------------------------------------------------- * - * | Adres pin | - * SCPH model number // Data pin | 32-pin BIOS | 40-pin BIOS | BIOS version - *------------------------------------------------------------------------------------------------------------------*/ -// #define SCPH_102 // DX - D0 | AX - A7 | | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5 -// #define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B -// #define SCPH_7500_9000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 -// #define SCPH_7000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 Enables hardware support for disabling BIOS patching. -// #define SCPH_3500_5500 // DX - D0 | AX - A16 | AX - A15 | 3.0j - CRC FF3EEB8C, 2.2j - CRC 24FC7E17, 2.1j - CRC BC190209 -// #define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6 -// #define SCPH_1000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.0j - CRC 3B601FC8 + * // Data pin | Adres pin | + * SCPH model number // | 32-pin BIOS | 40-pin BIOS | BIOS version + *-------------------------------------------------------------------------------------------------------------------*/ +// #define SCPH_102 // DX - D0 | AX - A7 | | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5 +// #define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B +// #define SCPH_7000_7500_9000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 +// #define SCPH_3500_5000_5500 // DX - D0 | AX - A16 | AX - A15 | 3.0j - CRC FF3EEB8C, 2.2j - CRC 24FC7E17, 2.1j - CRC BC190209 +// #define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6 +// #define SCPH_1000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.0j - CRC 3B601FC8 /******************************************************************************************************************* * Options @@ -66,9 +65,16 @@ * - ATmega32U4 (Pro Micro): Connect LED between PB6 (Pin 10) and GND. */ -// #define DEBUG_SERIAL_MONITOR // Enables serial monitor output. +//#define PATCH_SWITCHE // This allows the user to disable the BIOS patch on-the-fly. +/* + * This allows you to bypass the memory card blocking problems on the SCPH-7000. + * - Configure Pin D5 as Input. + * - Enable internal Pull-up. + * - Exit immediately the patch BIOS if the switch pulls the pin to GND + */ -/****************************************************************************************************************** +// #define DEBUG_SERIAL_MONITOR // Enables serial monitor output. +/* * Requires compilation with Arduino libs! * For Arduino connect TXD and GND, for ATtiny PB3 (pin 2) and GND, to your serial card RXD and GND. * @@ -80,16 +86,16 @@ * Pin 2 (PB3) -----> RX (Serial Card) * Pin 4 (GND) -----> GND * - *******************************************************************************************************************/ + */ /****************************************************************************************************************** * Summary of practical information. Fuses. Pinout ******************************************************************************************************************* * Fuses - * MCU | High | Low | Extended + * MCU | High | Low | Extended * -------------------------------------------------- - * ATmega | DF | EE | FF - * ATtiny | DF | E2 | FF + * ATmega32U4 | DF | EE | D7 + * ATtiny | DF | E2 | FF * * Pinout * Arduino | PSNee | @@ -105,7 +111,7 @@ * D7 | SUBQ | * D8 | DATA | * D9 | WFCK | - * D13 ^ D10 | LED | D10 only for ATmega32U4_16U4 + * D13 ^ D10 | LED | D10 only for ATmega32U4 * * ATtiny | PSNee | ISP | * --------------------------------------------------- @@ -236,10 +242,10 @@ uint8_t request_counter = 0; void Bios_Patching(void) { - // --- HARDWARE BYPASS OPTION (SCPH-7000 specific) --- - #if defined(SCPH_7000) - PIN_SWITCH_INPUT; // Configure Pin D5 as Input - PIN_SWITCH_SET; // Enable internal Pull-up (D5 defaults to HIGH) + // --- HARDWARE BYPASS OPTION --- + #if defined(PATCH_SWITCHE) + PIN_SWITCH_INPUT; // Configure Pin D5 as Input + PIN_SWITCH_SET; // Enable internal Pull-up (D5 defaults to HIGH) __builtin_avr_delay_cycles(10); // Short delay for voltage stabilization /** diff --git a/PSNee/settings.h b/PSNee/settings.h index b53ef49..054cb8a 100644 --- a/PSNee/settings.h +++ b/PSNee/settings.h @@ -1,20 +1,9 @@ #pragma once /* - The _delay_us function uses loops to generate an approximate delay for the specified number of microseconds. - It calculates the number of clock cycles required to achieve the requested delay and loops the corresponding number of times. - - The temporal precision of _delay_us depends on the microcontroller's clock frequency (F_CPU). - For the ATmega328 operating at a typical frequency of 16 MHz, here are some details on the precision. - - Clock Frequency: F_CPU must be defined correctly before using the function. For an ATmega328 operating at 16 MHz: - 1 clock cycle = 1 / 16,000,000 s ≈ 62.5 ns - 1 µs ≈ 16 clock cycles - - BIT_OFFSET _delay_us(2.75) = 44 clock cycles - OVERRIDE _delay_us(0.2) = 3,2 clock cycles - -*/ + * + * + */ /*------------------------------------------------------------------------------------------------ Specific parameter section for BIOS patches @@ -31,41 +20,29 @@ #define BIOS_PATCH #define SILENCE_THRESHOLD 1100 #define CONFIRM_COUNTER_TARGET 8 - #define PULSE_COUNT 47 //47 - #define BIT_OFFSET_CYCLES 47 //60 + #define PULSE_COUNT 47 + #define BIT_OFFSET_CYCLES 47 #define OVERRIDE_CYCLES 3 #endif - // // -------- SCPH 7500 / 9000 -------- - #ifdef SCPH_7500_9000 + // // -------- SCPH 7000 / 7500 / 9000 -------- + #ifdef SCPH_7000_7500_9000 #define BIOS_PATCH #define SILENCE_THRESHOLD 1100 #define CONFIRM_COUNTER_TARGET 1 - #define PULSE_COUNT 15 //15 - #define BIT_OFFSET_CYCLES 47 //60 + #define PULSE_COUNT 15 + #define BIT_OFFSET_CYCLES 47 #define OVERRIDE_CYCLES 3 #endif - - // -------- SCPH 7000 -------- - #ifdef SCPH_7000 - #define BIOS_PATCH - #define SILENCE_THRESHOLD 1100 - #define CONFIRM_COUNTER_TARGET 1 - #define PULSE_COUNT 15 - #define BIT_OFFSET_CYCLES 47 - #define OVERRIDE_CYCLES 3 - #endif - - // // ----- SCPH 3500 / 5000 / 5500 ----- - #ifdef SCPH_3500_5500 + #ifdef SCPH_3500_5000_5500 #define BIOS_PATCH #define SILENCE_THRESHOLD 25000 #define CONFIRM_COUNTER_TARGET 1 - #define PULSE_COUNT 84 //84 - #define BIT_OFFSET_CYCLES 47 //60 + #define PULSE_COUNT 84 + #define BIT_OFFSET_CYCLES 47 #define OVERRIDE_CYCLES 3 #endif @@ -109,41 +86,29 @@ #define BIOS_PATCH #define SILENCE_THRESHOLD 1500 #define CONFIRM_COUNTER_TARGET 8 - #define PULSE_COUNT 47 //47 - #define BIT_OFFSET_CYCLES 47 //60 + #define PULSE_COUNT 47 + #define BIT_OFFSET_CYCLES 47 #define OVERRIDE_CYCLES 3 #endif - // // -------- SCPH 7500 / 9000 -------- - #ifdef SCPH_7500_9000 + // // -------- SCPH 7000 / 7500 / 9000 -------- + #ifdef SCPH_7000_7500_9000 #define BIOS_PATCH #define SILENCE_THRESHOLD 1500 #define CONFIRM_COUNTER_TARGET 1 - #define PULSE_COUNT 15 //15 - #define BIT_OFFSET_CYCLES 47 //60 + #define PULSE_COUNT 15 + #define BIT_OFFSET_CYCLES 47 #define OVERRIDE_CYCLES 3 #endif - - // -------- SCPH 7000 -------- - #ifdef SCPH_7000 - #define BIOS_PATCH - #define SILENCE_THRESHOLD 1500 - #define CONFIRM_COUNTER_TARGET 1 - #define PULSE_COUNT 15 - #define BIT_OFFSET_CYCLES 47 - #define OVERRIDE_CYCLES 3 - #endif - - // // ----- SCPH 3500 / 5000 / 5500 ----- - #ifdef SCPH_3500_5500 + #ifdef SCPH_3500_5000_5500 #define BIOS_PATCH #define SILENCE_THRESHOLD 32000 #define CONFIRM_COUNTER_TARGET 1 - #define PULSE_COUNT 84 //84 - #define BIT_OFFSET_CYCLES 47 //60 + #define PULSE_COUNT 84 + #define BIT_OFFSET_CYCLES 47 #define OVERRIDE_CYCLES 3 #endif @@ -183,14 +148,12 @@ Region Settings Section ------------------------------------------------------------------------------------------------*/ -#if defined(SCPH_100) || \ - defined(SCPH_7500_9000) || \ - defined(SCPH_7000) || \ - defined(SCPH_3500_5500) || \ - defined(SCPH_3500) || \ - defined(SCPH_3000) || \ - defined(SCPH_1000) || \ - defined(SCPH_xxx3) || \ +#if defined(SCPH_100) || \ + defined(SCPH_7000_7500_9000) || \ + defined(SCPH_3500_5000_5500) || \ + defined(SCPH_3000) || \ + defined(SCPH_1000) || \ + defined(SCPH_xxx3) || \ defined(SCPH_5903) #define INJECT_SCEx 0 // NTSC-J @@ -311,8 +274,8 @@ void InjectLog(){ // SECURITY CHECK: Ensure only one console is selected // If you get "not portable" warnings here, it's only because multiple models are active. -#if (defined(SCPH_1000) + defined(SCPH_3000) + defined(SCPH_3500_5500) + \ - defined(SCPH_7000) + defined(SCPH_7500_9000) + defined(SCPH_100) + \ +#if (defined(SCPH_1000) + defined(SCPH_3000) + defined(SCPH_3500_5000_5500) + \ + defined(SCPH_7000_7500_9000) + defined(SCPH_100) + \ defined(SCPH_102) + defined(SCPH_xxx1) + defined(SCPH_xxx2) + \ defined(SCPH_xxx3) + defined(SCPH_5903) + defined(SCPH_xxxx)) > 1 #error "Too many consoles selected! Please uncomment ONLY ONE model." @@ -323,11 +286,9 @@ void InjectLog(){ #pragma message "Target Console: SCPH-1000 (NTSC-J)" #elif defined(SCPH_3000) #pragma message "Target Console: SCPH-3000 (NTSC-J)" -#elif defined(SCPH_3500_5500) +#elif defined(SCPH_3500_5000_5500) #pragma message "Target Console: SCPH-3500/5000/5500 (NTSC-J)" -#elif defined(SCPH_7000) - #pragma message "Target Console: SCPH-7000 (Internal Switch enabled)" -#elif defined(SCPH_7500_9000) +#elif defined(SCPH_7000_7500_9000) #pragma message "Target Console: SCPH-7500/9000 (NTSC-J)" #elif defined(SCPH_100) #pragma message "Target Console: SCPH-100 (NTSC-J)" diff --git a/PSNeeCore-2.0.0/avr/boards.txt b/PSNeeCore-2.0.0/avr/boards.txt index d988e18..797d5c5 100644 --- a/PSNeeCore-2.0.0/avr/boards.txt +++ b/PSNeeCore-2.0.0/avr/boards.txt @@ -251,6 +251,8 @@ menu.variant=Variant #### ATtiny 85/45/25 #### ############################ + + # General X5.name=ATtiny 85/45/25 X5.upload.tool=avrdude @@ -259,11 +261,22 @@ X5.bootloader.unlock_bits=0xFF X5.bootloader.lock_bits=0xFF X5.build.core=tiny X5.build.board=AVR_ATtinyX5 -X5.build.extra_flags= +X5.build.extra_flags={build.clkpr} +X5.build.f_cpu=8000000UL +X5.build.clkpr= + +# Upload port select + X5.build.export_merged_output=false X5.bootloader.file=empty/empty.hex + +# EEPROM + X5.bootloader.high_fuses=0xDD X5.bootloader.extended_fuses=0xFF + +# Baud rate + X5.upload.speed={upload.default_speed} # Variants @@ -292,32 +305,65 @@ X5.compiler.cpp.extra_flags=-Wextra -flto -g X5.ltoarcmd=avr-gcc-ar # Clock frequencies -X5.menu.clock.internal_8m=8 MHz (internal) -X5.menu.clock.internal_8m.bootloader.low_fuses=0xE2 -X5.menu.clock.internal_8m.build.f_cpu=8000000UL -X5.menu.clock.internal_8m.upload.default_speed=38400 +X5.bootloader.low_fuses=0xE2 + +X5.upload.default_speed=38400 ############################ #### ATmega 32U4/32U2 #### ############################ -32U4.name=ATmega 32U4/32U2 +# General +32U4.name=ATmega 32U4 32U4.vid=0x2341 32U4.pid=0x8036 32U4.manufacturer=PSNee 32U4.product=ATmega32U4 +32U4.upload.tool=avrdude +32U4.upload.maximum_data_size=2048 +32U4.bootloader.tool=avrdude +32U4.bootloader.unlock_bits=0x3F +32U4.bootloader.lock_bits=0x2F 32U4.build.core=arduino 32U4.build.board=AVR_ATmega32U4 32U4.build.extra_flags=-DUSB_VID=0x2341 -DUSB_PID=0x8036 -DUSB_MANUFACTURER="PSNee" -DUSB_PRODUCT="ATmega32U4" -32U4.upload.tool=avrdude -32U4.upload.speed=57600 -32U4.bootloader.tool=avrdude +32U4.build.f_cpu=16000000UL +32U4.build.clkpr= + +32U4.build.core=arduino +32U4.build.board=AVR_ATmega32U4 + #32U4.bootloader.file=caterina/Caterina-Leonardo.hex -32U4.bootloader.unlock_bits=0x3F -32U4.bootloader.lock_bits=0x2F -32U4.bootloader.high_fuses=0xDF + + + 32U4.bootloader.extended_fuses=0xFE +32U4.bootloader.low_fuses=0xEE + +# Upload port select + +32U4.upload.default_speed=57600 +32U4.build.export_merged_output=false +32U4.bootloader.file=empty/empty.hex + +# EEPROM + +32U4.bootloader.high_fuses=0xDF + +# Baud rate + +32U4.upload.speed={upload.default_speed} + + +# Upload port select + +328.upload.maximum_size=32768 +328.upload.default_speed=115200 +328.build.export_merged_output=false +328.bootloader.file=empty/empty.hex + + 32U4.menu.variant.32U4=ATmega32U4 32U4.menu.variant.32U4.build.mcu=atmega32u4 @@ -325,25 +371,12 @@ X5.menu.clock.internal_8m.upload.default_speed=38400 32U4.menu.variant.32U4.upload.maximum_data_size=2560 32U4.menu.variant.32U4.build.variant=32u -32U4.menu.variant.32U2=ATmega32U2 -32U4.menu.variant.32U2.build.mcu=atmega32u2 -32U4.menu.variant.32U2.upload.maximum_size=28672 -32U4.menu.variant.32U2.upload.maximum_data_size=2560 -32U4.menu.variant.32U2.build.variant=32u # Compiler flags -32U4.compiler.c.extra_flags= -32U4.compiler.c.elf.extra_flags= -32U4.compiler.cpp.extra_flags= +32U4.compiler.c.extra_flags= -flto -g +32U4.compiler.c.elf.extra_flags= -flto -g +32U4.compiler.cpp.extra_flags= -flto -g 32U4.ltoarcmd=avr-gcc-ar -# Clock frequencies -32U4.menu.clock.external_16m=16 MHz (external) -32U4.menu.clock.external_16m.bootloader.low_fuses=0xEE -32U4.menu.clock.external_16m.build.f_cpu=16000000UL -32U4.menu.clock.external_16m.upload.default_speed=57600 -32U4.menu.clock.internal_8m=8 MHz (internal) -32U4.menu.clock.internal_8m.bootloader.low_fuses=0xE2 -32U4.menu.clock.internal_8m.build.f_cpu=8000000UL -32U4.menu.clock.internal_8m.upload.default_speed=38400 +