From 89dfc829ee3e6fd96e9869132ebbb4eb724b4e12 Mon Sep 17 00:00:00 2001 From: kalymos Date: Sun, 15 Feb 2026 20:52:21 +0100 Subject: [PATCH] test neo BIOS patch --- PSNee/BIOS_patching.h | 23 +++++++++++++++-------- PSNee/PSNee.ino | 8 ++++---- PSNee/settings.h | 30 +++++++++++++++--------------- 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/PSNee/BIOS_patching.h b/PSNee/BIOS_patching.h index 3c6dbc0..2ec6074 100644 --- a/PSNee/BIOS_patching.h +++ b/PSNee/BIOS_patching.h @@ -2,7 +2,7 @@ #pragma once #ifdef BIOS_PATCH - + uint8_t current_pulses = 0; volatile uint8_t pulse_counter = 0; volatile uint8_t patch_done = 0; @@ -10,7 +10,10 @@ void Bios_Patching() { PIN_DX_INPUT; - PIN_DX_LOW; + //PIN_DX_LOW; + + + cli(); // Disable interrupts for timing integrity /* * PHASE 1: Signal Stabilization & Alignment @@ -27,15 +30,14 @@ * PHASE 2: Address Bus Window Alignment * Bypassing initial boot routines to reach the target memory-access cycle. */ - _delay_ms(BOOT_OFFSET); + _delay_ms(BOOT_OFFSET); + PIN_LED_ON; /* * PHASE 3: Zero-Latency Software Pulse Counting * Using manual polling to eliminate the jitter (0.5us) caused by ISR overhead. * cli() locks the CPU for cycle-accurate timing. */ - uint8_t current_pulses = 0; - cli(); // Disable interrupts for timing integrity while (current_pulses < PULSE_COUNT) { // Wait for AX line to go HIGH (Target Rising Edge) @@ -46,7 +48,7 @@ if (current_pulses < PULSE_COUNT) { while (PIN_AX_READ != 0); } - // At the 48th pulse, we exit immediately to Phase 4 + // At the 47th pulse, we exit immediately to Phase 4 } /* @@ -63,8 +65,10 @@ PIN_DX_OUTPUT; // Force line (Low/High-Z override) _delay_us(OVERRIDE); PIN_DX_INPUT; // Release bus immediately - + PIN_LED_OFF; sei(); // Restore global interrupts + + patch_done = 1; } @@ -103,6 +107,8 @@ pulse_counter = 0; patch_done = 1; // patch_done is set to 1, indicating that the first patch is completed. } + PIN_LED_ON; + PIN_LED_OFF; } void Bios_Patching(){ @@ -136,7 +142,8 @@ */ _delay_ms(BOOT_OFFSET); - // Armed for hardware detection + // Armed for hardware detectio + EIFR |=(1 << INTF0); PIN_AX_INTERRUPT_RISING; PIN_AX_INTERRUPT_ENABLE; diff --git a/PSNee/PSNee.ino b/PSNee/PSNee.ino index c8c6add..6501ded 100644 --- a/PSNee/PSNee.ino +++ b/PSNee/PSNee.ino @@ -44,14 +44,14 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX SCPH model number // Data pin | 32-pin BIOS | 40-pin BIOS | BIOS version -------------------------------------------------------------------------------------------------*/ //#define SCPH_102 // DX - D0 | AX - A7 | | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5 -//#define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B +#define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B //#define SCPH_7500_9000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 //#define SCPH_7000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 Enables hardware support for disabling BIOS patching. //#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C //#define SCPH_5000 // DX - D0 | AX - A5 | AX - A4 | 2.2j - CRC 24FC7E17 //#define SCPH_3500 // DX - D0 | AX - A5 | AX - A4 | 2.1j - CRC BC190209 //#define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6 -#define SCPH_1000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.0j - CRC 3B601FC8 +//#define SCPH_1000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.0j - CRC 3B601FC8 /*------------------------------------------------------------------------------------------------ Options @@ -433,7 +433,7 @@ void Init() { #endif #ifdef LED_RUN - PIN_LED_ON; + //PIN_LED_ON; #endif if (Flag_Switch == 0) { @@ -441,7 +441,7 @@ void Init() { } #ifdef LED_RUN - PIN_LED_OFF; + //PIN_LED_OFF; #endif #endif diff --git a/PSNee/settings.h b/PSNee/settings.h index 0e1aa31..1b2c87c 100644 --- a/PSNee/settings.h +++ b/PSNee/settings.h @@ -33,25 +33,25 @@ #define OVERRIDE 0.2 #endif -#ifdef SCPH_100 -#define BIOS_PATCH -#define INTERRUPT_RISING -#define BOOT_OFFSET 83.9 //83.72 - 84.15 -#define PULSE_COUNT 48 -#define BIT_OFFSET 2.75 //2.63 - 2.87 -#define OVERRIDE 0.2 -#endif - - // #ifdef SCPH_100 // #define BIOS_PATCH -// #define TEST_BIOS -// #define BOOT_OFFSET 83.9 // Stabilization window (ms) -// #define PULSE_COUNT 48 // Targeted AX address cycles -// #define BIT_OFFSET 3.15 // Precision data alignment (us) -// #define OVERRIDE 0.2 // DX injection width (us) +// #define INTERRUPT_RISING +// #define BOOT_OFFSET 83.9 //83.72 - 84.15 +// #define PULSE_COUNT 47 +// #define BIT_OFFSET 2.75 //2.63 - 2.87 +// #define OVERRIDE 0.2 // #endif + +#ifdef SCPH_100 +#define BIOS_PATCH +#define TEST_BIOS +#define BOOT_OFFSET 83.9 // Stabilization window (ms) +#define PULSE_COUNT 47 // Targeted AX address cycles +#define BIT_OFFSET 3.6 // Precision data alignment (us) 3.9 - 3.98 +#define OVERRIDE 0.25 // DX injection width (us) +#endif + #ifdef SCPH_7500_9000 #define BIOS_PATCH #define INTERRUPT_RISING