diff --git a/PSNee/MCU.h b/PSNee/MCU.h
index 5531c01..1b563ac 100644
--- a/PSNee/MCU.h
+++ b/PSNee/MCU.h
@@ -113,13 +113,21 @@
   *    3. CLOCK GATING (PRR): Shuts down clocks to TWI, SPI, and all Timers (0, 1, 2).
   *    4. UART MAINTENANCE: Keeps PRUSART0 active to allow Serial communication.
   ------------------------------------------------------------------------------------------------*/
+  void OptimizePeripherals(void) __attribute__((naked, section(".init3")));
 
-  static inline void OptimizePeripherals(void) {
-    // 1. Disable Interrupts during setup
+  void OptimizePeripherals(void) {
+    
+    // Watchdog Timer Shutdown (Prevent Boot-Loop) 
+    MCUSR = 0;
+    WDTCSR |= (1 << WDCE) | (1 << WDE);
+    WDTCSR = 0x00;
+
+
+    // Disable Interrupts during setup
     cli();
 
-    // 2. Analog Modules Shutdown (Critical for Power)
-    ADCSRA &= ~(1 << ADEN); // Disable ADC
+    // Analog Modules Shutdown (Critical for Power)
+    ADCSRA = 0;             // Disable ADC
     ACSR   |= (1 << ACD);   // Disable Analog Comparator
 
     DIDR0 = 0xFF; // Pins A0 to A7
@@ -127,13 +135,13 @@
       DIDR2 = 0xFF;
     #endif
 
-    // 4. GPIO Strategy (Unused pins to Pull-up)
+    // GPIO Strategy (Unused pins to Pull-up)
     // PORTx = 0xFF (Pull-ups) | DDRx = 0x00 (Inputs)
     PORTC |= 0xFF;
     #if defined(__AVR_ATmega328PB__) || defined(__AVR_ATmega128PB__)
       PORTE |= 0x0F; // Le Port E existe sur la série PB (PE0 à PE3)
     #endif
-    // 5. Power Reduction Register (PRR)
+    // Power Reduction Register (PRR)
     // We KEEP PRUSART0 (UART) and shut down EVERYTHING else.
     // _delay_ms() will still work (it's cycle-based, not timer-based).
 
@@ -175,7 +183,7 @@
     #endif
 
 
-    // 6. Double Security for Timer 0
+    // Double Security for Timer 0
     TCCR0B = 0; TIMSK0 = 0; // Timer 0
     TCCR1B = 0; TIMSK1 = 0; // Timer 1
     TCCR2B = 0; TIMSK2 = 0; // Timer 2
diff --git a/PSNee/PSNee.ino b/PSNee/PSNee.ino
index 15ce8ab..cf8ac3d 100644
--- a/PSNee/PSNee.ino
+++ b/PSNee/PSNee.ino
@@ -32,7 +32,7 @@
  *------------------------------------------------------------------------------------------------------------------*/
 // #define SCPH_102        // DX - D0  | AX - A7          |                  | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5
 // #define SCPH_100        // DX - D0  | AX - A7          |                  | 4.3j - CRC F2AF798B
-// #define SCPH_7500_9000  // DX - D0  | AX - A7          |                  | 4.0j - CRC EC541CD0
+ #define SCPH_7500_9000  // DX - D0  | AX - A7          |                  | 4.0j - CRC EC541CD0
 // #define SCPH_7000       // DX - D0  | AX - A7          |                  | 4.0j - CRC EC541CD0  Enables hardware support for disabling BIOS patching.
 // #define SCPH_3500_5500  // DX - D0  | AX - A16         | AX - A15         | 3.0j - CRC FF3EEB8C, 2.2j - CRC 24FC7E17, 2.1j - CRC BC190209 
 // #define SCPH_3000       // DX - D5  | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6 
@@ -658,11 +658,6 @@ void PerformInjectionSequence(uint8_t injectSCEx) {
 
 void Init() {
 
-  // --- Hardware Power & Peripheral Optimization ---
-
-  OptimizePeripherals();
-
-
   #ifdef LED_RUN
     PIN_LED_OUTPUT;
   #endif
diff --git a/PSNeeCore-2.0.0/avr/boards.txt b/PSNeeCore-2.0.0/avr/boards.txt
index 21c0229..d988e18 100644
--- a/PSNeeCore-2.0.0/avr/boards.txt
+++ b/PSNeeCore-2.0.0/avr/boards.txt
@@ -8,7 +8,7 @@
 ###########################################################################################################
 
 # Menu options
-menu.clock=Clock
+
 menu.variant=Variant
 
 #############################
@@ -26,10 +26,13 @@ menu.variant=Variant
 328.build.board=AVR_ATmega328
 328.build.bootloader_led=led+b5
 328.build.extra_flags={build.clkpr}
+328.build.f_cpu=16000000L
+328.build.clkpr=
 
 # Upload port select
 
 328.upload.maximum_size=32768
+328.upload.default_speed=115200
 328.build.export_merged_output=false
 328.bootloader.file=empty/empty.hex
 
@@ -46,18 +49,24 @@ menu.variant=Variant
 328.menu.variant.modelP.bootloader.extended_value=11111101
 328.menu.variant.modelP.build.variant=standard
 328.menu.variant.modelP.build.mcu=atmega328p
+328.menu.variant.modelP.bootloader.low_fuses=0xDF
+
 
 328.menu.variant.modelNonP=328 / 328A
 # 328.menu.variant.modelNonP.bootloader.cksel_bits=0111
 328.menu.variant.modelNonP.bootloader.extended_value=11111101
 328.menu.variant.modelNonP.build.variant=standard
 328.menu.variant.modelNonP.build.mcu=atmega328
+328.menu.variant.modelNonP.bootloader.low_fuses=0xDF
 
 328.menu.variant.modelPB=328PB
 # 328.menu.variant.modelPB.bootloader.cksel_bits=1111
-328.menu.variant.modelPB.bootloader.extended_value=11110111
+328.menu.variant.modelPB.bootloader.extended_value=11110101
 328.menu.variant.modelPB.build.variant=pb-variant
 328.menu.variant.modelPB.build.mcu=atmega328pb
+328.menu.variant.modelPB.bootloader.low_fuses=0xDF
+
+
 
 # Brown out detection
 
@@ -71,28 +80,6 @@ menu.variant=Variant
 328.ltoarcmd=avr-gcc-ar
 
 
-# Clock frequencies
-328.menu.clock.16MHz_external=External 16 MHz
-328.menu.clock.16MHz_external.upload.default_speed=115200
-# 328.menu.clock.16MHz_external.bootloader.low_fuses=0b1111{bootloader.cksel_bits}
-328.menu.clock.16MHz_external.bootloader.low_fuses=0xEE
-328.menu.clock.16MHz_external.build.clkpr=
-328.menu.clock.16MHz_external.build.f_cpu=16000000L
-
-
-328.menu.clock.8MHz_external=External 8 MHz
-328.menu.clock.8MHz_external.upload.default_speed=57600
-# 328.menu.clock.8MHz_external.bootloader.low_fuses=0b1111{bootloader.cksel_bits}
-328.menu.clock.8MHz_external.bootloader.low_fuses=0xEE
-328.menu.clock.8MHz_external.build.clkpr=
-328.menu.clock.8MHz_external.build.f_cpu=8000000L
-
-
-328.menu.clock.8MHz_internal=Internal 8 MHz
-328.menu.clock.8MHz_internal.upload.default_speed=38400
-328.menu.clock.8MHz_internal.bootloader.low_fuses=0xC2
-328.menu.clock.8MHz_internal.build.clkpr=
-328.menu.clock.8MHz_internal.build.f_cpu=8000000L
 
 #############################
 #### ATmega168/A/P/PA/PB ####