diff --git a/PSNee modchip installation guide.pdf b/PSNee modchip installation guide.pdf
index 2e3cbb4..6894449 100644
Binary files a/PSNee modchip installation guide.pdf and b/PSNee modchip installation guide.pdf differ
diff --git a/PSNee_V8.5/PSNee_V8.5/BIOS_patching.h b/PSNee_V8.6/PSNee_V8.6/BIOS_patching.h
similarity index 100%
rename from PSNee_V8.5/PSNee_V8.5/BIOS_patching.h
rename to PSNee_V8.6/PSNee_V8.6/BIOS_patching.h
diff --git a/PSNee_V8.5/PSNee_V8.5/MUC.h b/PSNee_V8.6/PSNee_V8.6/MUC.h
similarity index 66%
rename from PSNee_V8.5/PSNee_V8.5/MUC.h
rename to PSNee_V8.6/PSNee_V8.6/MUC.h
index 1d6b47b..baab000 100644
--- a/PSNee_V8.5/PSNee_V8.5/MUC.h
+++ b/PSNee_V8.6/PSNee_V8.6/MUC.h
@@ -1,18 +1,117 @@
-//Configuring the clock speed and associated registers.  F_CPU / (TCCR0B |= (1<<CS00) *(OCR0A = 159 +1) = 16000000 /(0 * (160)) = 100KHz
+// *****************************************************************************************************************
+// Configuration for different microcontrollers (MUC) to ensure compatibility with the code:
+// - Defines the clock speed, timers, and interrupts for each MUC.
+// - Configures I/O pins for data, clocks, and switches according to the requirements.
+// - Enables pull-up resistors on input pins where needed.
+// - Manages external interrupts and LED outputs for system feedback.
+// - Ensures the setup is compatible with various microcontroller models (e.g., ATmega328, ATtiny series, etc.)
+// *****************************************************************************************************************
+
+//******************************************************************************************************************
+// Configuring the clock speed and associated registers. The formula for calculating 
+// the clock frequency is F_CPU / (TCCR0B |= (1<<CS00)) * (OCR0A = 159 +1) = 16000000 / (0 * (160)) = 100KHz
+//******************************************************************************************************************
+
+//******************************************************************************************************************
+// Example: DDRB &= ~(1<<DDB0);  // Create a mask by shifting the bit 1 to the left by DDB0's position (bit 0), and then inverting it.
+// The bitwise AND operation (&=) updates the register DDRB by clearing the DDB0 bit (setting it to 0) 
+// without affecting the other bits. 
+//
+// For instance, if DDRB = b11111111 (binary value), the operation shifts the bit 1 to the left to create the mask 
+// (1<<DDB0) = b00000001, and then inverts it, which results in b11111110. The AND operation with DDRB clears DDB0.
+// 
+// Before:  DDRB = b11111111  // Initial value of DDRB (all pins set as output)
+// Mask:    ~(b00000001) = b11111110  // Mask generated by shifting and inverting the bit
+// After:   DDRB = b11111110  // The DDB0 bit is cleared (set to 0), while other bits remain unchanged
+//******************************************************************************************************************
+
+//******************************************************************************************************************
+// Example: DDRB |= (1<<DDB0);  // Create a mask by shifting the bit 1 to the left by DDB0's position (bit 0), 
+// and then apply a bitwise OR operation to set DDB0 to 1 (configure pin PB0 as an output).
+//
+// For instance, if DDRB = b11111111 (binary value), the operation shifts the bit 1 to the left to create the mask 
+// (1<<DDB0) = b00000001. The OR operation with DDRB sets the DDB0 bit to 1, leaving other bits unchanged.
+// 
+// Before:  DDRB = b11111111  // Initial value of DDRB (all pins set as output)
+// Mask:    (1<<DDB0) = b00000001  // Mask generated by shifting the bit 1 to the left to position DDB0
+// After:   DDRB = b11111111  // The DDB0 bit is set to 1, configuring pin PB0 as an output
+//******************************************************************************************************************
+
+//******************************************************************************************************************
+// Example: (PIND & (1<<PIND6));  // Create a mask by shifting the bit 1 to the left by PIND6's position (bit 6), 
+// and then apply a bitwise AND operation to read the state of the PIND6 pin. 
+// The result will be non-zero (true) if the PIND6 pin is high (1), and zero (false) if the PIND6 pin is low (0).
+//
+// For instance, if PIND = b10101010 (binary value), the operation shifts the bit 1 to the left to create the mask 
+// (1<<PIND6) = b01000000. The AND operation between PIND and the mask checks if the 6th bit is set to 1 (high).
+// 
+// Before:  PIND = b10101010  // Initial value of PIND (register containing input pin states)
+// Mask:    (1<<PIND6) = b01000000  // Mask generated by shifting the bit 1 to the left to position PIND6
+// Operation: PIND & b01000000 = b00000000 // If PIND6 is low (0)
+// Operation: PIND & b01000000 = b01000000 // If PIND6 is high (1)
+// 
+//******************************************************************************************************************
+
+//******************************************************************************************************************
+// Example: EICRA |= (1<<ISC01) | (1<<ISC00);  
+// This operation configures the external interrupt sense control (ISC) for interrupt INT0 (External Interrupt Request 0).
+// Specifically, it sets the mode of INT0 to "rising edge" trigger, meaning the interrupt will be triggered when the pin 
+// transitions from low to high (rising edge).
+//
+// EICRA (External Interrupt Control Register A) controls how external interrupts INT0 and INT1 are triggered. 
+// The bits ISC01 and ISC00 in this register define the trigger mode for interrupt INT0.
+// 
+// - Setting ISC01 to 1 and ISC00 to 1 (via the OR operation) configures INT0 to trigger on the rising edge.
+// 
+// Before:  EICRA = b00000000  // Initial value of EICRA, all interrupt sense control bits are cleared (no trigger mode set).
+// Operation: EICRA |= (1<<ISC01) | (1<<ISC00)  // Set ISC01 and ISC00 to 1 for rising edge trigger.
+// After:   EICRA = b00000011  // The bits ISC01 and ISC00 are now set, configuring INT0 to trigger on rising edge.
+// 
+// This technique is commonly used to configure external interrupts to trigger based on specific events like a rising 
+// or falling edge on the external interrupt pin (INT0 or INT1).
+//******************************************************************************************************************
+
+//******************************************************************************************************************
+// Example: EICRA = (EICRA & ~(1<<ISC00)) | (1<<ISC01);  
+// This operation configures the external interrupt sense control (ISC) for interrupt INT0 (External Interrupt Request 0). 
+// Specifically, it sets INT0 to trigger on a "falling edge" (when the signal transitions from high to low).
+// 
+// The bits ISC01 and ISC00 in the EICRA register define how the external interrupt INT0 is triggered. The operation 
+// clears the bit ISC00 while setting ISC01 to 1, configuring INT0 to trigger when the pin transitions from high to low, 
+// i.e., on the falling edge.
+// 
+// EICRA (External Interrupt Control Register A) controls how external interrupts INT0 and INT1 are triggered.
+// - ISC01 = 1, ISC00 = 0 configures INT0 to trigger on falling edge (high to low transition).
+// 
+// Before:  EICRA = b00000011  // Initial value with ISC01 = 1 and ISC00 = 1 (rising edge trigger for INT0)
+// Operation: EICRA & ~(1<<ISC00) clears ISC00 bit (sets it to 0) while keeping ISC01 at 1. Then OR operation with (1<<ISC01) ensures ISC01 stays 1.
+// After:   EICRA = b00000010  // The bit ISC00 is now cleared, configuring INT0 to trigger on the falling edge.
+// 
+// This technique is used to configure the interrupt to trigger on the falling edge (transition from high to low),
+// without changing the state of other control bits in the EICRA register.
+//******************************************************************************************************************
 
 #pragma once
 
 #ifdef ATmega328_168
 
+
+// Define the clock speed for the microcontroller
 #define F_CPU 16000000L
-#define TIMER_TCNT_CLEAR            TCNT0   =   0x00             //TCNT0 - Timer/Counter Register
-#define SET_OCROA_DIV               OCR0A   =   159;             //OCR0A – Output Compare Register A, 0x10011111, 100KHz
-#define SET_TIMER_TCCROA            TCCR0A |=  (1 << WGM01);     //TCCR0A – Timer/Counter Control Register A. turn on CTC mode, WGM01
-#define SET_TIMER_TCCROB            TCCR0B |=  (1 << CS00);      //TCCR0B – Timer/Counter Control Register B,  CS00: Clock Select,  clk I/O
+
+// Clear the timer count register (TCNT0)
+#define TIMER_TCNT_CLEAR            TCNT0   =   0x00             // TCNT0 - Timer/Counter Register, clears the timer count
+
+// Set OCR0A to achieve a 100KHz clock frequency
+#define SET_OCROA_DIV               OCR0A   =   159;             // OCR0A – Output Compare Register A, 100KHz clock generation, 0x10011111
+
+// Configure Timer/Counter 0 for CTC mode and enable the clock source
+#define SET_TIMER_TCCROA            TCCR0A |=  (1 << WGM01);     // TCCR0A – Timer/Counter Control Register A, enable CTC mode (WGM01)
+#define SET_TIMER_TCCROB            TCCR0B |=  (1 << CS00);      // TCCR0B – Timer/Counter Control Register B, set clock source to I/O clock
                                                                  //Waveform Generation Mode, Mode 2 CTC
+// Interrupt vector for timer compare match event                                                      
 #define CTC_TIMER_VECTOR            TIMER0_COMPA_vect            //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
 
-
 #include <stdint.h>
 #include <stdbool.h>
 #include <avr/io.h>
@@ -20,187 +119,91 @@
 #include <avr/sfr_defs.h>
 #include <util/delay.h>
 
-// Globale interrupt seting
-#define GLOBAL_INTERRUPT_ENABLE     SREG   |=  (1<<7)           
-#define GLOBAL_INTERRUPT_DISABLE    SREG   &= ~(1<<7)    
+// Global interrupt control settings
+#define GLOBAL_INTERRUPT_ENABLE     SREG   |=  (1<<7)           // Set the I-bit (bit 7) in the Status Register to enable global interrupts
+#define GLOBAL_INTERRUPT_DISABLE    SREG   &= ~(1<<7)           // Clear the I-bit (bit 7) in the Status Register to disable global interrupts
 
-// Handling the main pins
+// Main pin configuration for input and output
 
-// Main pins input
-#define PIN_DATA_INPUT              DDRB   &= ~(1<<DDB0)        
-#define PIN_WFCK_INPUT              DDRB   &= ~(1<<DDB1)       // Create a mask (1<<0) with the first bit at 1 b00000001 uses the ~ operator to perform a bit inversion b11111110,
-#define PIN_SQCK_INPUT              DDRD   &= ~(1<<DDD6)       // &= updates the DDRB register with the AND operator and the mask, DDRB bxxxxxxxx OR mask b11111110 = bxxxxxxx0                     
-#define PIN_SUBQ_INPUT              DDRD   &= ~(1<<DDD7) 
+// Define the main pins as inputs
+#define PIN_DATA_INPUT              DDRB   &= ~(1<<DDB0)       // Set DDRB register to configure PINB0 as input 
+#define PIN_WFCK_INPUT              DDRB   &= ~(1<<DDB1)       // Set DDRB register to configure PINB1 as input
+#define PIN_SQCK_INPUT              DDRD   &= ~(1<<DDD6)       // Set DDRB register to configure PINB6 as input                   
+#define PIN_SUBQ_INPUT              DDRD   &= ~(1<<DDD7)       // Set DDRB register to configure PINB7 as input
                             
-// Main pin output
-#define PIN_DATA_OUTPUT             DDRB   |=  (1<<DDB0)       // Create a mask (1<<0) with the first bit at 1 b00000001,     
-#define PIN_WFCK_OUTPUT             DDRB   |=  (1<<DDB1)       // |= updates the DDRB register with the OR operator and the mask, DDRB bxxxxxxxx OR mask b00000001 = bxxxxxxx1
+// Enable pull-ups and set high on the main pins
+#define PIN_DATA_OUTPUT             DDRB   |=  (1<<DDB0)       // Set DDRB register to configure PINB0 as output 
+#define PIN_WFCK_OUTPUT             DDRB   |=  (1<<DDB1)       // Set DDRB register to configure PINB1 as output
            
 // Define pull-ups and set high at the main pin
-#define PIN_DATA_SET                PORTB  |=  (1<<PB0)        // Create a mask (1<<0) with the first bit at 1 b00000001,
-                                                               // |= updates the PORTB register with the OR operator and the mask, PORTB bxxxxxxxx OR mask b00000001 = bxxxxxxx1
+#define PIN_DATA_SET                PORTB  |=  (1<<PB0)        // Set PORTB register to make PINB0 high (enable pull-up)
              
-// Define pull-ups set down at the main pin
-#define PIN_DATA_CLEAR              PORTB  &= ~(1<<PB0)        // Create a mask (1<<0) with the first bit at 1 b00000001 uses the ~ operator to perform a bit inversion b11111110,                    
-#define PIN_WFCK_CLEAR              PORTB  &= ~(1<<PB1)        // &= updates the DDRB register with the AND operator and the mask, DDRB bxxxxxxxx OR mask b11111110 = bxxxxxxx0
+// Clear the main pins (set low)
+#define PIN_DATA_CLEAR              PORTB  &= ~(1<<PB0)        // Set PORTB register to make PINB0 low                  
+#define PIN_WFCK_CLEAR              PORTB  &= ~(1<<PB1)        // Set PORTB register to make PINB1 low
                          
-// Read the main pins
-#define PIN_SQCK_READ              (PIND   &   (1<<PIND6))     // Create a mask (1<<6) with the six bit at 1 b00100000,                       
-#define PIN_SUBQ_READ              (PIND   &   (1<<PIND7))     // compare the PINB register and the mask with the AND operator, and returns the result, PINB bxx1xxxxx AND mask b00100000 = 1                      
-#define PIN_WFCK_READ              (PINB   &   (1<<PINB1))                                                       
+// Read the state of the main input pins
+#define PIN_SQCK_READ              (PIND   &   (1<<PIND6))     // Check if the value of PIND6 is high (1)                      
+#define PIN_SUBQ_READ              (PIND   &   (1<<PIND7))     // Check if the value of PIND7 is high (1)                      
+#define PIN_WFCK_READ              (PINB   &   (1<<PINB1))     // Check if the value of PIND1 is high (1)        
 
-// Handling and use of the LED pin
+// LED pin handling (for indication)
 #define LED_RUN
-#define PIN_LED_OUTPUT              DDRB   |=  (1<<DDB5)                                
-#define PIN_LED_ON                  PORTB  |=  (1<<PB5)      
-#define PIN_LED_OFF                 PORTB  &= ~(1<<PB5)   
+#define PIN_LED_OUTPUT              DDRB   |=  (1<<DDB5)       // Configure PINB5 as output (for LED)                
+#define PIN_LED_ON                  PORTB  |=  (1<<PB5)        // Set PINB5 high (turn on LED)
+#define PIN_LED_OFF                 PORTB  &= ~(1<<PB5)        // Set PINB5 low (turn off LED)
 
 // Handling the BIOS patch
 
-// BIOS interrupt seting
-#define TIMER_INTERRUPT_ENABLE      TIMSK0 |=  (1<<OCIE0A)
-#define TIMER_INTERRUPT_DISABLE     TIMSK0 &= ~(1<<OCIE0A)
+// Enable/Disable timer interrupts
+#define TIMER_INTERRUPT_ENABLE      TIMSK0 |=  (1<<OCIE0A)     // Enable interrupt on Timer0 Compare Match A
+#define TIMER_INTERRUPT_DISABLE     TIMSK0 &= ~(1<<OCIE0A)     // Disable interrupt on Timer0 Compare Match A
 
-// BIOS timer clear
-#define TIMER_TIFR_CLEAR            TIFR0  |=  (1<<OCF0A)
+// Clear the timer interrupt flag
+#define TIMER_TIFR_CLEAR            TIFR0  |=  (1<<OCF0A)      // Clear the Timer0 Compare Match A interrupt flag
 
-// Pins input
-#define PIN_AX_INPUT                DDRD   &= ~(1<<DDD2)                            
-#define PIN_AY_INPUT                DDRD   &= ~(1<<DDD3)                             
-#define PIN_DX_INPUT                DDRD   &= ~(1<<DDD4)                             
-// Pin output
-#define PIN_DX_OUTPUT               DDRD   |=  (1<<DDD4)                             
-// Define pull-ups set high 
-#define PIN_DX_SET                  PORTD  |=  (1<<PD4)                              
-// Define pull-ups set down 
-#define PIN_DX_CLEAR                PORTD  &= ~(1<<PD4)                            
-// Read pins for BIOS patch
-#define PIN_AX_READ                (PIND   &   (1<<PIND2))                             
-#define PIN_AY_READ                (PIND   &   (1<<PIND3))                             
+// Define input pins for the BIOS patch
+#define PIN_AX_INPUT                DDRD   &= ~(1<<DDD2)       // Set DDRD register to configure PIND2 as input
+#define PIN_AY_INPUT                DDRD   &= ~(1<<DDD3)       // Set DDRD register to configure PIND3 as input
+#define PIN_DX_INPUT                DDRD   &= ~(1<<DDD4)       // Set DDRD register to configure PIND4 as input
 
-// Handling the external interrupt
-#define PIN_AX_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT0)
-#define PIN_AY_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT1)
+// Define output pins for the BIOS patch
+#define PIN_DX_OUTPUT               DDRD   |=  (1<<DDD4)       // Set DDRD register to configure PIND4 as output
 
-#define PIN_AX_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT0)
-#define PIN_AY_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT1)
+// Set pull-ups high on output pins
+#define PIN_DX_SET                  PORTD  |=  (1<<PD4)       // Set PORTD register to make PIND4 high
 
-#define PIN_AX_INTERRUPT_RISING     EICRA  |=  (1<<ISC01)|(1<<ISC00)
-#define PIN_AY_INTERRUPT_RISING     EICRA  |=  (1<<ISC11)|(1<<ISC10)
+// Set pull-ups low on output pins
+#define PIN_DX_CLEAR                PORTD  &= ~(1<<PD4)       // Set PORTD register to make PIND4 low
 
-#define PIN_AX_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC00)) | (1<<ISC01))
-#define PIN_AY_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC10)) | (1<<ISC11))
+// Read the input pins for the BIOS patch
+#define PIN_AX_READ                (PIND   &   (1<<PIND2))    // Read the state of PIND2                     
+#define PIN_AY_READ                (PIND   &   (1<<PIND3))    // Read the state of PIND3                       
 
-#define PIN_AX_INTERRUPT_VECTOR        INT0_vect              
-#define PIN_AY_INTERRUPT_VECTOR        INT1_vect    
+// External interrupt configuration for BIOS patch
+#define PIN_AX_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT0)      // Enable external interrupt on INT0 (PINB2)
+#define PIN_AY_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT1)      // Enable external interrupt on INT1 (PINB3)
 
-// Handling and reading the switch pin for patch BIOS
-#define PIN_SWITCH_INPUT            DDRD   &= ~(1<<DDD5)                              
-#define PIN_SWITCH_SET              PORTD  |=  (1<<PD5)                                
-#define PIN_SWICHE_READ            (PIND   &   (1<<PIND5))
+#define PIN_AX_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT0)      // Disable external interrupt on INT0
+#define PIN_AY_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT1)      // Disable external interrupt on INT1
+
+#define PIN_AX_INTERRUPT_RISING     EICRA  |=  (1<<ISC01)|(1<<ISC00)                  // Configure INT0 for rising edge trigger
+#define PIN_AY_INTERRUPT_RISING     EICRA  |=  (1<<ISC11)|(1<<ISC10)                  // Configure INT1 for rising edge trigger
+
+#define PIN_AX_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC00)) | (1<<ISC01))    // Configure INT0 for falling edge trigger
+#define PIN_AY_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC10)) | (1<<ISC11))    // Configure INT1 for falling edge trigger
+
+// Interrupt vectors for external interrupts
+#define PIN_AX_INTERRUPT_VECTOR        INT0_vect              // Interrupt vector for INT0 (external interrupt)
+#define PIN_AY_INTERRUPT_VECTOR        INT1_vect              // Interrupt vector for INT1 (external interrupt)
+
+// Handle switch input for BIOS patch
+#define PIN_SWITCH_INPUT            DDRD   &= ~(1<<DDD5)      // Configure PIND5 as input for switch                      
+#define PIN_SWITCH_SET              PORTD  |=  (1<<PD5)       // Set PIND5 high (enable pull-up)            
+#define PIN_SWICHE_READ            (PIND   &   (1<<PIND5))    // Read the state of PIND5 (switch input)
 
 #endif
 
-#ifdef LGT8F328P
-
-#define F_CPU 32000000L
-#define TIMER_TCNT_CLEAR            TCNT0   =   0x00             
-#define SET_OCROA_DIV               OCR0A   =   319;             
-#define SET_TIMER_TCCROA            TCCR0A |=  (1 << WGM01);     
-#define SET_TIMER_TCCROB            TCCR0B |=  (1 << CS00); 
-#define CTC_TIMER_VECTOR            TIMER0_COMPA_vect            //??
-
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <avr/io.h>
-#include <avr/interrupt.h>
-#include <avr/sfr_defs.h>
-#include <util/delay.h>
-
-// Globale interrupt seting
-#define GLOBAL_INTERRUPT_ENABLE     SREG   |=  (1<<7)           
-#define GLOBAL_INTERRUPT_DISABLE    SREG   &= ~(1<<7)    
-
-// Handling the main pins
-
-// Main pins input
-#define PIN_DATA_INPUT              DDRB   &= ~(1<<DDB0)        
-#define PIN_WFCK_INPUT              DDRB   &= ~(1<<DDB1)       
-#define PIN_SQCK_INPUT              DDRD   &= ~(1<<DDD6)      
-#define PIN_SUBQ_INPUT              DDRD   &= ~(1<<DDD7) 
-                            
-// Main pin output
-#define PIN_DATA_OUTPUT             DDRB   |=  (1<<DDB0)       
-#define PIN_WFCK_OUTPUT             DDRB   |=  (1<<DDB1)       
-           
-// Define pull-ups and set high at the main pin
-#define PIN_DATA_SET                PORTB  |=  (1<<PB0)        
-                                                              
-             
-// Define pull-ups set down at the main pin
-#define PIN_DATA_CLEAR              PORTB  &= ~(1<<PB0)        
-#define PIN_WFCK_CLEAR              PORTB  &= ~(1<<PB1)        
-                         
-// Read the main pins
-#define PIN_SQCK_READ              (PIND   &   (1<<PIND6))         
-#define PIN_SUBQ_READ              (PIND   &   (1<<PIND7))     
-#define PIN_WFCK_READ              (PINB   &   (1<<PINB1))                                                       
-
-// Handling and use of the LED pin
-#define LED_RUN
-#define PIN_LED_OUTPUT              DDRB   |=  (1<<DDB5)                                
-#define PIN_LED_ON                  PORTB  |=  (1<<PB5)      
-#define PIN_LED_OFF                 PORTB  &= ~(1<<PB5)   
-
-// Handling the BIOS patch
-
-// BIOS interrupt seting
-#define TIMER_INTERRUPT_ENABLE      TIMSK0 |=  (1<<OCIE0A)
-#define TIMER_INTERRUPT_DISABLE     TIMSK0 &= ~(1<<OCIE0A)
-
-// BIOS timer clear
-#define TIMER_TIFR_CLEAR            TIFR0  |=  (1<<OCF0A)
-
-// Pins input
-#define PIN_AX_INPUT                DDRD   &= ~(1<<DDD2)                            
-#define PIN_AY_INPUT                DDRD   &= ~(1<<DDD3)                             
-#define PIN_DX_INPUT                DDRD   &= ~(1<<DDD4)                             
-// Pin output
-#define PIN_DX_OUTPUT               DDRD   |=  (1<<DDD4)                             
-// Define pull-ups set high 
-#define PIN_DX_SET                  PORTD  |=  (1<<PD4)                              
-// Define pull-ups set down 
-#define PIN_DX_CLEAR                PORTD  &= ~(1<<PD4)                            
-// Read pins for BIOS patch
-#define PIN_AX_READ                (PIND   &   (1<<PIND2))                             
-#define PIN_AY_READ                (PIND   &   (1<<PIND3))                             
-
-// Handling the external interrupt
-#define PIN_AX_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT0)
-#define PIN_AY_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT1)
-
-#define PIN_AX_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT0)
-#define PIN_AY_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT1)
-
-#define PIN_AX_INTERRUPT_RISING     EICRA  |=  (1<<ISC01)|(1<<ISC00)
-#define PIN_AY_INTERRUPT_RISING     EICRA  |=  (1<<ISC11)|(1<<ISC10)
-
-#define PIN_AX_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC00)) | (1<<ISC01))
-#define PIN_AY_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC10)) | (1<<ISC11))
-
-#define PIN_AX_INTERRUPT_VECTOR        INT0_vect              
-#define PIN_AY_INTERRUPT_VECTOR        INT1_vect    
-
-// Handling and reading the switch pin for patch BIOS
-#define PIN_SWITCH_INPUT            DDRD   &= ~(1<<DDD5)                              
-#define PIN_SWITCH_SET              PORTD  |=  (1<<PD5)                                
-#define PIN_SWICHE_READ            (PIND   &   (1<<PIND5))
-
-
-
-
-#endif
 
 #ifdef ATmega32U4_16U4
 
@@ -343,10 +346,23 @@
 #define TIMER_INTERRUPT_ENABLE      TIMSK |=  (1<<OCIE0A)
 #define TIMER_INTERRUPT_DISABLE     TIMSK &= ~(1<<OCIE0A)
 
-#if !defined(SCPH_xxx1) && !defined(SCPH_xxx2) && !defined(SCPH_103)
- #error "ATtiny85_45_25 Not compatible with BIOS patch, please choose a compatible SCPH. For example: SCPH_xxx1: SCPH_xxx2: SCPH_103"
+// Handling and use of the LED pin
+#define LED_RUN
+#define PIN_LED_OUTPUT              DDRB   |=  (1<<DDB3)                                
+#define PIN_LED_ON                  PORTB  |=  (1<<PB3)      
+#define PIN_LED_OFF                 PORTB  &= ~(1<<PB3)   
+
+#if !defined(SCPH_xxx1) && !defined(SCPH_xxx2) && !defined(SCPH_103) && !defined(SCPH_xxxx)
+ #error "ATtiny85_45_25 Not compatible with BIOS patch"
 #endif
 
+
+// *****************************************************************************************************************
+// WARNING:
+// The following code  is not functional as-is. 
+// *****************************************************************************************************************
+
+
 #ifdef ATtiny88_48
 
 #define F_CPU 16000000L
@@ -448,16 +464,14 @@
 
 #ifdef ATtiny214_414
 
-
-
 //#define SET_CTRLA
-//#define F_CPU 16000000L
+#define DF_CPU 20000000L
 #define TIMER_TCNT_CLEAR            TCA0.SINGLE.CNT   =   0x00             //TCNT0 - Timer/Counter Register
-#define SET_OCROA_DIV               TCA0.SINGLE.CMP0L   =   159;             //OCR0A – Output Compare Register A, 0x10011111, 100KHz
-#define SET_TIMER_TCCROA            TCA0.SINGLE.CTRLB |=  TCA_SINGLE_WGMODE_FRQ_gc    //TCCR0A – Timer/Counter Control Register A. turn on CTC mode, CTC0
-#define SET_TIMER_TCCROB            TCA0.SINGLE.CTRLA |=  TCA_SINGLE_CLKSEL_DIV1_gc//TCCR0B – Timer/Counter Control Register B,  CS00: Clock Select,  clk I/O
+#define SET_OCROA_DIV               TCA0.SINGLE.CMP0L   =   100;             //OCR0A – Output Compare Register A, 0x10011111, 100KHz
+#define SET_TIMER_TCCROA            TCA0.SINGLE.CTRLB |=  (1 << TCA_SINGLE_WGM0); //TCA_SINGLE_WGMODE_FRQ_gc    //TCCR0A – Timer/Counter Control Register A. turn on CTC mode, CTC0
+#define SET_TIMER_TCCROB            TCA0.SINGLE.CTRLA |=  (1 << TCA_SINGLE_CLKSEL0);  //TCA_SINGLE_CLKSEL_DIV1_gc//TCCR0B – Timer/Counter Control Register B,  CS00: Clock Select,  clk I/O
                                                                  //Waveform Generation Mode, Mode 2 CTC
-#define CTC_TIMER_VECTOR            TCA0_CMP0_vect            //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
+#define CTC_TIMER_VECTOR            TCA0_OVF_vect         //TCA0_CMP0_vect            //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
 
 
 #include <stdint.h>
@@ -468,8 +482,8 @@
 #include <util/delay.h>
 
 // Globale interrupt seting
-#define GLOBAL_INTERRUPT_ENABLE     CPU.SREG   |=  (1<<7)           
-#define GLOBAL_INTERRUPT_DISABLE    CPU.SREG   &= ~(1<<7)    
+#define GLOBAL_INTERRUPT_ENABLE     __asm__ __volatile__ ("sei" ::) //CPU.SREG   |=  (1<<7)           
+#define GLOBAL_INTERRUPT_DISABLE    __asm__ __volatile__ ("cli" ::) //CPU.SREG   &= ~(1<<7)    
 
 // Handling the main pins
 
@@ -551,6 +565,103 @@
 
 #endif
 
+#ifdef LGT8F328P
+
+#define F_CPU 32000000L
+#define TIMER_TCNT_CLEAR            TCNT0   =   0x00             
+#define SET_OCROA_DIV               OCR0A   =   319;             
+#define SET_TIMER_TCCROA            TCCR0A |=  (1 << WGM01);     
+#define SET_TIMER_TCCROB            TCCR0B |=  (1 << CS00); 
+#define CTC_TIMER_VECTOR            TIMER0_COMPA_vect       
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <avr/sfr_defs.h>
+#include <util/delay.h>
+
+// Globale interrupt seting
+#define GLOBAL_INTERRUPT_ENABLE     SREG   |=  (1<<7)           
+#define GLOBAL_INTERRUPT_DISABLE    SREG   &= ~(1<<7)    
+
+// Handling the main pins
+
+// Main pins input
+#define PIN_DATA_INPUT              DDRB   &= ~(1<<DDB0)        
+#define PIN_WFCK_INPUT              DDRB   &= ~(1<<DDB1)       
+#define PIN_SQCK_INPUT              DDRD   &= ~(1<<DDD6)      
+#define PIN_SUBQ_INPUT              DDRD   &= ~(1<<DDD7) 
+                            
+// Main pin output
+#define PIN_DATA_OUTPUT             DDRB   |=  (1<<DDB0)       
+#define PIN_WFCK_OUTPUT             DDRB   |=  (1<<DDB1)       
+           
+// Define pull-ups and set high at the main pin
+#define PIN_DATA_SET                PORTB  |=  (1<<PB0)        
+                                                              
+             
+// Define pull-ups set down at the main pin
+#define PIN_DATA_CLEAR              PORTB  &= ~(1<<PB0)        
+#define PIN_WFCK_CLEAR              PORTB  &= ~(1<<PB1)        
+                         
+// Read the main pins
+#define PIN_SQCK_READ              (PIND   &   (1<<PIND6))         
+#define PIN_SUBQ_READ              (PIND   &   (1<<PIND7))     
+#define PIN_WFCK_READ              (PINB   &   (1<<PINB1))                                                       
+
+// Handling and use of the LED pin
+#define LED_RUN
+#define PIN_LED_OUTPUT              DDRB   |=  (1<<DDB5)                                
+#define PIN_LED_ON                  PORTB  |=  (1<<PB5)      
+#define PIN_LED_OFF                 PORTB  &= ~(1<<PB5)   
+
+// Handling the BIOS patch
+
+// BIOS interrupt seting
+#define TIMER_INTERRUPT_ENABLE      TIMSK0 |=  (1<<OCIE0A)
+#define TIMER_INTERRUPT_DISABLE     TIMSK0 &= ~(1<<OCIE0A)
+
+// BIOS timer clear
+#define TIMER_TIFR_CLEAR            TIFR0  |=  (1<<OCF0A)
+
+// Pins input
+#define PIN_AX_INPUT                DDRD   &= ~(1<<DDD2)                            
+#define PIN_AY_INPUT                DDRD   &= ~(1<<DDD3)                             
+#define PIN_DX_INPUT                DDRD   &= ~(1<<DDD4)                             
+// Pin output
+#define PIN_DX_OUTPUT               DDRD   |=  (1<<DDD4)                             
+// Define pull-ups set high 
+#define PIN_DX_SET                  PORTD  |=  (1<<PD4)                              
+// Define pull-ups set down 
+#define PIN_DX_CLEAR                PORTD  &= ~(1<<PD4)                            
+// Read pins for BIOS patch
+#define PIN_AX_READ                (PIND   &   (1<<PIND2))                             
+#define PIN_AY_READ                (PIND   &   (1<<PIND3))                             
+
+// Handling the external interrupt
+#define PIN_AX_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT0)
+#define PIN_AY_INTERRUPT_ENABLE     EIMSK  |=  (1<<INT1)
+
+#define PIN_AX_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT0)
+#define PIN_AY_INTERRUPT_DISABLE    EIMSK  &= ~(1<<INT1)
+
+#define PIN_AX_INTERRUPT_RISING     EICRA  |=  (1<<ISC01)|(1<<ISC00)
+#define PIN_AY_INTERRUPT_RISING     EICRA  |=  (1<<ISC11)|(1<<ISC10)
+
+#define PIN_AX_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC00)) | (1<<ISC01))
+#define PIN_AY_INTERRUPT_FALLING   (EICRA   =  (EICRA & ~(1<<ISC10)) | (1<<ISC11))
+
+#define PIN_AX_INTERRUPT_VECTOR        INT0_vect              
+#define PIN_AY_INTERRUPT_VECTOR        INT1_vect    
+
+// Handling and reading the switch pin for patch BIOS
+#define PIN_SWITCH_INPUT            DDRD   &= ~(1<<DDD5)                              
+#define PIN_SWITCH_SET              PORTD  |=  (1<<PD5)                                
+#define PIN_SWICHE_READ            (PIND   &   (1<<PIND5))
+
+#endif
 
 #ifdef CH32V003
 
diff --git a/PSNee_V8.5/PSNee_V8.5/PSNee_V8.5.ino b/PSNee_V8.6/PSNee_V8.6/PSNee_V8.6.ino
similarity index 60%
rename from PSNee_V8.5/PSNee_V8.5/PSNee_V8.5.ino
rename to PSNee_V8.6/PSNee_V8.6/PSNee_V8.6.ino
index 94c211b..b71e19f 100644
--- a/PSNee_V8.5/PSNee_V8.5/PSNee_V8.5.ino
+++ b/PSNee_V8.6/PSNee_V8.6/PSNee_V8.6.ino
@@ -1,21 +1,3 @@
-//------------------------------------------------------------------------------------------------
-//                         Select your chip
-//------------------------------------------------------------------------------------------------
-
-//#define ATmega328_168  // Fuses: JAP_FAT - H: DF, L: EE, E: FF; Other - H: DF, L: FF, E: FF.
-//#define ATmega32U4_16U4
-//#define ATtiny85_45_25
-
-/*  PinVCC-3.5v, PinGND-GND, 
-    Pin2-BIOS AX, 
-    Pin3-BIOS AY, 
-    Pin4-BIOS DX, Pin5-Switch*(optional),
-    Pin6-SQCK, 
-    Pin7-SUBQ, 
-    Pin8-DATA, 
-    Pin9-GATE_WFCK, 
-    PinRST-RESET*(Only for JAP_FAT)  */
-
 //------------------------------------------------------------------------------------------------
 //                         Select your console
 //------------------------------------------------------------------------------------------------
@@ -23,23 +5,67 @@
 //   If a BIOS checksum is specified, it is more important than the SCPH model number!
 //------------------------------------------------------------------------------------------------
 
+//All NTSC-U/C SCPH_xxx1, all PAL FAT models SCPH_xxx2, SCPH_103. It's 0.5 seconds longer than choosing a specific region.
+//#define SCPH_xxxx
+
+//Here the regions are specified
 //#define SCPH_xxx1        // Use for all NTSC-U/C models. No BIOS patching needed.
 //#define SCPH_xxx2        // Use for all PAL FAT models. No BIOS patching needed.
-//#define SCPH_103         // No BIOS patching needed.
+//#define SCPH_103         // Maybe for all SCPH_xxx3 but I have no info.
+
+//And all models that require a BIOS patch
 //#define SCPH_102         // DX - D0, AX - A7. BIOS ver. 4.4e, CRC 0BAD7EA9 | 4.5e, CRC 76B880E5
 //#define SCPH_100         // DX - D0, AX - A7. BIOS ver. 4.3j, CRC F2AF798B
-//#define SCPH_7000_9000  // DX - D0, AX - A7. BIOS ver. 4.0j, CRC EC541CD0
+//#define SCPH_7000_9000   // DX - D0, AX - A7. BIOS ver. 4.0j, CRC EC541CD0
 //#define SCPH_5500        // DX - D0, AX - A5. BIOS ver. 3.0j, CRC FF3EEB8C
 //#define SCPH_3500_5000   // DX - D0, for 40-pin BIOS: AX - A4, for 32-pin BIOS: AX - A5. BIOS ver. 2.2j, CRC 24FC7E17 | 2.1j, CRC BC190209
 //#define SCPH_3000        // DX - D5, for 40-pin BIOS: AX - A6, AY - A7, for 32-pin BIOS: AX - A7, AY - A8. BIOS ver. 1.1j, CRC 3539DEF6
 //#define SCPH_1000        // DX - D5, for 40-pin BIOS: AX - A6, AY - A7, for 32-pin BIOS: AX - A7, AY - A8. BIOS ver. 1.0j, CRC 3B601FC8
 
+
+//------------------------------------------------------------------------------------------------
+//                         Select your chip
+//------------------------------------------------------------------------------------------------
+
+//#define ATmega328_168  
+//#define ATmega32U4_16U4
+//#define ATtiny85_45_25 
+
+/*  
+  Fuses: 
+  ATmega - H: DF, L: EE, E: FD. 
+  ATtiny - H: DF, L: E2; E: FD.
+
+  Pinout Arduino:
+  VCC-3.5v, PinGND-GND, 
+  D2-BIOS AX (Only for Bios patch)
+  D3-BIOS AY (Only for BIOS ver. 1.0j-1.1j)
+  D4-BIOS DX (Only for Bios patch)
+  D5-Switch* (Optional for Bios patch)
+  D6-SQCK
+  D7-SUBQ
+  D8-DATA
+  D9-GATE_WFCK
+  RST-RESET* (Only for JAP_FAT)
+
+  Pinout ATtiny:
+  Pin1-RESET
+  Pin2-LED
+  Pin3-WFCK
+  Pin4-GND
+  Pin5-SQCK (MOSI)
+  Pin6-SUBQ (MISO)
+  Pin7_DATA (SCK)
+  Pin8-VCC
+*/
+  
+
 //------------------------------------------------------------------------------------------------
 //                         Options
 //------------------------------------------------------------------------------------------------
 
-//#define PATCH_SWICHE  // Enables hardware support for disabling BIOS patching.
-//#define LED_RUN
+#define LED_RUN         // Turns on the LED when injections occur. D13 for Arduino, ATtiny add a led between PB3 (pin 2) and gnd with a 1k resistor in series, ATmega32U4 (Pro Micro) add a led between PB6 (pin 10) and gnd with a 1k resistor in series
+//#define PATCH_SWICHE  // Enables hardware support for disabling BIOS patching. Useful in rare cases where the BIOS patch prevents the playback of original games
 
 //------------------------------------------------------------------------------------------------
 //                         pointer and variable section
@@ -62,11 +88,28 @@ volatile uint16_t millisec = 0;
 //Flag initializing for automatic console generation selection 0 = old, 1 = pu-22 end  ++
 volatile bool wfck_mode = 0;
 
+volatile bool Flag_Switch = 0;
+
 //------------------------------------------------------------------------------------------------
 //                         Code section
 //------------------------------------------------------------------------------------------------
 
-//Counter increment function  Fuses
+// *****************************************************************************************
+// Interrupt Service Routine: CTC_TIMER_VECTOR
+// Description: 
+// This ISR is triggered by the Timer/Counter Compare Match event. It increments time-related 
+// counters used for tracking microseconds and milliseconds.
+//
+// Functionality:
+// - Increments `microsec` by 10 on each interrupt call.
+// - Increments `count_isr` to keep track of the number of interrupts.
+// - When `count_isr` reaches 100, it means 1 millisecond has elapsed:
+//     - `millisec` is incremented.
+//     - `count_isr` is reset to 0.
+//
+// Notes:
+// - This method provides a simple way to maintain a software-based timekeeping system.
+// *****************************************************************************************
 ISR(CTC_TIMER_VECTOR) {
   microsec += 10;                    
   count_isr++;                  
@@ -77,9 +120,30 @@ ISR(CTC_TIMER_VECTOR) {
   }
 }
 
-//Timer register reset function
+// *****************************************************************************************
+// Function: Timer_Start
+// Description: 
+// This function initializes and starts the timer by resetting the timer counter register 
+// and enabling timer interrupts. It ensures compatibility across multiple microcontrollers.
+//
+// Supported Microcontrollers:
+// - ATmega328/168
+// - ATmega32U4/16U4
+// - ATtiny85/45/25
+//
+// Functionality:
+// - Clears the timer counter to ensure a fresh start.
+// - Enables the timer interrupt to allow periodic execution of ISR routines.
+// - If BIOS_PATCH is defined, it also clears the timer interrupt flag to prevent 
+//   unwanted immediate interrupts.
+//
+// Notes:
+// - The actual timer configuration is handled in MUC.h.
+// - This function ensures that all supported MCUs behave consistently.
+//
+// *****************************************************************************************
 void Timer_Start() {
-#if defined(ATmega328_168) || defined(ATmega32U4_16U4) || defined(ATtiny85_45_25) || defined(LGT8F328P)
+#if defined(ATmega328_168) || defined(ATmega32U4_16U4) || defined(ATtiny85_45_25)
   TIMER_TCNT_CLEAR;
   TIMER_INTERRUPT_ENABLE;
   #if defined(BIOS_PATCH)
@@ -88,50 +152,71 @@ void Timer_Start() {
 #endif
 }
 
-//Function to stop timer registers, and reset time counters
+// *****************************************************************************************
+// Function: Timer_Stop
+// Description: 
+// Stops the timer by disabling interrupts and resetting the timer counter. 
+// It also clears the time tracking variables (count_isr, microsec, millisec) 
+// to ensure a fresh start when the timer is restarted.
+//
+// Supported Microcontrollers:
+// - ATmega328/168
+// - ATmega32U4/16U4
+// - ATtiny85/45/25
+//
+// *****************************************************************************************
 void Timer_Stop() {
   
-  #if defined(ATmega328_168) || defined(ATmega32U4_16U4) || defined(ATtiny85_45_25) || defined(LGT8F328P)
-    TIMER_INTERRUPT_DISABLE;
-    TIMER_TCNT_CLEAR;
+  #if defined(ATmega328_168) || defined(ATmega32U4_16U4) || defined(ATtiny85_45_25)
+    TIMER_INTERRUPT_DISABLE;  // Disable timer interrupts to stop counting
+    TIMER_TCNT_CLEAR;         // Reset the timer counter to ensure proper timing when restarted
   #endif
+  // Reset time tracking variables
   count_isr = 0;
   microsec = 0;
   millisec = 0;
 }
 
-void Init() {
-#if defined(ATmega328_168) || defined(ATmega32U4_16U4) || defined(ATtiny85_45_25) || defined(LGT8F328P)
-  TIMER_TCNT_CLEAR;
-  SET_OCROA_DIV;
-  SET_TIMER_TCCROA;
-  SET_TIMER_TCCROB;
-#endif
-
-#if defined(PATCH_SW) && defined(BIOS_PATCH)
-  PIN_SWITCH_INPUT;
-  PIN_SWITCH_SET;
-#endif
-
-#ifdef LED_RUN
-  PIN_LED_OUTPUT;
-#endif
-
-  GLOBAL_INTERRUPT_ENABLE;
-  
-  PIN_SQCK_INPUT;
-  PIN_SUBQ_INPUT;
-}
-
-// borrowed from AttyNee. Bitmagic to get to the SCEX strings stored in flash (because Harvard architecture)
-// Read a specific bit from an array of bytes
+// *****************************************************************************************
+// Function: readBit
+// Description: 
+// Reads a specific bit from an array of bytes.
+// This function helps retrieve SCEX data efficiently while working within 
+// the constraints of Harvard architecture.
+//
+// Parameters:
+// - index: The bit position to read within the byte array.
+// - ByteSet: A pointer to the byte array containing the data.
+//
+// Return:
+// - Returns 1 if the specified bit at the given index is set (1).
+// - Returns 0 if the specified bit is cleared (0).
+//
+// Explanation:
+// - The function determines which byte contains the requested bit using (index / 8).
+// - It then calculates the bit position within that byte using (index % 8).
+// - A bitwise AND operation extracts the bit's value, and the double NOT (!!) operator 
+//   ensures a clean boolean return value (1 or 0).
+//
+// *****************************************************************************************
 uint8_t readBit(uint8_t index, const uint8_t* ByteSet) {
   return !!(ByteSet[index / 8] & (1 << (index % 8)));  // Return true if the specified bit is set in ByteSet[index]
 }
 
 
-// Static arrays storing SCEX data for different regions
+// *****************************************************************************************
+// Function: inject_SCEX
+// Description: 
+// Injects SCEX data corresponding to a given region ('e' for Europe, 'a' for America, 
+// 'i' for Japan). This function is used for modulating the SCEX signal to bypass 
+// region-locking mechanisms.
+//
+// Parameters:
+// - region: A character ('e', 'a', or 'i') representing the target region.
+//
+// *****************************************************************************************
 void inject_SCEX(const char region) {
+  // SCEX data patterns for different regions (SCEE, SCEA, SCEI)
   static const uint8_t SCEEData[] = {
     0b01011001,
     0b11001001,
@@ -169,12 +254,12 @@ void inject_SCEX(const char region) {
     }
     else {
       // modulate DATA pin based on WFCK_READ
-      if (wfck_mode)  // If wfck_mode is true(pu22mode)
+      if (wfck_mode)  // WFCK mode (pu22mode enabled): synchronize PIN_DATA with WFCK clock signal
       {
         PIN_DATA_OUTPUT;
         Timer_Start();
         do {
-          // read wfck pin
+          // Read the WFCK pin and set or clear DATA accordingly
           if (PIN_WFCK_READ) {
             PIN_DATA_SET; 
           }
@@ -184,9 +269,9 @@ void inject_SCEX(const char region) {
           }
         }
         while (microsec < DELAY_BETWEEN_BITS);
-        Timer_Stop();  // Stop timer
+        Timer_Stop();  // Stop the timer after the delay
       }
-      // PU-18 or lower mode
+      // PU-18 or lower mode: simply set PIN_DATA as input with a delay
       else {
         PIN_DATA_INPUT;
         _delay_us(DELAY_BETWEEN_BITS);
@@ -199,6 +284,32 @@ void inject_SCEX(const char region) {
   _delay_ms(DELAY_BETWEEN_INJECTIONS);
 }
 
+void Init() {
+#if defined(ATmega328_168) || defined(ATmega32U4_16U4) || defined(ATtiny85_45_25)
+  TIMER_TCNT_CLEAR;
+  SET_OCROA_DIV;
+  SET_TIMER_TCCROA;
+  SET_TIMER_TCCROB;
+#endif
+
+#if defined(PATCH_SW) && defined(BIOS_PATCH)
+  PIN_SWITCH_INPUT;
+  PIN_SWITCH_SET;
+  if (PIN_SWICHE_READ = 0){
+   Flag_Switch =1;
+  }
+#endif
+
+#ifdef LED_RUN
+  PIN_LED_OUTPUT;
+#endif
+
+  GLOBAL_INTERRUPT_ENABLE;
+  
+  PIN_SQCK_INPUT;
+  PIN_SUBQ_INPUT;
+}
+
 int main() {
   uint8_t  hysteresis = 0;
   uint8_t  scbuf[12] = { 0 };             // SUBQ bit storage
@@ -210,39 +321,31 @@ int main() {
 
   Init();
 
+#if defined(BIOS_PATCH)
+
 #ifdef LED_RUN
   PIN_LED_ON;
 #endif
 
-#if defined(BIOS_PATCH) && !defined(PATCH_SWICHE)
-  Bios_Patching();
-#elif defined(BIOS_PATCH) && defined(PATCH_SWICHE)
-  if (PIN_SWICHE_READ != 0) {
+  if (Flag_Switch == 0) {
     Bios_Patching();
-  } else {
-
-    while (PIN_SQCK_READ == 0)
-      ;
-    while (PIN_WFCK_READ == 0)
-      ;
   }
-  // wait for console power on and stable signals
-#else
 
-  while (PIN_SQCK_READ == 0)
-    ;
-  while (PIN_WFCK_READ == 0)
-    ;
+#ifdef LED_RUN
+  PIN_LED_OFF;
+#endif
+
 #endif
 
   Timer_Start();
-
+  //************************************************************************
   // Board detection
   //
   // GATE: __-----------------------  // this is a PU-7 .. PU-20 board!
   //
   // WFCK: __-_-_-_-_-_-_-_-_-_-_-_-  // this is a PU-22 or newer board!
   // typical readouts PU-22: highs: 2449 lows: 2377
+  //************************************************************************
   do {
     if (PIN_WFCK_READ == 0) lows++;             // good for ~5000 reads in 1s
     _delay_us(200);
@@ -259,10 +362,6 @@ int main() {
     wfck_mode = 0;                             //flag oldmod
   }
 
-#ifdef LED_RUN
-  PIN_LED_OFF;
-#endif
-
   while (1) {
 
     _delay_ms(1); /* Start with a small delay, which can be necessary 
@@ -306,12 +405,14 @@ int main() {
 
     GLOBAL_INTERRUPT_ENABLE;  // End critical section
 
-    /* Check if read head is in wobble area
-    |  We only want to unlock game discs (0x41) and only if the read head is in the outer TOC area.
-    |  We want to see a TOC sector repeatedly before injecting (helps with timing and marginal lasers).
-    |  All this logic is because we don't know if the HC-05 is actually processing a getSCEX() command.
-    |  Hysteresis is used because older drives exhibit more variation in read head positioning.
-    |  While the laser lens moves to correct for the error, they can pick up a few TOC sectors. */
+    //************************************************************************
+    // Check if read head is in wobble area
+    // We only want to unlock game discs (0x41) and only if the read head is in the outer TOC area.
+    // We want to see a TOC sector repeatedly before injecting (helps with timing and marginal lasers).
+    // All this logic is because we don't know if the HC-05 is actually processing a getSCEX() command.
+    // Hysteresis is used because older drives exhibit more variation in read head positioning.
+    // While the laser lens moves to correct for the error, they can pick up a few TOC sectors.
+    //************************************************************************
 
     //This variable initialization macro is to replace (0x41) with a filter that will check that only the three most significant bits are correct. 0x001xxxxx
     uint8_t isDataSector = (((scbuf[0] & 0x40) == 0x40) && (((scbuf[0] & 0x10) == 0) && ((scbuf[0] & 0x80) == 0)));
@@ -341,8 +442,12 @@ int main() {
       // Hysteresis naturally goes to 0 otherwise (the read head moved).
       hysteresis = 11;
 
+    //************************************************************************
+    //Executes the region code patch injection sequence.
+    //************************************************************************
+
 #ifdef LED_RUN
-      PIN_LED_ON;
+  PIN_LED_ON;
 #endif
 
       PIN_DATA_OUTPUT;  
@@ -358,7 +463,7 @@ int main() {
 
       // inject symbols now. 2 x 3 runs seems optimal to cover all boards
       for (uint8_t scex = 0; scex < 2; scex++) {
-        inject_SCEX(region[scex]);  //
+        inject_SCEX(region[scex]);
       }
 
       if (!wfck_mode)  // Set WFCK pin input
@@ -369,7 +474,7 @@ int main() {
       PIN_DATA_INPUT;
 
 #ifdef LED_RUN
-      PIN_LED_OFF;
+  PIN_LED_OFF;
 #endif
     }
   }
diff --git a/PSNee_V8.5/PSNee_V8.5/settings.h b/PSNee_V8.6/PSNee_V8.6/settings.h
similarity index 91%
rename from PSNee_V8.5/PSNee_V8.5/settings.h
rename to PSNee_V8.6/PSNee_V8.6/settings.h
index 28f2882..e647712 100644
--- a/PSNee_V8.5/PSNee_V8.5/settings.h
+++ b/PSNee_V8.6/PSNee_V8.6/settings.h
@@ -17,7 +17,9 @@
 
 */
 
-
+#ifdef  SCPH_xxxx
+#define SCEZ
+#endif
 
 #ifdef  SCPH_xxx1
 #define SCEA
@@ -111,25 +113,29 @@
 #endif
 
 #ifdef SCEA
-const char region[3] = {'a', 'a', 'a'};
+const char region[1] = {'a'};
 #endif
 
 #ifdef SCEE
-const char region[3] = {'e', 'e', 'e'};
+const char region[1] = {'e'};
 #endif
 
 #ifdef SCEI
-const char region[3] = {'i', 'i', 'i'};
+const char region[1] = {'i'};
+#endif
+
+#ifdef SCEZ
+const char region[3] = {'a', 'e', 'i'};
 #endif
 
 #if !defined(SCPH_xxx1) && !defined(SCPH_xxx2) && !defined(SCPH_103) && \
     !defined(SCPH_102) && !defined(SCPH_100) && !defined(SCPH_7000_9000) && \
     !defined(SCPH_5500) && !defined(SCPH_3500_5000) && !defined(SCPH_3000) && \
-    !defined(SCPH_1000)
+    !defined(SCPH_1000) && !defined(SCPH_xxxx)
  #error "Console not selected! Please uncoment #define with SCPH model number."
 #elif !(defined(SCPH_xxx1) ^ defined(SCPH_xxx2) ^ defined(SCPH_103) ^ \
       defined(SCPH_102) ^ defined(SCPH_100) ^ defined(SCPH_7000_9000) ^ \
       defined(SCPH_5500) ^ defined(SCPH_3500_5000) ^ defined(SCPH_3000) ^ \
-      defined(SCPH_1000))
+      defined(SCPH_1000) ^ defined(SCPH_xxxx))
  #error "May be selected only one console! Please check #define with SCPH model number."
 #endif
diff --git a/PSNeecore/hardware/avr/1.0.1/boards.txt b/PSNeecore-1.2/avr/boards.txt
similarity index 88%
rename from PSNeecore/hardware/avr/1.0.1/boards.txt
rename to PSNeecore-1.2/avr/boards.txt
index d9a29e6..5b7a63d 100644
--- a/PSNeecore/hardware/avr/1.0.1/boards.txt
+++ b/PSNeecore-1.2/avr/boards.txt
@@ -1,6 +1,6 @@
 # Menu options
 menu.variant=Variant
-menu.fuses=Fuses
+#menu.fuses=Fuses
 
 ##############################
 ### ATiny25/45/85     ########
@@ -11,8 +11,7 @@ menu.fuses=Fuses
 ATtinyX5.name=ATtiny25/45/85
 
 ATtinyX5.upload.tool=arduino:avrdude
-ATtinyX5.upload.low_fuses=0xff
-
+ATtinyX5.upload.low_fuses=0xe2
 
 ATtinyX5.program.tool=arduino:avrdude
 ATtinyX5.program.unlock_bits=0xff
@@ -87,11 +86,11 @@ ATtinyX8.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 # General
 328.name=ATmega328
 
-328.32u4.tool=arduino:avrdude
+328.upload.tool=arduino:avrdude
 328.upload.default_speed=57600
 328.upload.maximum_data_size=2048
 328.upload.maximum_size=30720
-
+328.upload.low_fuses=0xee
 
 328.build.core=arduino:arduino
 328.build.board=AVR_ATmega328
@@ -110,11 +109,7 @@ ATtinyX8.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 328.menu.variant.modelPB.build.variant=pb-variant 
 328.menu.variant.modelPB.build.mcu=atmega328pb
 
-328.menu.fuses.BIOSpatch=BIOS patch
-328.menu.fuses.BIOSpatch.upload.low_fuses=0xee
 
-328.menu.fuses.NoBIOSpatch=No BIOS patch
-328.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 
 #############################
 #### ATmega168/A/P/PA/PB ####
@@ -126,6 +121,7 @@ ATtinyX8.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 168.upload.default_speed=57600
 168.upload.maximum_size=15872
 168.upload.maximum_data_size=1024
+168.upload.low_fuses=0xee
 
 168.build.core=arduino:arduino
 168.build.board=AVR_ATmega168
@@ -145,12 +141,6 @@ ATtinyX8.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 168.menu.variant.modelPB.build.variant=pb-variant
 168.menu.variant.modelPB.build.mcu=atmega168pb
 
-168.menu.fuses.BIOSpatch=BIOS patch
-168.menu.fuses.BIOSpatch.upload.low_fuses=0xee
-
-168.menu.fuses.NoBIOSpatch=No BIOS patch
-168.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
-
 #############################
 #### atmega32u4          ####
 #############################
@@ -189,6 +179,7 @@ ATtinyX8.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 32u4.upload.maximum_size=30720
 32u4.upload.use_1200bps_touch=true
 32u4.upload.wait_for_upload_port=true
+32u4.upload.low_fuses=0xee
 
 
 
@@ -206,9 +197,4 @@ ATtinyX8.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 32u4.vid.0=0x239A
 32u4.pid.0=0x800C
 
-32u4.menu.fuses.BIOSpatch=BIOS patch
-32u4.menu.fuses.BIOSpatch.upload.low_fuses=0xee
-
-32u4.menu.fuses.NoBIOSpatch=No BIOS patch
-32u4.menu.fuses.NoBIOSpatch.upload.low_fuses=0xff
 
diff --git a/PSNeecore/hardware/avr/1.0.1/bootloaders/bootloader.txt b/PSNeecore-1.2/avr/bootloaders/bootloader.txt
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/bootloaders/bootloader.txt
rename to PSNeecore-1.2/avr/bootloaders/bootloader.txt
diff --git a/PSNeecore/hardware/avr/1.0.1/platform.txt b/PSNeecore-1.2/avr/platform.txt
similarity index 73%
rename from PSNeecore/hardware/avr/1.0.1/platform.txt
rename to PSNeecore-1.2/avr/platform.txt
index 6162f14..8611ad0 100644
--- a/PSNeecore/hardware/avr/1.0.1/platform.txt
+++ b/PSNeecore-1.2/avr/platform.txt
@@ -1,5 +1,5 @@
-name=PSNee
-version=1.0.1
+name=PSNeeCore
+version=1.2.0
 
 tools.avrdude.path={runtime.tools.avrdude.path}
 tools.avrdude.cmd.path={path}/bin/avrdude
@@ -11,11 +11,11 @@ tools.avrdude.program.params.quiet=-q -q
 # tools.avrdude.program.verify is needed for backwards compatibility with IDE 1.6.8 or older, IDE 1.6.9 or newer overrides this value
 tools.avrdude.program.verify=
 tools.avrdude.program.params.noverify=-V
-tools.avrdude.program.pattern="{cmd.path}" "-C{config.path}" {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} -Uefuse:w:0xff:m -Uhfuse:w:0xdf:m -Ulfuse:w:{upload.low_fuses}:m "-Uflash:w:{build.path}/{build.project_name}.hex:i"
+tools.avrdude.program.pattern="{cmd.path}" "-C{config.path}" -F {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} -Uefuse:w:0xfd:m -Uhfuse:w:0xdf:m -Ulfuse:w:{upload.low_fuses}:m "-Uflash:w:{build.path}/{build.project_name}.hex:i"
 
 tools.avrdude.erase.params.verbose=-v -v -v -v
 tools.avrdude.erase.params.quiet=-q -q
-tools.avrdude.erase.pattern="{cmd.path}" "-C{config.path}" {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Uefuse:w:0xff:m -Uhfuse:w:0xdf:m -Ulfuse:w:{bootloader.low_fuses}:m
+tools.avrdude.erase.pattern="{cmd.path}" "-C{config.path}" {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Uefuse:w:0xfd:m -Uhfuse:w:0xdf:m -Ulfuse:w:{bootloader.low_fuses}:m
 
 ##tools.avrdude.bootloader.params.verbose=-v
 ##tools.avrdude.bootloader.params.quiet=-q -q
diff --git a/PSNeecore/hardware/avr/1.0.1/variants/leonardo/pins_arduino.h b/PSNeecore-1.2/avr/variants/leonardo/pins_arduino.h
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/variants/leonardo/pins_arduino.h
rename to PSNeecore-1.2/avr/variants/leonardo/pins_arduino.h
diff --git a/PSNeecore/hardware/avr/1.0.1/variants/micro/pins_arduino.h b/PSNeecore-1.2/avr/variants/micro/pins_arduino.h
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/variants/micro/pins_arduino.h
rename to PSNeecore-1.2/avr/variants/micro/pins_arduino.h
diff --git a/PSNeecore/hardware/avr/1.0.1/variants/pb-variant/pins_arduino.h b/PSNeecore-1.2/avr/variants/pb-variant/pins_arduino.h
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/variants/pb-variant/pins_arduino.h
rename to PSNeecore-1.2/avr/variants/pb-variant/pins_arduino.h
diff --git a/PSNeecore/hardware/avr/1.0.1/variants/standard/pins_arduino.h b/PSNeecore-1.2/avr/variants/standard/pins_arduino.h
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/variants/standard/pins_arduino.h
rename to PSNeecore-1.2/avr/variants/standard/pins_arduino.h
diff --git a/PSNeecore/hardware/avr/1.0.1/variants/tiny8/pins_arduino.h b/PSNeecore-1.2/avr/variants/tiny8/pins_arduino.h
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/variants/tiny8/pins_arduino.h
rename to PSNeecore-1.2/avr/variants/tiny8/pins_arduino.h
diff --git a/PSNeecore/hardware/avr/1.0.1/variants/tinyx8/pins_arduino.h b/PSNeecore-1.2/avr/variants/tinyx8/pins_arduino.h
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/variants/tinyx8/pins_arduino.h
rename to PSNeecore-1.2/avr/variants/tinyx8/pins_arduino.h
diff --git a/PSNeecore/hardware/avr/1.0.1/variants/tinyx8_mh/pins_arduino.h b/PSNeecore-1.2/avr/variants/tinyx8_mh/pins_arduino.h
similarity index 100%
rename from PSNeecore/hardware/avr/1.0.1/variants/tinyx8_mh/pins_arduino.h
rename to PSNeecore-1.2/avr/variants/tinyx8_mh/pins_arduino.h
diff --git a/README.md b/README.md
index 9f07713..a567dc3 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
-# PSNee V8.5
+# PSNee V8.6
 THE modechip supports the largest number of Playstation 1 variants, and the largest number of microcontrollers
 
-![Logo](images/PSNee_V8_logo.png)
+![Logo](/images/PSNee-8.6-logo.png)
 
 ## Features
 - Remove Disk Region Protection
@@ -22,4 +22,6 @@ All US models, all European models, and the vast majority of Japanese models.
 For all useful information consult the Wiki
 
 ## Model tested
-![test](images/model_tested.png)
+![test](images/test-PSNee-v8.6.png)
+
+P.S. I don't have an American model, or SCPH_xxx3. If you have tested it, tell me.
diff --git a/changelog b/changelog
index 9a479cd..3329036 100644
--- a/changelog
+++ b/changelog
@@ -1,7 +1,11 @@
+Update:mars 2025
+
+-Added led support for ATtiny
+-Added card support to simplify fuse management
+
 Update:july 2024
 
 -Reimplementation of support for MUCs ATtiny25/45/85, Atmega32u4
--added support for MUC LGF8F328
 
 -------------------------------------------------------------
 
diff --git a/images/BIOS/32p SCPH 3500-5000-pic.png b/images/BIOS/32p SCPH 3500-5000-pic.png
new file mode 100644
index 0000000..b9f4457
Binary files /dev/null and b/images/BIOS/32p SCPH 3500-5000-pic.png differ
diff --git a/images/MUC Arduino/ATtiny25_45_85.png b/images/MUC Arduino/ATtiny25_45_85.png
index 0532bea..44610ff 100644
Binary files a/images/MUC Arduino/ATtiny25_45_85.png and b/images/MUC Arduino/ATtiny25_45_85.png differ
diff --git a/images/MUC Arduino/Pro Micro.png b/images/MUC Arduino/Pro Micro.png
index d8993d3..b1cdbeb 100644
Binary files a/images/MUC Arduino/Pro Micro.png and b/images/MUC Arduino/Pro Micro.png differ
diff --git a/images/MUC Arduino/micro.png b/images/MUC Arduino/micro.png
index d90a7de..fd8efba 100644
Binary files a/images/MUC Arduino/micro.png and b/images/MUC Arduino/micro.png differ
diff --git a/images/PSNee-8.6-logo.png b/images/PSNee-8.6-logo.png
new file mode 100644
index 0000000..a7b663c
Binary files /dev/null and b/images/PSNee-8.6-logo.png differ
diff --git a/images/PSNee_V8_logo.png b/images/PSNee_V8_logo.png
deleted file mode 100644
index eb4cd5a..0000000
Binary files a/images/PSNee_V8_logo.png and /dev/null differ
diff --git a/images/model_tested.png b/images/model_tested.png
deleted file mode 100644
index a6e70e5..0000000
Binary files a/images/model_tested.png and /dev/null differ
diff --git a/images/schemat/LED_PIN.png b/images/schemat/LED_PIN.png
new file mode 100644
index 0000000..5c81a0b
Binary files /dev/null and b/images/schemat/LED_PIN.png differ
diff --git a/images/schemat/PIN_SWITCH.png b/images/schemat/PIN_SWITCH.png
new file mode 100644
index 0000000..28b7ef8
Binary files /dev/null and b/images/schemat/PIN_SWITCH.png differ
diff --git a/images/test-PSNee-v8.6.png b/images/test-PSNee-v8.6.png
new file mode 100644
index 0000000..13c5efd
Binary files /dev/null and b/images/test-PSNee-v8.6.png differ