From b0f882668533ff382698beded758355e44d44a1e Mon Sep 17 00:00:00 2001 From: kalymos Date: Wed, 18 Mar 2026 18:45:40 +0100 Subject: [PATCH] finalize ATmega328 BIOS timers; start ATmega32U4 support Completed BIOS patching timer adjustments for ATmega328. Initialized timer configuration and register mapping for ATmega32U4. --- PSNee/BIOS_patching.h | 22 ++++--- PSNee/MCU.h | 138 ++++++++++-------------------------------- PSNee/PSNee.ino | 4 +- PSNee/settings.h | 29 +++++---- 4 files changed, 65 insertions(+), 128 deletions(-) diff --git a/PSNee/BIOS_patching.h b/PSNee/BIOS_patching.h index b588288..1355579 100644 --- a/PSNee/BIOS_patching.h +++ b/PSNee/BIOS_patching.h @@ -94,7 +94,7 @@ void Bios_Patching(void) { #if defined(SCPH_7000) PIN_SWITCH_INPUT; // Configure Pin D5 as Input PIN_SWITCH_SET; // Enable internal Pull-up (D5 defaults to HIGH) - __builtin_avr_delay_cycles(2); // Short delay for voltage stabilization + __builtin_avr_delay_cycles(10); // Short delay for voltage stabilization /** * Exit immediately if the switch pulls the pin to GND (Logic LOW). @@ -140,17 +140,21 @@ void Bios_Patching(void) { // --- PHASE 3: LAUNCH HARDWARE COUNTING (AX) --- impulse = PULSE_COUNT; PIN_LED_ON; + PIN_AX_INTERRUPT_CLEAR; PIN_AX_INTERRUPT_RISING; // Setup rising-edge trigger PIN_AX_INTERRUPT_ENABLE; // Engage ISR - while (patch != 1); // Busy-wait for ISR completion + while (patch != 1); + // --- PHASE 4 & 5: SECONDARY PATCHING SEQUENCE --- #ifdef INTERRUPT_RISING_HIGH_PATCH + PIN_AY_INPUT; current_confirms = 0; + impulse = PULSE_COUNT_2; // Monitor for the specific silent gap before the second patch window while (current_confirms < CONFIRM_COUNTER_TARGET_2) { - count = SILENCE_THRESHOLD; + uint16_t count = SILENCE_THRESHOLD; while (count > 0) { if (PIN_AX_READ != 0) { while (WAIT_AX_FALLING); @@ -163,15 +167,19 @@ void Bios_Patching(void) { } } - impulse = PULSE_COUNT_2; PIN_LED_ON; - PIN_AY_INTERRUPT_RISING; + PIN_AY_INTERRUPT_CLEAR; + PIN_AY_INTERRUPT_FALLING; PIN_AY_INTERRUPT_ENABLE; - + while (patch != 2); // Busy-wait for secondary ISR completion + + + return; + #endif - cli(); // Post-patching cleanup: disable interrupts + } #endif diff --git a/PSNee/MCU.h b/PSNee/MCU.h index 67b1352..d5025bd 100644 --- a/PSNee/MCU.h +++ b/PSNee/MCU.h @@ -317,13 +317,12 @@ defined(SCPH_1000) // Address (AX) and Data (DX) lines for BIOS override - #define PIN_AX_INPUT DDRD &= ~(1 << DDD2) #define PIN_DX_INPUT DDRD &= ~(1 << DDD4) #define PIN_DX_OUTPUT DDRD |= (1 << DDD4) #define PIN_DX_SET PORTD |= (1 << PD4) #define PIN_DX_CLEAR PORTD &= ~(1 << PD4) - // Blocking wait macros for AX synchronization + #define PIN_AX_INPUT DDRD &= ~(1 << DDD2) #define WAIT_AX_RISING (!(PIND & (1 << PIND2))) // Wait for pulse start (Blocking until Rising Edge) #define WAIT_AX_FALLING (PIND & (1 << PIND2)) // Wait for pulse end (Blocking until Falling Edge) #define PIN_AX_READ (!!(PIND & (1 << PIND2))) @@ -333,6 +332,7 @@ #define PIN_AX_INTERRUPT_DISABLE EIMSK &= ~(1<