From f7bf40ea6b7dfe2e11804dbc07a51da6bafc383d Mon Sep 17 00:00:00 2001 From: kalymos Date: Thu, 12 Feb 2026 18:49:02 +0100 Subject: [PATCH] refactor: optimize BIOS patching sequence with refined timing nomenclature Refined the BIOS patching and standardized timing nomenclature for better technical clarity. Changes: - Ad technical documentation within the code. - Standardized timing variables for better clarity: - BOOT_OFFSET: Replaces initial checkpoint. - FOLLOWUP_OFFSET: Replaces initial checkpoint2. - PULSE_COUNT: Replaces trigger . - BIT_OFFSET: Replaces hold . - OVERRIDE: Replaces patching. --- PSNee/BIOS_patching.h | 155 +++++++++++++++++++++++++----------------- PSNee/settings.h | 96 +++++++++++++------------- 2 files changed, 139 insertions(+), 112 deletions(-) diff --git a/PSNee/BIOS_patching.h b/PSNee/BIOS_patching.h index fb6ec27..a00d22e 100644 --- a/PSNee/BIOS_patching.h +++ b/PSNee/BIOS_patching.h @@ -3,44 +3,76 @@ #ifdef BIOS_PATCH - volatile uint8_t impulse = 0; - volatile uint8_t patch = 0; + volatile uint8_t pulse_counter = 0; + volatile uint8_t patch_done = 0; #ifdef INTERRUPT_RISING ISR(PIN_AX_INTERRUPT_VECTOR) { - impulse++; - if (impulse == TRIGGER){ // If impulse reaches the value defined by TRIGGER, the following actions are performed: - _delay_us(HOLD); - PIN_DX_OUTPUT; - _delay_us(PATCHING); + /* + * PHASE 3: Pulse Counting (Inside ISR) + * The hardware Interrupt Service Routine (ISR) now takes over. + * It counts the exact number of incoming pulses on PIN_AX until it + * matches the PULSE_COUNT value. + */ + pulse_counter++; + if (pulse_counter == PULSE_COUNT){ // If pulse_counter reaches the value defined by PULSE_COUNT + /* + * PHASE 4: Precision Bit Alignment + * Once the PULSE_COUNT is reached, a micro-delay (BIT_OFFSET) is applied. + * This shifts the timing from the clock edge to the exact bit position + * within the data stream that needs modification. + */ + _delay_us(BIT_OFFSET); + /* + * PHASE 5: Data Bus Overdrive (The Patch) + * Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit. + * This effectively overwrites the BIOS data on-the-fly + * before reverting the pin to INPUT to release the bus. + */ + PIN_DX_OUTPUT; + _delay_us (OVERRIDE); PIN_DX_INPUT; PIN_AX_INTERRUPT_DISABLE; - impulse = 0; - patch = 1; // patch is set to 1, indicating that the first patch is completed. + pulse_counter = 0; + patch_done = 1; // patch_done is set to 1, indicating that the first patch is completed. } } void Bios_Patching(){ + /* + * PHASE 1: Signal Stabilization & Alignment + * Detects the startup state (Cold Boot vs. Reset). + * If the line is already HIGH (Cold Boot), we wait for a full LOW-to-HIGH transition + * to ensure we are aligned with the start of a clean clock cycle. + */ - PIN_AX_INTERRUPT_RISING; - - if (PIN_AX_READ != 0) // If the AX pin is high + if (PIN_AX_READ != 0) // Case: Power-on / Line high (---__-_-_) { - while (PIN_AX_READ != 0); // Wait for it to go low - while (PIN_AX_READ == 0); // Then wait for it to go high again. + while (PIN_AX_READ != 0); // Wait for falling edge + while (PIN_AX_READ == 0); // Wait for next rising edge to sync } - else // If the AX pin is low + else // Case: Reset / Line low (_____-_-_) { - while (PIN_AX_READ == 0); // Wait for it to go high. + while (PIN_AX_READ == 0); // Wait for the very first rising edge } - // Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT. - _delay_ms(CHECKPOINT); + /* + * PHASE 2: Reaching the Target Memory Window + * We introduce a strategic delay (BOOT_OFFSET) to skip initial noise. + * This points the execution to a known idle gap in the + * address range calls before the critical data appears. + * DELAY: |---//-----| + * AX: -_-_//-_-_________-_-_-_ + */ + _delay_ms(BOOT_OFFSET); + + // Armed for hardware detection + PIN_AX_INTERRUPT_RISING; PIN_AX_INTERRUPT_ENABLE; - while (patch != 1); // Wait for the first stage of the patch to complete: + while (patch_done != 1); // Wait for the first stage of the patch to complete: } @@ -49,37 +81,37 @@ #ifdef INTERRUPT_FALLING ISR(PIN_AX_INTERRUPT_VECTOR) { - impulse++; - if (impulse == TRIGGER){ // If impulse reaches the value defined by TRIGGER, the following actions are performed: - _delay_us (HOLD); + pulse_counter++; + if (pulse_counter == PULSE_COUNT){ + _delay_us (BIT_OFFSET); PIN_DX_OUTPUT; - _delay_us (PATCHING); + _delay_us (OVERRIDE); PIN_DX_INPUT; PIN_AX_INTERRUPT_DISABLE; - impulse = 0; - patch = 1; // patch is set to 1, indicating that the first patch is completed. + pulse_counter = 0; + patch_done = 1; } } void Bios_Patching(){ - - PIN_AX_INTERRUPT_FALLING; - - if (PIN_AX_READ != 0) // If the AX pin is high + + if (PIN_AX_READ != 0) { - while (PIN_AX_READ != 0); // Wait for it to go low - while (PIN_AX_READ == 0); // Then wait for it to go high again. + while (PIN_AX_READ != 0); + while (PIN_AX_READ == 0); } - else // If the AX pin is low + else { - while (PIN_AX_READ == 0); // Wait for it to go high. + while (PIN_AX_READ == 0); } - _delay_ms(CHECKPOINT); // Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT. + _delay_ms(BOOT_OFFSET); / + + PIN_AX_INTERRUPT_FALLING; PIN_AX_INTERRUPT_ENABLE; - while (patch != 1); // Wait for the first stage of the patch to complete: + while (patch_done != 1); } #endif @@ -87,67 +119,62 @@ #ifdef INTERRUPT_RISING_HIGH_PATCH ISR(PIN_AX_INTERRUPT_VECTOR) { - impulse++; - if (impulse == TRIGGER){ // If impulse reaches the value defined by TRIGGER, the following actions are performed: - _delay_us (HOLD); + pulse_counter++; + if (pulse_counter == PULSE_COUNT){ + _delay_us (BIT_OFFSET); PIN_DX_SET; PIN_DX_OUTPUT; - _delay_us (PATCHING); + _delay_us (OVERRIDE); PIN_DX_CLEAR; PIN_DX_INPUT; PIN_AX_INTERRUPT_DISABLE; - impulse = 0; - patch = 1; // patch is set to 1, indicating that the first patch is completed. + pulse_counter = 0; + patch_done = 1; } } ISR(PIN_AY_INTERRUPT_VECTOR){ - impulse++; - if (impulse == TRIGGER2) // If impulse reaches the value defined by TRIGGER2, the following actions are performed: + pulse_counter++; + if (pulse_counter == PULSE_COUNT_2) { - _delay_us (HOLD2); + _delay_us (BIT_OFFSET_2); PIN_DX_OUTPUT; - _delay_us (PATCHING2); + _delay_us (OVERRIDE_2); PIN_DX_INPUT; PIN_AY_INTERRUPT_DISABLE; - patch = 2; // patch is set to 2, indicating that the second patch is completed. + patch_done = 2; } } void Bios_Patching(){ - PIN_AX_INTERRUPT_RISING; - - if (PIN_AX_READ != 0) // If the AX pin is high + if (PIN_AX_READ != 0) { - while (PIN_AX_READ != 0); // Wait for it to go low - while (PIN_AX_READ == 0); // Then wait for it to go high again. + while (PIN_AX_READ != 0); + while (PIN_AX_READ == 0); } - else // If the AX pin is low + else { - while (PIN_AX_READ == 0); // Wait for it to go high. + while (PIN_AX_READ == 0); } - _delay_ms(CHECKPOINT); // Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT. + _delay_ms(BOOT_OFFSET); + + PIN_AX_INTERRUPT_RISING; PIN_AX_INTERRUPT_ENABLE; - while (patch != 1); // Wait for the first stage of the patch to complete: + while (patch_done != 1); + while (PIN_AY_READ != 0); - #ifdef HIGH_PATCH - PIN_AY_INTERRUPT_FALLING; - #else - PIN_AY_INTERRUPT_RISING; - #endif - - while (PIN_AY_READ != 0); // Wait for it to go low + _delay_ms(FOLLOWUP_OFFSET); - _delay_ms(CHECKPOINT2); // Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT2. + PIN_AY_INTERRUPT_RISING; PIN_AY_INTERRUPT_ENABLE; - while (patch != 2); // Wait for the second stage of the patch to complete: + while (patch_done != 2); } diff --git a/PSNee/settings.h b/PSNee/settings.h index 7f48b1a..3f5e3e4 100644 --- a/PSNee/settings.h +++ b/PSNee/settings.h @@ -11,8 +11,8 @@ 1 clock cycle = 1 / 16,000,000 s ≈ 62.5 ns 1 µs ≈ 16 clock cycles - HOLD _delay_us(2.75) = 44 clock cycles - PATCHING _delay_us(0.2) = 3,2 clock cycles + BIT_OFFSET _delay_us(2.75) = 44 clock cycles + OVERRIDE _delay_us(0.2) = 3,2 clock cycles */ @@ -27,93 +27,93 @@ #ifdef SCPH_102 #define BIOS_PATCH #define INTERRUPT_RISING -#define CHECKPOINT 83.9 -#define TRIGGER 48 -#define HOLD 2.75 -#define PATCHING 0.2 +#define BOOT_OFFSET 83.9 +#define PULSE_COUNT 48 +#define BIT_OFFSET 2.75 +#define OVERRIDE 0.2 #endif #ifdef SCPH_100 #define BIOS_PATCH #define INTERRUPT_RISING -#define CHECKPOINT 83.9 //83.72 - 84.15 -#define TRIGGER 48 -#define HOLD 2.75 //2.63 - 2.87 -#define PATCHING 0.2 +#define BOOT_OFFSET 83.9 //83.72 - 84.15 +#define PULSE_COUNT 48 +#define BIT_OFFSET 2.75 //2.63 - 2.87 +#define OVERRIDE 0.2 #endif #ifdef SCPH_7500_9000 #define BIOS_PATCH #define INTERRUPT_RISING -#define CHECKPOINT 75.2 //74.95 - 75.55 -#define TRIGGER 16 -#define HOLD 2.8 -#define PATCHING 0.2 +#define BOOT_OFFSET 75.2 //74.95 - 75.55 +#define PULSE_COUNT 16 +#define BIT_OFFSET 2.8 +#define OVERRIDE 0.2 #endif #ifdef SCPH_7000 //#define PATCH_SWITCH #define BIOS_PATCH #define INTERRUPT_RISING -#define CHECKPOINT 75.2 //75.3 -#define TRIGGER 16 -#define HOLD 2.8 -#define PATCHING 0.2 +#define BOOT_OFFSET 75.2 //75.3 +#define PULSE_COUNT 16 +#define BIT_OFFSET 2.8 +#define OVERRIDE 0.2 #endif #ifdef SCPH_5500 #define BIOS_PATCH #define INTERRUPT_FALLING -#define CHECKPOINT 76.07 //75.99 - 76.14 -#define TRIGGER 21 -#define HOLD 2.8 -#define PATCHING 0.2 +#define BOOT_OFFSET 76.07 //75.99 - 76.14 +#define PULSE_COUNT 21 +#define BIT_OFFSET 2.8 +#define OVERRIDE 0.2 #endif #ifdef SCPH_5000 #define BIOS_PATCH #define INTERRUPT_FALLING -#define CHECKPOINT 75.2 //75.12 - 75.27 -#define TRIGGER 21 -#define HOLD 2.8 //2.7 - 2.85 -#define PATCHING 0.1 +#define BOOT_OFFSET 75.2 //75.12 - 75.27 +#define PULSE_COUNT 21 +#define BIT_OFFSET 2.8 //2.7 - 2.85 +#define OVERRIDE 0.1 #endif #ifdef SCPH_3500 #define BIOS_PATCH #define INTERRUPT_FALLING -#define CHECKPOINT 75.2 //75.12 - 75.27 -#define TRIGGER 21 -#define HOLD 2.75 //2.65 - 2.85 -#define PATCHING 0.2 +#define BOOT_OFFSET 75.2 //75.12 - 75.27 +#define PULSE_COUNT 21 +#define BIT_OFFSET 2.75 //2.65 - 2.85 +#define OVERRIDE 0.2 #endif #ifdef SCPH_3000 #define BIOS_PATCH -#define CHECKPOINT 82.9 //82.65 - 83.26 -#define TRIGGER 60 -#define HOLD 2.7 //2.58 - 2.8 -#define PATCHING 0.15 -#define HIGH_PATCH #define INTERRUPT_RISING_HIGH_PATCH -#define CHECKPOINT2 253.3 -#define TRIGGER2 43 -#define HOLD2 2.88 -#define PATCHING2 0.15 +#define BOOT_OFFSET 82.9 //82.65 - 83.26 +#define PULSE_COUNT 60 +#define BIT_OFFSET 2.7 //2.58 - 2.8 +#define OVERRIDE 0.15 +#define HIGH_PATCH +#define FOLLOWUP_OFFSET 253.3 +#define PULSE_COUNT_2 43 +#define BIT_OFFSET_2 2.88 +#define OVERRIDE_2 0.15 #endif #ifdef SCPH_1000 #define BIOS_PATCH -#define CHECKPOINT 82.9 // 82.63 - 83.26 -#define TRIGGER 92 -#define HOLD 2.65 // 2.58 - 2.75 -#define PATCHING 0.15 -#define HIGH_PATCH #define INTERRUPT_RISING_HIGH_PATCH -#define CHECKPOINT2 272.8 -#define TRIGGER2 71 -#define HOLD2 2.88 -#define PATCHING2 0.15 +#define BOOT_OFFSET 82.9 // 82.63 - 83.26 +#define PULSE_COUNT 92 +#define BIT_OFFSET 2.65 // 2.58 - 2.75 +#define OVERRIDE 0.15 +#define HIGH_PATCH +#define FOLLOWUP_OFFSET 272.8 +#define PULSE_COUNT_2 71 +#define BIT_OFFSET_2 2.88 +#define OVERRIDE_2 0.15 #endif /*------------------------------------------------------------------------------------------------