mirror of
https://github.com/kalymos/PsNee.git
synced 2026-05-11 09:20:12 +00:00
0ff2612c7c
- Board Detection: Added 300ms stabilization delay to filter PU-7/20 power-up noise and sync with PU-22+ oscillating signals. - Injection: Added conditional break to allow single-region selection and updated WFCK modulation for 7.3/14.6 kHz compatibility. - Logic: Optimized sector filtering using bitmask (0xD0) and improved hysteresis tracking for Standard and SCPH-5903 models. - Code Quality: Standardized nomenclature (subqBuffer, hysteresis, pulseCounter) and added comprehensive English documentation. - Performance: Reduced binary size by optimizing loops and variable types.
299 lines
9.9 KiB
C
299 lines
9.9 KiB
C
#pragma once
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#ifdef BIOS_PATCH
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volatile uint8_t pulseCounter = 0;
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volatile uint8_t patchStep = 0;
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#ifdef INTERRUPT_RISING
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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/*
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* PHASE 3: Pulse Counting (Inside ISR)
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* The hardware Interrupt Service Routine (ISR) now takes over.
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* It counts the exact number of incoming pulses on PIN_AX until it
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* matches the PULSE_COUNT value.
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*/
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//if (--pulseCounter == 0) {
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pulseCounter++;
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if (pulseCounter == PULSE_COUNT){ // If pulseCounter reaches the value defined by PULSE_COUNT
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/*
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* PHASE 4: Precision Bit Alignment
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* Once the PULSE_COUNT is reached, a micro-delay (BIT_OFFSET) is applied.
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* This shifts the timing from the clock edge to the exact bit position
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* within the data stream that needs modification.
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*/
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_delay_us(BIT_OFFSET);
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/*
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* PHASE 5: Data Bus Overdrive (The Patch)
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* Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit.
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* This effectively overwrites the BIOS data on-the-fly
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* before reverting the pin to INPUT to release the bus.
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*/
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE);
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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pulseCounter = 0;
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patchStep = 1; // patchStep is set to 1, indicating that the first patch is completed.
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}
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}
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void Bios_Patching(){
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/*
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* PHASE 1: Signal Stabilization & Alignment
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* Detects the startup state (Cold Boot vs. Reset).
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* If the line is already HIGH (Cold Boot), we wait for a full LOW-to-HIGH transition
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* to ensure we are aligned with the start of a clean clock cycle.
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*/
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if (PIN_AX_READ != 0) { // Case: Power-on / Line high (---__-_-_)
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while (PIN_AX_READ != 0); // Wait for falling edge
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while (PIN_AX_READ == 0); // Wait for next rising edge to sync
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}
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else { // Case: Reset / Line low (_____-_-_)
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while (PIN_AX_READ == 0); // Wait for the very first rising edge
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}
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/*
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* PHASE 2: Reaching the Target Memory Window
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* We introduce a strategic delay (BOOT_OFFSET) to skip initial noise.
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* This points the execution to a known idle gap in the
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* address range calls before the critical data appears.
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* DELAY: |---//-----|
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* AX: -_-_//-_-_________-_-_-_
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*/
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_delay_ms(BOOT_OFFSET);
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// Armed for hardware detection
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//pulseCounter = PULSE_COUNT;
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PIN_AX_INTERRUPT_RISING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patchStep != 1); // Wait for the first stage of the patch to complete:
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}
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#endif
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#ifdef INTERRUPT_FALLING
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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pulseCounter++;
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if (pulseCounter == PULSE_COUNT){
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_delay_us (BIT_OFFSET);
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE);
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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pulseCounter = 0;
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patchStep = 1;
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}
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}
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void Bios_Patching(){
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if (PIN_AX_READ != 0) {
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while (PIN_AX_READ != 0);
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while (PIN_AX_READ == 0);
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}
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else {
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while (PIN_AX_READ == 0);
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}
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_delay_ms(BOOT_OFFSET);
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PIN_AX_INTERRUPT_FALLING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patchStep != 1);
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}
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#endif
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#ifdef INTERRUPT_RISING_HIGH_PATCH
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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pulseCounter++;
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if (pulseCounter == PULSE_COUNT){
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_delay_us (BIT_OFFSET);
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PIN_DX_SET;
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE);
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PIN_DX_CLEAR;
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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pulseCounter = 0;
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patchStep = 1;
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}
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}
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ISR(PIN_AY_INTERRUPT_VECTOR){
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pulseCounter++;
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if (pulseCounter == PULSE_COUNT_2) {
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_delay_us (BIT_OFFSET_2);
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE_2);
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PIN_DX_INPUT;
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PIN_AY_INTERRUPT_DISABLE;
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patchStep = 2;
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}
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}
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void Bios_Patching(){
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if (PIN_AX_READ != 0) {
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while (PIN_AX_READ != 0);
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while (PIN_AX_READ == 0);
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}
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else {
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while (PIN_AX_READ == 0);
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}
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_delay_ms(BOOT_OFFSET);
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PIN_AX_INTERRUPT_RISING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patchStep != 1);
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while (PIN_AY_READ != 0);
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_delay_ms(FOLLOWUP_OFFSET);
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PIN_AY_INTERRUPT_RISING;
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PIN_AY_INTERRUPT_ENABLE;
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while (patchStep != 2);
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}
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#endif
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#endif
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/*
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* ======================================================================================
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* FUNCTION : Bios_Patching()
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* TARGET : Data Bus (DX) synchronized via Address Bus (AX / AY)
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*
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* OPERATIONAL LOGIC:
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* This function intercepts a specific memory transaction by counting clock cycles
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* on Address lines (AX/AY) to inject modified data onto the Data line (DX)
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* in real-time (On-the-fly patching).
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*
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* KEY PHASES:
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* 1. SYNC (AX): Aligns the CPU with the first valid address cycle after boot/reset
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* to establish a deterministic T0 reference point.
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* 2. GATING (BOOT_OFFSET): Skips initial BIOS noise/calls to reach the target
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* memory window.
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* 3. ADDRESS COUNTING (ISR AX): Hardware-based pulse counting using ultra-fast
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* decrement-to-zero logic to identify the exact target bit location.
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* 4. DATA OVERDRIVE (DX): Momentarily forces DX pin to OUTPUT mode to overwrite
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* the original BIOS bit with a custom logic state.
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* 5. SEQUENCING (Optional AY): Transitions to a secondary address line (AY) for
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* multi-stage patching or follow-up verification.
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* ======================================================================================
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*/
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#ifdef BIOS_PATCH_2
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volatile uint8_t pulseCounter = 0;
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volatile uint8_t patchStep = 0;
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// --- MAIN INTERRUPT SERVICE ROUTINE (ADDRESS AX) ---
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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/*
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* PHASE 3: Pulse Counting (Inside ISR)
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* Decrementing towards zero is the fastest operation on AVR architecture.
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*/
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if (--pulseCounter == 0) {
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/* PHASE 4: Precision Bit Alignment */
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_delay_us(BIT_OFFSET);
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/* PHASE 5: Data Bus Overdrive (The Patch on DX) */
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#ifdef INTERRUPT_RISING_HIGH_PATCH
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PIN_DX_SET; // Pre-set HIGH state for Variant 3
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#endif
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PIN_DX_OUTPUT; // Take control of the Data Bus
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_delay_us(OVERRIDE);
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#ifdef INTERRUPT_RISING_HIGH_PATCH
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PIN_DX_CLEAR; // Release HIGH state
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#endif
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PIN_DX_INPUT; // Immediately release the Data Bus
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PIN_AX_INTERRUPT_DISABLE;
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patchStep = 1; // Notify Stage 1 completion
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}
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}
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// --- SECONDARY INTERRUPT SERVICE ROUTINE (ADDRESS AY - Variant 3) ---
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#ifdef INTERRUPT_RISING_HIGH_PATCH
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ISR(PIN_AY_INTERRUPT_VECTOR) {
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if (--pulseCounter == 0) {
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_delay_us(BIT_OFFSET_2);
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PIN_DX_OUTPUT;
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_delay_us(OVERRIDE_2);
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PIN_DX_INPUT;
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PIN_AY_INTERRUPT_DISABLE;
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patchStep = 2; // Notify Stage 2 completion
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}
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}
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#endif
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void Bios_Patching() {
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/*
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* PHASE 1: Signal Stabilization & Alignment (AX)
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* Handles Cold Boot (Line High) vs Reset (Line Low) states.
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*/
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if (PIN_AX_READ != 0) { // Case: Power-on / Line high
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while (PIN_AX_READ != 0); // Wait for falling edge
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while (PIN_AX_READ == 0); // Wait for next rising edge to sync
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}
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else { // Case: Reset / Line low
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while (PIN_AX_READ == 0); // Wait for the very first rising edge
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}
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/* PHASE 2: Reaching the Target Memory Window */
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_delay_ms(BOOT_OFFSET);
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// Countdown Preparation (Optimized for speed)
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pulseCounter = PULSE_COUNT;
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patchStep = 0;
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// Dynamic Interrupt Configuration
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#if defined(INTERRUPT_RISING) || defined(INTERRUPT_RISING_HIGH_PATCH)
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PIN_AX_INTERRUPT_RISING;
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#elif defined(INTERRUPT_FALLING)
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PIN_AX_INTERRUPT_FALLING;
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#endif
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// Arm Hardware Interrupt
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PIN_AX_INTERRUPT_ENABLE;
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while (patchStep != 1); // Block until first patch is applied
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/*
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* OPTIONAL PHASE: Secondary Patch (Variant 3 only)
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* Switches detection to the second Address line (AY).
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*/
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#ifdef INTERRUPT_RISING_HIGH_PATCH
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while (PIN_AY_READ != 0); // Ensure AY is low before arming
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_delay_ms(FOLLOWUP_OFFSET);
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pulseCounter = PULSE_COUNT_2; // Re-load counter for AY pulses
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PIN_AY_INTERRUPT_RISING;
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PIN_AY_INTERRUPT_ENABLE;
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while (patchStep != 2); // Block until second patch is applied
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#endif
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}
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#endif
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