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10a054d60c
Re-implemented Hardware ISR (INT0/INT1): Restored interrupt-driven pulse counting to eliminate polling jitter. Tests confirmed that at 16MHz, software polling is too inconsistent for reliable DATA OVERDRIVE synchronization. Mechanism Freeze: The core logic (Stabilization -> Silence Detection -> ISR Counting -> Injection) is now finalized and stable. Portability Note: Maintained a clean structure to allow future non-ISR porting, although the ISR version remains the mandatory standard for ATmega328P @ 16MHz performance.