mirror of
https://github.com/kalymos/PsNee.git
synced 2026-05-07 08:06:39 +00:00
* MUC-MCU Fixed the MUC-MCU file name. Fixed a bug that prevented additional MCUs from being compiled. Modified the clock registers for ATtiny 48-88s; the TCCROB register is missing in these MUCs. * Too many things to summarize Refactoring of the setting file, to be able to have settings specifying the HYSTERESIS_MAX variable. Renamed precompilation variable in BIOS_patching file. Changing console selection in .ino file * Renaming files to make updating easier * Update README.md * logo 8.7 * optimization on regin injection * Ad bios patch 102A, and correct some images. * SCPH_102A bios patch WIP * Cleaning the selection area Redesign of the selection area, and addition of the SCPH_hyma mode equivalent to the legacy mode with the difference of a hysteresis of 25 * Layout modification * clining * ad debug mode * debug mesga * creation of debug functions, and cleaning * Update PSNee.ino * serial debug cleaning * added compilation message * some comment cleaning * removal of the TIMER removal of the ISR(CTC_TIMER_VECTOR) function, and all its dependencies. - Timer_Start - Timer_Stop modification - Board detection - inject_SCEX - BIOS_PATCH - MCU - Setting * Update PSNee.ino Implementing a dedicated board_detection function with optimized logic. Remodeling the inject_SCEX function. * timer optimization * Breaking down the main function into smaller modules. Modular breakdown: Separated main logic into - captureSubQ, - logic_SCPH_5903, - logic_Standard, - performInjectionSequence. Added support for SCPH-5903 by RepairBox Co-Authored-By: RepairBox <33960601+danielfergisz@users.noreply.github.com> * Optimization performInjectionSequence(): Deep refactor with a cleaner. captureSubQ(): Faster bit-banging and improved timing accuracy. board_detection(): Optimized logic . General Cleanup: Fixed all warnings and minimized memory footprint. * Optimization Optimization of the performInjectionSequence function BIOS patch verification (work in progress) and general code cleanup * BIOS patch obtimisation * opti patch bios 3500 * opti bios patch SCPH-1000 * opti BIOS patch SCPH-3000, SCPH-100. * refactor: optimize BIOS patching sequence with refined timing nomenclature Refined the BIOS patching and standardized timing nomenclature for better technical clarity. Changes: - Ad technical documentation within the code. - Standardized timing variables for better clarity: - BOOT_OFFSET: Replaces initial checkpoint. - FOLLOWUP_OFFSET: Replaces initial checkpoint2. - PULSE_COUNT: Replaces trigger . - BIT_OFFSET: Replaces hold . - OVERRIDE: Replaces patching. * test refactor: optimize PS1 patch for SCPH-100 using zero-latency polling Ported the BIOS patch from ISR to manual polling to achieve cycle-accurate precision for 33.86MHz bus timing. * test neo BIOS patch * Refactor pulse counting logic for jitter reduction * BIOS patch simplification Removal of ISR and reduction of code in the BIOS patch, for improved portability and robustness. For now it is only available for the SCPH-100 and 102. * BIOS patche neo for SCPH-9000_7500 SCPH-7000 SCPH-5500 * BIOS patch neo SCPH-5000 SCPH-3500 * BIOS patche neo SCPH-3000 SCPH-1000 I finally completed the value conversion for the BIOS patch without IRS * refactor: optimize core detection and injection logic for performance and size - board_detection: Added early exit for newer boards and tightened the sampling loop to reduce CPU overhead. - captureSubQ: Simplified clock-edge synchronization and localized buffers to improve register allocation. - performInjectionSequence: Replaced bit-calculation math with a streamlined byte-shift approach. Refined WFCK modulation to ensure zero-jitter phase locking. - logic_Standard/5903: Refactored pattern matching into a decision tree. Factorized redundant buffer checks (scbuf[1]/[6]) and replaced multiple equality tests with range comparisons. Optimization results: - Reduced Flash memory footprint (smaller binary size). - Improved execution speed by removing redundant logical operations. - Increased signal stability during the critical injection phase. * PSNee v9.0 Update New PSNeeCore v2: Completely rewritten core engine for all supported MCUs. Auto-MCU Detection: Manual board selection removed. Automatically detects ATmega (328/168/128/PB), 32U4, and ATtiny families at compile time. Deep Init Optimization: Hard-shutdown of unused internal modules (ADC, DAC, Timers) to minimize power draw and electrical noise. Native PB Support: Full compatibility for 128PB and 328PB (PRR2 registers and extra Ports). * PSNee v9.0 Update New PSNeeCore v2: Completely rewritten core engine for all supported MCUs. Auto-MCU Detection: Manual board selection removed. Automatically detects ATmega (328/168/128/PB), 32U4, and ATtiny families at compile time. Deep Init Optimization: Hard-shutdown of unused internal modules (ADC, DAC, Timers) to minimize power draw and electrical noise. Native PB Support: Full compatibility for 128PB and 328PB (PRR2 registers and extra Ports). logo --------- Co-authored-by: RepairBox <33960601+danielfergisz@users.noreply.github.com>