VGA Project Status
Project File: | vga.ise | Current State: | Programming File Generated

Module Name:

fpga

- Errors:

No Errors

Target Device:

xc2s200-5fg256

- Warnings:

29 Warnings

Product Version:

ISE 8.2i

- Updated:

Mon Jan 1 22:23:05 2007

VGA Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization | Used | Available | Utilization | Note(s)
Total Number Slice Registers | 174 | 4,704 | 3% |
Number used as Flip Flops | 173 |  |  |
Number used as Latches | 1 |  |  |
Number of 4 input LUTs | 688 | 4,704 | 14% |
Logic Distribution |  |  |  |
Number of occupied Slices | 402 | 2,352 | 17% |
Number of Slices containing only related logic | 402 | 402 | 100% |
Number of Slices containing unrelated logic | 0 | 402 | 0% |
Total Number 4 input LUTs | 716 | 4,704 | 15% |
Number used as logic | 688 |  |  |
Number used as a route-thru | 28 |  |  |
Number of bonded IOBs | 22 | 176 | 12% |
IOB Flip Flops | 2 |  |  |
Number of Block RAMs | 7 | 14 | 50% |
Number of GCLKs | 3 | 4 | 75% |
Number of GCLKIOBs | 1 | 4 | 25% |
Total equivalent gate count for design | 120,964 |  |  |
Additional JTAG gate count for IOBs | 1,104 |  |  |

Performance Summary
Final Timing Score: | 0 | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Mon Jan 1 22:21:50 2007 | 0 | 21 Warnings | 6 Infos
Translation Report | Current | Mon Jan 1 22:22:03 2007 | 0 | 0 | 7 Infos
Map Report | Current | Mon Jan 1 22:22:16 2007 | 0 | 7 Warnings | 2 Infos
Place and Route Report | Current | Mon Jan 1 22:22:44 2007 | 0 | 0 | 2 Infos
Static Timing Report | Current | Mon Jan 1 22:22:52 2007 | 0 | 0 | 2 Infos
Bitgen Report | Current | Mon Jan 1 22:23:05 2007 | 0 | 1 Warning | 0

Secondary Reports
Report Name | Status | Generated
Xplorer Report |  |