DEC-8I-H8NA-D	KT8/I Time-Sharing Option Functional Description
DEC-8I-HOCA-D	KE8/I Extended Arithmetic Element

interrupt occurs here

 510 00516 7141 	CLL CIA
 511 00517 1155 	TAD LASTV
 512 00520 7630 	SZL CLA
 513 00521 4526 	ERROR		/STORAGE FILLED BY PUSHDOWN LIST


6000 PWS The contents of the AC register are loaded into the SW
register. This instruction performs no operation if the IM
flag is 1.

6001 ION The IE flag is set to 1, enabling interrupts, after a one
instruction delay.

6002 IOF The IE flag is set to 0, disabling interrupts.

6003 PSI Skip if the IE flag is 1. This instruction performs no
operation if the IM flag is 1.

6004 PAI The contents of the IB register are loaded into the IF
register, and the II flag is set to 0, just as if a JMP or
JMS was executed when the IM flag is 1. This instruction
performs no operation if the IM flag is 1.

6005 PAS The contents of the DF register are loaded into bits
[03..05] of the SF register, and the contents of the IF
register are loaded into bits [00..02] of the SF register,
just as they would be loaded on an interrupt. This
instruction performs no operation of the IM flag is 1.

6006 PDX The DM flag is set to 1 for the execution of the next
instruction. This instruction executes normally if IM is 1,
but since DM is 1 anytime IM is 1, it effectively performs
no operation.

6007 PEX The IM flag is set to 1, switching the CPU into normal mode,
after a one instruction delay. This instruction executes
notmally if IM is 1, but effectively performs no operation.

62x1 CDF Bits [06..08] of the instruction are loaded into the DF
register.
62x2 CIF Bits [06..08] of the instruction are loaded into the IB
register, and the II flag is set to 1. The contents of the
IB register will be loaded into the IF register, and the II
flag will be set to 0, when the next JMP or JMS instruction
is executed. The reload happens after any instruction and/or
indirect address words are read, but before the JMS writes
its return address; the return address is written to the new
instruction field. The II flag blocks interrupts between the
CIF and the JMP/JMS (page 53 of the 1970 small computer
handbook describes the effect of the II flag, even though
the flag itself is not described clearly).

6214 RDF The contents of the DF register are logically ORed into
bits [06..08] of the AC register.

6224 RIF The contents of the IF register are logically ORed into
bits [06..08] of the AC register.

6234 RIB The contents of the SF register are logically ORed into
bits [06..11] of the AC register; if the AC register is
initially 0, then bits [09..11] of the AC register get the
value which was in the DF register at the time of the last
interrupt, and bits [06..08] of the AC register get the
value which was in the IF register at the time of the last
interrupt.

6244 RMF Bits [03..05] of the SF register are loaded into the DF
register, bits [00..02] of the SF register are loaded into
the IB register, and the II flag is set to 1. The next JMP
or JMS instruction completes the restore.
