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fixed bug in tt tx state machine not asserting interrupt

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This commit is contained in:
brad 2010-10-23 23:24:52 +00:00
parent 3d425fe732
commit 0622c1c3a8
12 changed files with 304 additions and 115 deletions
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53
rtl/bootrom.v
View File

@ -2,8 +2,11 @@
// boot rom occupies one page from 7400 - 7577
//
`define bootrom_tss8
//`define bootrom_uart
//`define bootrom_uart 1
`ifndef bootrom_uart
`define bootrom_tss8 1
`endif
module bootrom(clk, reset, addr, data_out, rd, selected);
@ -28,7 +31,7 @@ module bootrom(clk, reset, addr, data_out, rd, selected);
delay <= delay - 3'o1;
assign active = delay != 3'b000;
assign selected = active && (addr >= 12'o7400 && addr <= 12'o7577);
assign selected = active && (addr >= 15'o07400 && addr <= 15'o07577);
assign data_out = data;
@ -46,30 +49,30 @@ module bootrom(clk, reset, addr, data_out, rd, selected);
case (addr)
// copy tss8 bootstrap to ram and jump to it
// (see ../rom/rom.pal)
12'o7400: data = 12'o7240;
12'o7401: data = 12'o1224;
12'o7402: data = 12'o3010;
12'o7403: data = 12'o1217;
12'o7404: data = 12'o3410;
12'o7405: data = 12'o1220;
12'o7406: data = 12'o3410;
12'o7407: data = 12'o1221;
12'o7410: data = 12'o3410;
12'o7411: data = 12'o1222;
12'o7412: data = 12'o3410;
12'o7413: data = 12'o1223;
12'o7414: data = 12'o3410;
12'o7415: data = 12'o7300;
12'o7416: data = 12'o5624;
12'o7417: data = 12'o7600;
12'o7420: data = 12'o6603;
12'o7421: data = 12'o6622;
12'o7422: data = 12'o5352;
12'o7423: data = 12'o5752;
12'o7424: data = 12'o7750;
15'o7400: data = 12'o7240;
15'o7401: data = 12'o1224;
15'o7402: data = 12'o3010;
15'o7403: data = 12'o1217;
15'o7404: data = 12'o3410;
15'o7405: data = 12'o1220;
15'o7406: data = 12'o3410;
15'o7407: data = 12'o1221;
15'o7410: data = 12'o3410;
15'o7411: data = 12'o1222;
15'o7412: data = 12'o3410;
15'o7413: data = 12'o1223;
15'o7414: data = 12'o3410;
15'o7415: data = 12'o7300;
15'o7416: data = 12'o5624;
15'o7417: data = 12'o7600;
15'o7420: data = 12'o6603;
15'o7421: data = 12'o6622;
15'o7422: data = 12'o5352;
15'o7423: data = 12'o5752;
15'o7424: data = 12'o7750;
endcase // case(addr)
if (rd && active && addr == 12'o7416)
if (rd && active && addr == 15'o07416)
deactivate = 1;
`endif
`ifdef bootrom_uart

13
rtl/ide.v
View File

@ -4,7 +4,7 @@
//
module ide(clk, reset, ata_rd, ata_wr, ata_addr, ata_in, ata_out, ata_done,
ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
ide_data_in, ide_data_out, ide_dior, ide_diow, ide_cs, ide_da);
input clk;
input reset;
@ -17,7 +17,8 @@ module ide(clk, reset, ata_rd, ata_wr, ata_addr, ata_in, ata_out, ata_done,
reg [15:0] ata_out;
output ata_done;
inout [15:0] ide_data_bus;
input [15:0] ide_data_in;
output [15:0] ide_data_out;
output ide_dior;
output ide_diow;
output [1:0] ide_cs;
@ -41,10 +42,10 @@ module ide(clk, reset, ata_rd, ata_wr, ata_addr, ata_in, ata_out, ata_done,
// if write, drive ide_bus
assign ide_data_bus = (ata_wr && (ata_state == s0 ||
assign ide_data_out = (ata_wr && (ata_state == s0 ||
ata_state == s1 ||
ata_state == s2 ||
ata_state == s3)) ? ata_in : 16'bz;
ata_state == s3)) ? ata_in : 16'b0;
// assert cs & da during r/w cycle
assign assert_cs = (ata_rd || ata_wr) && ata_state != s4;
@ -69,7 +70,7 @@ module ide(clk, reset, ata_rd, ata_wr, ata_addr, ata_in, ata_out, ata_done,
else
ata_state <= ata_state_next;
always @(clk or ata_state or ata_rd or ata_wr or ata_addr or ide_data_bus)
always @(clk or ata_state or ata_rd or ata_wr or ata_addr)
begin
case (ata_state)
idle:
@ -94,6 +95,6 @@ module ide(clk, reset, ata_rd, ata_wr, ata_addr, ata_in, ata_out, ata_done,
ata_out <= 0;
else
if (ata_state == s2 && ata_rd)
ata_out <= ide_data_bus;
ata_out <= ide_data_in;
endmodule // ide

62
rtl/ide_disk.v
View File

@ -8,7 +8,7 @@ module ide_disk(clk, reset,
ide_error, ide_done,
buffer_addr, buffer_rd, buffer_wr,
buffer_in, buffer_out,
ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
ide_data_in, ide_data_out, ide_dior, ide_diow, ide_cs, ide_da);
input clk;
input reset;
@ -82,7 +82,8 @@ module ide_disk(clk, reset,
wire [15:0] ata_out;
wire ata_done;
inout [15:0] ide_data_bus;
input [15:0] ide_data_in;
output [15:0] ide_data_out;
output ide_dior;
output ide_diow;
output [1:0] ide_cs;
@ -105,12 +106,12 @@ module ide_disk(clk, reset,
reg grab_buffer_in;
//
ide ide1(.clk(clk), .reset(reset),
.ata_rd(ata_rd), .ata_wr(ata_wr), .ata_addr(ata_addr),
.ata_in(ata_in), .ata_out(ata_out), .ata_done(ata_done),
.ide_data_bus(ide_data_bus),
.ide_dior(ide_dior), .ide_diow(ide_diow),
.ide_cs(ide_cs), .ide_da(ide_da));
ide ide(.clk(clk), .reset(reset),
.ata_rd(ata_rd), .ata_wr(ata_wr), .ata_addr(ata_addr),
.ata_in(ata_in), .ata_out(ata_out), .ata_done(ata_done),
.ide_data_in(ide_data_in), .ide_data_out(ide_data_out),
.ide_dior(ide_dior), .ide_diow(ide_diow),
.ide_cs(ide_cs), .ide_da(ide_da));
//
wire [23:0] lba;
@ -152,7 +153,12 @@ module ide_disk(clk, reset,
end
if (grab_buffer_in)
buffer_in_hold <= buffer_in;
begin
`ifdef debug
$display("ide_disk: grabbing buffer_in %o", buffer_in);
`endif
buffer_in_hold <= buffer_in;
end
end
//
@ -286,7 +292,7 @@ module ide_disk(clk, reset,
begin
ata_wr = 1;
ata_addr = ATA_CYLHIGH;
ata_in = lba[23:16]; // LBA[23:16]
ata_in = {8'b0, lba[23:16]}; // LBA[23:16]
if (ata_done)
ide_state_next = init8;
end
@ -379,7 +385,7 @@ module ide_disk(clk, reset,
//buffer read
buffer_addr = offset;
buffer_rd = 1;
grab_buffer_in = 1;
// grab_buffer_in = 1;
ata_in = {4'b0, buffer_in};
inc_offset = 1;
@ -388,10 +394,11 @@ module ide_disk(clk, reset,
write1:
begin
grab_buffer_in = 1;
ata_wr = 1;
ata_addr = ATA_DATA;
ata_in = {4'b0, buffer_in_hold};
//$display("ide_disk: write1, %o", buffer_in_hold);
$display("ide_disk: write1, %o", buffer_in_hold);
if (ata_done)
begin
@ -440,6 +447,37 @@ module ide_disk(clk, reset,
endcase
end
`ifdef debug_ide_state
always @(posedge clk)
/* verilator lint_off CASEINCOMPLETE */
case (ide_state)
ready: $display("ide_state: ready");
init0: $display("ide_state: init");
init1: $display("ide_state: init1");
init2: $display("ide_state: init2");
init3: $display("ide_state: init3");
init4: $display("ide_state: init4");
init5: $display("ide_state: init5");
init6: $display("ide_state: init6");
init7: $display("ide_state: init7");
init8: $display("ide_state: init8");
init9: $display("ide_state: init9");
init10: $display("ide_state: init10");
init11: $display("ide_state: init11");
read0: $display("ide_state: read0");
read1: $display("ide_state: read1");
write0: $display("ide_state: write0");
write1: $display("ide_state: write1");
last0: $display("ide_state: last0");
last1: $display("ide_state: last1");
last2: $display("ide_state: last2");
last3: $display("ide_state: last3");
wait0: $display("ide_state: wait0");
wait1: $display("ide_state: wait1");
endcase
/* verilator lint_on CASEINCOMPLETE */
`endif
endmodule

44
rtl/pdp8.v
View File

@ -432,9 +432,9 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
assign pc_mux = (state == F1 && pc_skip) ? (pc + 12'd2) :
(state == F1 && pc_incr) ? (pc + 12'd1) :
(state == F3 && !(opr || iot) && (!mb[8] & jmp)) ? ma :
(state == F3 && !(opr || iot) && (!mb[8] & jmp)) ? ma[11:0] :
(state == D3 && jmp) ? mb :
(state == E3 && jms) ? ma :
(state == E3 && jms) ? ma[11:0] :
(state == E3 && isz && mb == 12'b0) ? (pc + 12'd1) :
pc;
@ -551,6 +551,7 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
interrupt_skip = 0;
/* verilator lint_off CASEINCOMPLETE */
case (state)
F1:
begin
@ -567,7 +568,8 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
if (iot && ~UF)
begin
casex (io_select)
/* verilator lint_off CASEINCOMPLETE */
casez (io_select)
6'b000000: // ION, IOF
case (mb[2:0])
// 3'b001:
@ -577,7 +579,7 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
interrupt_skip = 1;
endcase
6'b010xxx: // CDF..RMF
6'b010???: // CDF..RMF
begin
// if (mb[1])
// begin // CIF
@ -616,11 +618,13 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
end
endcase // casex(io_select)
/* verilator lint_on CASEINCOMPLETE */
end // if (iot && ~UF)
end
endcase
/* verilator lint_on CASEINCOMPLETE */
end
@ -664,7 +668,7 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
if (interrupt && interrupt_enable &&
!interrupt_inhibit && !interrupt_cycle)
begin
if (0)
if (1)
$display("xxx interrupt, pc %o; %b %b %b; %b %b",
pc,
interrupt, interrupt_enable, interrupt_cycle,
@ -689,7 +693,7 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
interrupt_cycle <= 0;
if (0)
$display("read ram [%o] -> %o", ram_addr, ram_data_in);
$display("cpu: read ram [%o] -> %o", ram_addr, ram_data_in);
mb <= ram_data_in;
ir <= ram_data_in[11:9];
@ -723,16 +727,18 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
end
if (opr)
casex ({mb[8],mb[0]})
2'b0x: // group 1
case ({mb[8],mb[0]})
2'b00, 2'b01: // group 1
begin
case ({mb[7],mb[5]})
2'b00: ;
2'b01: ac <= ~ac;
2'b10: ac <= 12'o0;
2'b11: ac <= 12'o7777;
endcase
case ({mb[6],mb[4]})
2'b00: ;
2'b01: l <= ~l;
2'b10: l <= 1'b0;
2'b11: l <= 1'b1;
@ -750,9 +756,6 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
if (mb[7])
ac <= 0;
end
default:
;
endcase
if (iot && UF)
@ -763,7 +766,8 @@ $display("user iot: set UI");
if (iot && ~UF)
begin
casex (io_select)
/* verilator lint_off CASEINCOMPLETE */
casez (io_select)
6'b000000: // ION, IOF
case (mb[2:0])
3'b001:
@ -776,7 +780,7 @@ $display("user iot: set UI");
// interrupt_skip = 1;
endcase
6'b010xxx: // CDF..RMF
6'b010???: // CDF..RMF
begin
if (mb[0])
DF <= mb[5:3]; // CDF
@ -828,7 +832,8 @@ $display("user iot: set UI");
end // if (mb[2:0] == 3'b100)
end
endcase // case(io_select)
/* verilator lint_on CASEINCOMPLETE */
if (io_data_avail)
begin
`ifdef debug
@ -874,6 +879,7 @@ $display("user iot: set UI");
// group 3
if (mb[8] & mb[0])
/* verilator lint_off CASEINCOMPLETE */
case ({mb[6:4]})
3'b001: /* MQL */
begin
@ -883,6 +889,7 @@ $display("user iot: set UI");
3'b100: ac <= ac | mq; /* MQA */
3'b101: ac <= mq;
endcase
/* verilator lint_on CASEINCOMPLETE */
end
end
@ -894,6 +901,7 @@ $display("user iot: set UI");
if (!mb[8])
begin
case (mb[3:1])
3'b000: ;
3'b001: // BSW
{l,ac} <= {l,ac[5:0],ac[11:6]};
3'b010: // RAL
@ -904,6 +912,8 @@ $display("user iot: set UI");
{l,ac} <= {ac[0],l,ac[11:1]};
3'b101: // RTR
{l,ac} <= {ac[1:0],l,ac[11:2]};
3'b110: ;
3'b111: ;
endcase
end
@ -1017,7 +1027,11 @@ $display("user iot: set UI");
else
if (dca)
ac <= 0;
end
end // case: E3
default:
;
endcase // case(state)
endmodule

15
rtl/pdp8_io.v
View File

@ -8,7 +8,7 @@ module pdp8_io(clk, brgclk, reset, iot, state, mb,
io_data_avail, io_interrupt, io_skip, io_clear_ac,
io_ram_read_req, io_ram_write_req, io_ram_done,
io_ram_ma, io_ram_in, io_ram_out,
ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus,
ide_dior, ide_diow, ide_cs, ide_da, ide_data_in, ide_data_out,
rs232_in, rs232_out);
input clk;
@ -37,7 +37,8 @@ module pdp8_io(clk, brgclk, reset, iot, state, mb,
output ide_diow;
output [1:0] ide_cs;
output [2:0] ide_da;
inout [15:0] ide_data_bus;
input [15:0] ide_data_in;
output [15:0] ide_data_out;
input rs232_in;
output rs232_out;
@ -90,7 +91,7 @@ module pdp8_io(clk, brgclk, reset, iot, state, mb,
.uart_out(rs232_out));
`ifndef use_rf_pli
pdp8_rf tf(.clk(clk),
pdp8_rf rf(.clk(clk),
.reset(reset),
.iot(iot),
.state(state),
@ -116,7 +117,8 @@ module pdp8_io(clk, brgclk, reset, iot, state, mb,
.ide_diow(ide_diow),
.ide_cs(ide_cs),
.ide_da(ide_da),
.ide_data_bus(ide_data_bus));
.ide_data_in(ide_data_in),
.ide_data_out(ide_data_out));
`endif
assign tt_io_clear_ac = 1'b0;
@ -131,8 +133,9 @@ module pdp8_io(clk, brgclk, reset, iot, state, mb,
rf_io_selected ? rf_io_data_avail :
1'b0;
`ifdef debug
always @(*)
`ifdef debug_ints
// always @(*)
always @(kw_io_interrupt or tt_io_interrupt or rf_io_interrupt or io_interrupt)
if (io_interrupt)
$display("io: io_interrupt: %b %b %b",
kw_io_interrupt, tt_io_interrupt, rf_io_interrupt);

17
rtl/pdp8_kw.v
View File

@ -57,19 +57,23 @@ module pdp8_kw(clk, reset, iot, state, mb,
io_selected = 1'b0;
if (state == F1 && iot)
/* verilator lint_off CASEINCOMPLETE */
case (io_select)
6'o13:
begin
io_selected = 1'b1;
/* verilator lint_off CASEINCOMPLETE */
case (mb[2:0] )
3'o3:
if (kw_flag)
io_skip = 1'b1;
endcase
/* verilator lint_on CASEINCOMPLETE */
end
endcase // case(io_select)
/* verilator lint_on CASEINCOMPLETE */
end
`ifdef sim_time_kw
@ -131,7 +135,7 @@ module pdp8_kw(clk, reset, iot, state, mb,
end
3'o3:
begin
`ifdef debug
`ifdef sim_time_kw
$display("kw8i: CSCF %d", c_cycles);
`endif
kw_flag <= 1'b0;
@ -151,6 +155,8 @@ module pdp8_kw(clk, reset, iot, state, mb,
kw_clk_en <= 1;
kw_int_en <= 1;
end
default:
;
endcase
end
@ -160,13 +166,19 @@ module pdp8_kw(clk, reset, iot, state, mb,
begin
kw_flag <= 1;
`ifdef debug
if (kw_clk_en)
$display("kw8i: assert_kw_flag %t", $time);
`endif
`ifdef sim_time_kw
if (kw_flag == 0) $display("kw8i: set kw_flag! cycles %d, %t",
cycles, $time);
`endif
end
end
default:
;
endcase // case(state)
//
@ -181,7 +193,8 @@ module pdp8_kw(clk, reset, iot, state, mb,
if (assert_kw_ctr_zero)
begin
`ifdef debug
$display("kw8i assert assert_kw_flag rtl");
if (kw_clk_en)
$display("kw8i assert assert_kw_flag rtl");
`endif
assert_kw_flag <= 1;
end

31
rtl/pdp8_ram.v
View File

@ -27,15 +27,6 @@ module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr,
inout [15:0] sram2_io;
output sram2_ce_n, sram2_ub_n, sram2_lb_n;
`ifdef use_sim_model
ram_32kx12 ram(.A(addr),
.DI(data_in),
.DO(data_out),
.CE_N(1'b0),
.WE_N(~wr));
`else
//
wire rom_decode;
wire [11:0] rom_data;
@ -47,8 +38,28 @@ module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr,
.rd(rd),
.selected(rom_decode));
`ifdef use_sim_ram_model
wire [11:0] sram_data_in;
wire [11:0] sram_data_out;
ram_32kx12 ram(.A(addr),
.DI(sram_data_in),
.DO(sram_data_out),
.CE_N(1'b0),
.WE_N(~wr));
assign sram_data_in = data_in;
assign data_out = rom_decode ? rom_data : sram_data_out;
// always @(posedge clk)
// $display("addr %o, rom_decode %b %o", addr, rom_decode, rom_data);
`else
//
wire sram1_ub, sram1_lb;
wire sram1_ub, sram1_lb;
// common
assign sram_a = {3'b0, addr};

86
rtl/pdp8_rf.v
View File

@ -381,7 +381,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
io_data_avail, io_interrupt, io_skip, io_clear_ac,
ram_read_req, ram_write_req, ram_done,
ram_ma, ram_in, ram_out,
ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus);
ide_dior, ide_diow, ide_cs, ide_da, ide_data_in, ide_data_out);
input clk, reset, iot;
input [11:0] io_data_in;
@ -407,7 +407,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
output ide_diow;
output [1:0] ide_cs;
output [2:0] ide_da;
inout [15:0] ide_data_bus;
input [15:0] ide_data_in;
output [15:0] ide_data_out;
// -------------------------------------------------------
@ -565,7 +566,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
.buffer_wr(ide_buffer_wr),
.buffer_in(ide_buffer_in),
.buffer_out(ide_buffer_out),
.ide_data_bus(ide_data_bus),
.ide_data_in(ide_data_in),
.ide_data_out(ide_data_out),
.ide_dior(ide_dior),
.ide_diow(ide_diow),
.ide_cs(ide_cs),
@ -617,6 +619,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
$display("rf: DMAW disk_addr %o", {EMA, DMA});
`endif
end
default:
;
endcase
end // case: 6'o60
@ -640,6 +644,10 @@ module pdp8_rf(clk, reset, iot, state, mb,
io_data_out = 0;
io_clear_ac = 1;
end
default:
;
endcase // case(mb[2:0])
end
@ -661,6 +669,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
io_data_out = DMA;
io_clear_ac = 1;
end
default:
;
endcase
end
@ -674,9 +684,14 @@ module pdp8_rf(clk, reset, iot, state, mb,
io_clear_ac = 1;
end
3'o5: // DXAC
io_data_out = EMA;
io_data_out = { 4'b0, EMA };
default:
;
endcase // case(mb[2:0])
end
default:
;
endcase // case(io_select)
end
@ -691,8 +706,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
is_read <= 1'b0;
is_write <= 1'b0;
EMA <= 1'b0;
DMA <= 1'b0;
EMA <= 8'b0;
DMA <= 12'b0;
MEX <= 3'b0;
PEF <= 1'b0;
CIE <= 1'b0;
@ -736,7 +751,12 @@ module pdp8_rf(clk, reset, iot, state, mb,
3'o5: // DIML
begin
end
default:
;
endcase // case(mb[2:0])
default:
;
endcase
end
@ -772,6 +792,9 @@ module pdp8_rf(clk, reset, iot, state, mb,
$display("rf: DMAW ac %o", io_data_in);
`endif
end
default:
;
endcase // case(mb[2:0])
6'o61:
@ -786,6 +809,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
$display("rf: DIML %o", io_data_in);
`endif
end
default:
;
endcase // case(mb[2:0])
6'o64:
@ -795,10 +820,14 @@ module pdp8_rf(clk, reset, iot, state, mb,
3: // DXAL
begin
// clear ac
EMA <= io_data_in;
EMA <= io_data_in[7:0];
end
default:
;
endcase
default:
;
endcase
end // if (iot)
@ -823,6 +852,9 @@ module pdp8_rf(clk, reset, iot, state, mb,
DCF <= 1'b1;
end
default:
;
endcase // case(state)
// comb logic to create 'next state'
@ -945,6 +977,9 @@ module pdp8_rf(clk, reset, iot, state, mb,
db_next_state = DB_read_new_page;
end
end
default:
;
endcase
end
@ -981,6 +1016,9 @@ module pdp8_rf(clk, reset, iot, state, mb,
$display("read-new; buffer-dirty %b, buffer-disk-addr %o, disk-addr %o",
buffer_dirty, buffer_disk_addr[19:8], disk_addr[19:8]);
end
default:
;
endcase
`endif
end
@ -992,7 +1030,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
if (reset)
begin
dma_wc <= 12'b0;
dma_addr <= 14'b0;
dma_addr <= 15'b0;
end
else
begin
@ -1041,7 +1079,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
DB_next_xfer_read:
begin
/* snoop for our wc & ca */
if (dma_addr == 14'o07750 && ram_done)
if (dma_addr == 15'o07750 && ram_done)
begin
dma_wc <= buff_out;
`ifdef debug
@ -1049,7 +1087,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
`endif
end
if (dma_addr == 14'o07751 && ram_done)
if (dma_addr == 15'o07751 && ram_done)
begin
dma_addr[11:0] <= buff_out;
`ifdef debug
@ -1079,6 +1117,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
end
`endif
default:
;
endcase
end
@ -1162,7 +1202,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
db_state == DB_next_xfer_read ? buff_out :
db_state == DB_begin_xfer_write ? buffer_hold :
db_state == DB_done_xfer ? dma_wc :
db_state == DB_done_xfer1 ? dma_addr :
db_state == DB_done_xfer1 ? dma_addr[11:0] :
12'b0;
assign buffer_rd = db_state == DB_check_xfer_read && buffer_matches_DMA;
@ -1195,5 +1235,29 @@ module pdp8_rf(clk, reset, iot, state, mb,
WLS <= 1'b0;
end
`ifdef debug_rf_state
always @(posedge clk)
/* verilator lint_off CASEINCOMPLETE */
case (db_state)
DB_idle: $display("db_state: DB_idle");
DB_start_xfer1: $display("db_state: DB_start_xfer1");
DB_start_xfer2: $display("db_state: DB_start_xfer2");
DB_start_xfer3: $display("db_state: DB_start_xfer3");
DB_check_xfer_read: $display("db_state: DB_check_xfer_read");
DB_next_xfer_read: $display("db_state: DB_next_xfer_read");
DB_next_xfer_incr: $display("db_state: DB_next_xfer_incr");
DB_begin_xfer_write: $display("db_state: DB_begin_xfer_write");
DB_check_xfer_write: $display("db_state: DB_check_xfer_write");
DB_done_xfer: $display("db_state: DB_done_xfer");
DB_done_xfer1: $display("db_state: DB_done_xfer1");
DB_done_xfer2: $display("db_state: DB_done_xfer2");
DB_done_xfer3: $display("db_state: DB_done_xfer3");
DB_read_new_page: $display("db_state: DB_read_new_page");
DB_write_old_page: $display("db_state: DB_write_old_page %t", $time);
endcase
/* verilator lint_on CASEINCOMPLETE */
`endif
endmodule

55
rtl/pdp8_tt.v
View File

@ -49,8 +49,8 @@ module pdp8_tt(clk, brgclk, reset,
wire tx_busy;
// interface to uart
reg [1:0] tto_state;
wire [1:0] tto_state_next;
reg [2:0] tto_state;
wire [2:0] tto_state_next;
wire tto_empty;
wire tto_req;
reg tto_write;
@ -143,14 +143,17 @@ module pdp8_tt(clk, brgclk, reset,
io_skip = rx_int;
if (mb[1])
tti_read = 1;
begin
tti_read = 1;
end
if (mb[2])
begin
io_data_out = rx_data;
`ifdef debug_tt_data
$display("xxx rx_data %o", rx_data);
if (mb[1])
$display("xxx rx_data %o", rx_data);
`endif
io_data_out = rx_data;
end
else
io_data_out = 12'b0;
@ -169,6 +172,10 @@ module pdp8_tt(clk, brgclk, reset,
if (mb[2])
tto_write = 1;
end
default:
;
endcase // case(io_select)
end
@ -203,7 +210,12 @@ module pdp8_tt(clk, brgclk, reset,
6'o03:
begin
if (mb[1] /*&& ~assert_rx_int*/)
rx_int <= 1'b0;
begin
rx_int <= 1'b0;
`ifdef debug
$display("xxx reset rx_int");
`endif
end
end
6'o04:
@ -214,7 +226,7 @@ module pdp8_tt(clk, brgclk, reset,
if (mb[1] && ~assert_tx_int)
begin
tx_int <= 1'b0;
`ifdef debug_tt_in
`ifdef debug
$display("xxx reset tx_int");
`endif
end
@ -226,19 +238,26 @@ tx_int <= 1'b0;
$display("xxx tx_data %o %t", io_data_in, $time);
`endif
end
end // case: 6'o04
end
default:
;
endcase
end // if (iot && state == F1)
else
begin
if (assert_rx_int)
if (assert_rx_int && ~rx_int)
begin
//$display("xxx set rx_int");
$display("xxx set rx_int");
rx_int <= 1;
end
if (assert_tx_int)
tx_int <= 1;
if (assert_tx_int && ~tx_int)
begin
$display("xxx set tx_int");
tx_int <= 1;
end
// if (assert_tx_int)
// begin
@ -273,12 +292,18 @@ tx_int <= 1'b0;
assign tto_state_next = (tto_state == 0 && tto_write) ? 1 :
(tto_state == 1 && tx_ack) ? 2 :
(tto_state == 2 && ~tx_ack) ? 3 :
(tto_state == 3 && tx_empty) ? 0 :
(tto_state == 3 && tx_empty) ? 4 :
(tto_state == 4) ? 0 :
tto_state;
assign assert_tx_int = tto_state == 3 && tx_empty;
// assign assert_tx_int = tto_empty;
assign assert_tx_int = tto_state == 4;
`ifdef debug
always @(posedge clk)
if (tto_state != 0)
$display("tto_state %d; tx_ack %b tx_empty %b",
tto_state, tx_ack, tx_empty);
`endif
`ifdef debug_tt_int
always @(posedge clk)

22
rtl/ram_256x12.v
View File

@ -28,20 +28,32 @@ module ram_256x12(clk, reset, a, din, dout, ce, we);
begin
if (we && ce)
begin
`ifdef debug
if (ram_debug)
`ifdef debug_rf_buffer
if (ram_debug != 0)
$display("rf: buffer ram write [%o] <- %o", a, din);
`endif
ram[a] = din;
end
`ifdef debug
if (ram_debug && we == 0 && ce == 1)
`ifdef debug_rf_buffer
if (ram_debug != 0&& we == 0 && ce == 1)
$display("rf: buffer ram read [%o] -> %o", a, ram[a]);
`endif
end
//`define is_async
`ifdef is_async
assign dout = ram[a];
`else
reg [11:0] dout;
always @(posedge clk)
if (reset)
dout <= 0;
else
if (~we && ce)
dout <= ram[a];
`endif
endmodule

19
rtl/ram_32kx12.v
View File

@ -11,7 +11,7 @@ module ram_32kx12(A, DI, DO, CE_N, WE_N);
// synthesis translate_off
integer i;
reg [11:0] v;
integer file;
reg [63:0] file;
reg [1023:0] str;
reg [1023:0] testfilename;
integer n;
@ -41,14 +41,17 @@ module ram_32kx12(A, DI, DO, CE_N, WE_N);
begin
$display("ram: code filename: %s", testfilename);
file = $fopen(testfilename, "r");
while ($fscanf(file, "%o %o\n", i, v) > 0)
if (file > 0)
begin
//$display("ram[%o] <- %o", i, v);
ram[i] = v;
while ($fscanf(file, "%o %o\n", i, v) > 0)
begin
$display("ram[%o] <- %o", i, v);
ram[i] = v;
end
$display("ram: done reading");
$fclose(file);
end
$fclose(file);
end
end
// synthesis translate_on
@ -64,7 +67,7 @@ module ram_32kx12(A, DI, DO, CE_N, WE_N);
ram[ A ] = DI;
end
`ifdef debug_ram
`ifdef debug_ram_read
if (WE_N == 1 && CE_N == 0)
$display("ram: read [%o] -> %o", A, ram[A]);
`endif

2
rtl/uart.v
View File

@ -243,6 +243,7 @@ module uart(clk, reset,
4'd7: $display("tx: %b", tx_reg[6]);
4'd8: $display("tx: %b", tx_reg[7]);
4'd9: $display("tx: done");
default: ;
endcase
`endif
@ -261,6 +262,7 @@ module uart(clk, reset,
tx_cnt <= 0;
tx_empty <= 1;
end
default: ;
endcase
end