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brought rs232 to top

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This commit is contained in:
brad
2010-04-14 23:41:35 +00:00
parent 6379274142
commit 6a67dce53a
9 changed files with 104 additions and 44 deletions
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4
rtl/ide_disk.v
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@@ -193,7 +193,9 @@ module ide_disk(clk, reset,
begin begin
ide_state_next = init0; ide_state_next = init0;
clear_done = 1; clear_done = 1;
`ifdef debug
$display("ide_disk: XXX go!"); $display("ide_disk: XXX go!");
`endif
end end
end end
@@ -413,7 +415,9 @@ module ide_disk(clk, reset,
begin begin
clear_done = 1; clear_done = 1;
ide_state_next = ready; ide_state_next = ready;
`ifdef debug
$display("ide_disk: XXX last3, done"); $display("ide_disk: XXX last3, done");
`endif
end end
default: default:

6
rtl/pdp8.v
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@@ -758,9 +758,7 @@ module pdp8(clk, reset,
mq <= ac; mq <= ac;
ac <= 0; ac <= 0;
end end
3'b100: ac <= ac | mq; 3'b100: ac <= ac | mq; /* MQA */
//3'b101: tmq <= mq;
3'b100: ac <= mq; /* MQA */
3'b101: ac <= mq; 3'b101: ac <= mq;
endcase endcase
end end
@@ -796,7 +794,9 @@ module pdp8(clk, reset,
ac <= ac | switches; ac <= ac | switches;
if (mb[1]) if (mb[1])
begin begin
`ifdef debug
$display("HLT! %o", mb); $display("HLT! %o", mb);
`endif
run <= 0; run <= 0;
end end
end end

36
rtl/pdp8_io.v
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@@ -3,14 +3,18 @@
// Dev 2006 Brad Parker brad@heeltoe.com // Dev 2006 Brad Parker brad@heeltoe.com
// Revamp 2009 Brad Parker brad@heeltoe.com // Revamp 2009 Brad Parker brad@heeltoe.com
module pdp8_io(clk, reset, iot, state, mb, module pdp8_io(clk, brgclk, reset, iot, state, mb,
io_data_in, io_data_out, io_select, io_data_in, io_data_out, io_select,
io_data_avail, io_interrupt, io_skip, io_clear_ac, io_data_avail, io_interrupt, io_skip, io_clear_ac,
io_ram_read_req, io_ram_write_req, io_ram_done, io_ram_read_req, io_ram_write_req, io_ram_done,
io_ram_ma, io_ram_in, io_ram_out, io_ram_ma, io_ram_in, io_ram_out,
ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus); ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus,
rs232_in, rs232_out);
input clk, reset, iot; input clk;
input brgclk;
input reset;
input iot;
input [11:0] io_data_in; input [11:0] io_data_in;
input [11:0] mb; input [11:0] mb;
input [3:0] state; input [3:0] state;
@@ -29,6 +33,15 @@ module pdp8_io(clk, reset, iot, state, mb,
output wire [14:0] io_ram_ma; output wire [14:0] io_ram_ma;
output wire [11:0] io_ram_out; output wire [11:0] io_ram_out;
output ide_dior;
output ide_diow;
output [1:0] ide_cs;
output [2:0] ide_da;
inout [15:0] ide_data_bus;
input rs232_in;
output rs232_out;
wire kw_io_selected; wire kw_io_selected;
wire kw_io_interrupt; wire kw_io_interrupt;
wire kw_io_skip; wire kw_io_skip;
@@ -47,13 +60,6 @@ module pdp8_io(clk, reset, iot, state, mb,
wire rf_io_skip; wire rf_io_skip;
wire rf_io_clear_ac; wire rf_io_clear_ac;
output ide_dior;
output ide_diow;
output [1:0] ide_cs;
output [2:0] ide_da;
inout [15:0] ide_data_bus;
pdp8_kw kw(.clk(clk), pdp8_kw kw(.clk(clk),
.reset(reset), .reset(reset),
.iot(iot), .iot(iot),
@@ -66,7 +72,7 @@ module pdp8_io(clk, reset, iot, state, mb,
.io_skip(kw_io_skip)); .io_skip(kw_io_skip));
pdp8_tt tt(.clk(clk), pdp8_tt tt(.clk(clk),
.brgclk(/*brgclk*/clk), .brgclk(brgclk),
.reset(reset), .reset(reset),
.iot(iot), .iot(iot),
.state(state), .state(state),
@@ -78,7 +84,10 @@ module pdp8_io(clk, reset, iot, state, mb,
.io_data_out(tt_io_data_out), .io_data_out(tt_io_data_out),
.io_data_avail(tt_io_data_avail), .io_data_avail(tt_io_data_avail),
.io_interrupt(tt_io_interrupt), .io_interrupt(tt_io_interrupt),
.io_skip(tt_io_skip)); .io_skip(tt_io_skip),
.uart_in(rs232_in),
.uart_out(rs232_out));
pdp8_rf tf(.clk(clk), pdp8_rf tf(.clk(clk),
.reset(reset), .reset(reset),
@@ -107,6 +116,9 @@ module pdp8_io(clk, reset, iot, state, mb,
.ide_da(ide_da), .ide_da(ide_da),
.ide_data_bus(ide_data_bus)); .ide_data_bus(ide_data_bus));
assign tt_io_clear_ac = 1'b0;
assign rf_io_clear_ac = 1'b0;
assign io_data_out = assign io_data_out =
tt_io_selected ? tt_io_data_out : tt_io_selected ? tt_io_data_out :
rf_io_selected ? rf_io_data_out : rf_io_selected ? rf_io_data_out :

12
rtl/pdp8_kw.v
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@@ -85,28 +85,38 @@ module pdp8_kw(clk, reset, iot, state, mb,
begin begin
kw_int_en <= 1'b1; kw_int_en <= 1'b1;
kw_clk_en <= 1'b1; kw_clk_en <= 1'b1;
`ifdef debug
$display("kw8i: clocks on!"); $display("kw8i: clocks on!");
`endif
end end
3'o2: 3'o2:
begin begin
`ifdef debug
$display("CCFF"); $display("CCFF");
`endif
kw_flag <= 1'b0; kw_flag <= 1'b0;
kw_clk_en <= 1'b0; kw_clk_en <= 1'b0;
kw_int_en <= 1'b0; kw_int_en <= 1'b0;
end end
3'o3: 3'o3:
begin begin
`ifdef debug
$display("CSCF"); $display("CSCF");
`endif
kw_flag <= 1'b0; kw_flag <= 1'b0;
end end
3'o6: 3'o6:
begin begin
`ifdef debug
$display("CCEC"); $display("CCEC");
`endif
kw_clk_en <= 1; kw_clk_en <= 1;
end end
3'o7: 3'o7:
begin begin
`ifdef debug
$display("CECI"); $display("CECI");
`endif
kw_clk_en <= 1; kw_clk_en <= 1;
kw_int_en <= 1; kw_int_en <= 1;
end end
@@ -118,7 +128,9 @@ module pdp8_kw(clk, reset, iot, state, mb,
if (assert_kw_flag) if (assert_kw_flag)
begin begin
kw_flag <= 1; kw_flag <= 1;
`ifdef debug
if (kw_flag == 0) $display("kw8i: set kw_flag!\n"); if (kw_flag == 0) $display("kw8i: set kw_flag!\n");
`endif
end end
end end

2
rtl/pdp8_ram.v
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@@ -35,8 +35,6 @@ module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr,
.CE_N(1'b0), .CE_N(1'b0),
.WE_N(~wr)); .WE_N(~wr));
`else `else
wire [15:0] ram1_io;
// //
wire sram1_ub, sram1_lb; wire sram1_ub, sram1_lb;

37
rtl/pdp8_rf.v
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@@ -1,6 +1,8 @@
// RF08 Emulation using IDE disk // RF08 Emulation using IDE disk
// brad@heeltoe.com // brad@heeltoe.com
//`define debug_rf
/* /*
RF08 Sizes: RF08 Sizes:
@@ -523,7 +525,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
assign buff_addr = ide_active ? ide_buffer_addr : buffer_addr; assign buff_addr = ide_active ? ide_buffer_addr : buffer_addr;
assign buff_in = ide_active ? ide_buffer_out : buffer_hold; assign buff_in = ide_active ? ide_buffer_out : buffer_hold;
assign buff_rd = ide_active ? ide_buffer_rd : 1'b1; assign buff_rd = ide_active ? ide_buffer_rd : 1'b1/*buffer_rd?*/;
assign buff_wr = ide_active ? ide_buffer_wr : buffer_wr; assign buff_wr = ide_active ? ide_buffer_wr : buffer_wr;
// ide disk // ide disk
@@ -552,8 +554,10 @@ module pdp8_rf(clk, reset, iot, state, mb,
// //
// combinatorial logic // combinatorial logic
always @(state or always @(state or iot or io_select or mb or io_data_in or
ADC or DRL or PER or WLS or NXD or DCF) ADC or DRL or PER or WLS or NXD or DCF or
PCA or DRE or EIE or PIE or CIE or MEX or DMA or EMA or
disk_addr)
begin begin
// sampled during f1 // sampled during f1
io_skip = 0; io_skip = 0;
@@ -572,7 +576,9 @@ module pdp8_rf(clk, reset, iot, state, mb,
begin begin
io_data_out = 0; io_data_out = 0;
dma_start = 1'b1; dma_start = 1'b1;
`ifdef debug
$display("rf: go! disk_addr %o", disk_addr); $display("rf: go! disk_addr %o", disk_addr);
`endif
end end
3'o5: // DMAW 3'o5: // DMAW
begin begin
@@ -660,7 +666,9 @@ module pdp8_rf(clk, reset, iot, state, mb,
6'o60: // DCMA 6'o60: // DCMA
if (mb[2:0] == 3'b001) if (mb[2:0] == 3'b001)
begin begin
$display("rf: DCMA"); `ifdef debug
$display("rf: DCMA");
`endif
DMA <= 0; DMA <= 0;
PEF <= 1'b0; PEF <= 1'b0;
NXD <= 1'b0; NXD <= 1'b0;
@@ -674,7 +682,9 @@ $display("rf: DCMA");
PIE <= 1'b0; PIE <= 1'b0;
CIE <= 1'b0; CIE <= 1'b0;
MEX <= 3'b0; MEX <= 3'b0;
$display("rf: DCIM"); `ifdef debug
$display("rf: DCIM");
`endif
end end
3'o2: // DSAC 3'o2: // DSAC
begin begin
@@ -724,7 +734,9 @@ is_read <= 1'b1;
PIE <= io_data_in[7]; PIE <= io_data_in[7];
CIE <= io_data_in[6]; CIE <= io_data_in[6];
MEX <= io_data_in[5:3]; MEX <= io_data_in[5:3];
$display("rf: DIML %o", io_data_in); `ifdef debug
$display("rf: DIML %o", io_data_in);
`endif
end end
endcase // case(mb[2:0]) endcase // case(mb[2:0])
@@ -755,7 +767,9 @@ $display("rf: DIML %o", io_data_in);
DMA <= disk_addr[11:0]; DMA <= disk_addr[11:0];
is_read <= 1'b0; is_read <= 1'b0;
is_write <= 1'b0; is_write <= 1'b0;
$display("rf: set DCF (CIE %b)", CIE); `ifdef debug
$display("rf: set DCF (CIE %b)", CIE);
`endif
DCF <= 1'b1; DCF <= 1'b1;
end end
@@ -861,13 +875,18 @@ $display("rf: set DCF (CIE %b)", CIE);
begin begin
dma_wc <= ram_in + 12'o0001; dma_wc <= ram_in + 12'o0001;
db_done <= 0; db_done <= 0;
`ifdef debug
if (ram_done) $display("rf: read wc %o", ram_in); if (ram_done) $display("rf: read wc %o", ram_in);
`endif
end end
DB_start_xfer2: DB_start_xfer2:
begin begin
dma_addr <= { MEX, ram_in + 12'o0001 }; dma_addr <= { MEX, ram_in + 12'o0001 };
`ifdef debug
if (ram_done) $display("rf: read ca %o", ram_in); if (ram_done) $display("rf: read ca %o", ram_in);
`endif
end end
DB_start_xfer3: DB_start_xfer3:
@@ -899,15 +918,19 @@ $display("rf: set DCF (CIE %b)", CIE);
DB_check_xfer_write: DB_check_xfer_write:
buffer_dirty <= 1; buffer_dirty <= 1;
`ifdef debug
DB_done_xfer: DB_done_xfer:
if (ram_done) $display("rf: write wc %o", dma_wc); if (ram_done) $display("rf: write wc %o", dma_wc);
DB_done_xfer1: DB_done_xfer1:
if (ram_done) $display("rf: write ca %o", dma_addr); if (ram_done) $display("rf: write ca %o", dma_addr);
`endif
DB_done_xfer2: DB_done_xfer2:
begin begin
`ifdef debug
$display("rf: done"); $display("rf: done");
`endif
db_done <= 1; db_done <= 1;
end end

29
rtl/pdp8_tt.v
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@@ -1,17 +1,20 @@
// PDP8 console emulation // PDP8 console emulation
// brad@heeltoe.com // brad@heeltoe.com
//`define sim_time `ifdef debug
`define debug_tt_int 1 `define debug_tt_int 1
//`define debug_tt_reg 1 //`define debug_tt_reg 1
//`define debug_tt_state 1 //`define debug_tt_state 1
`define debug_tt_data 1 `define debug_tt_data 1
`endif
//`define sim_time
module pdp8_tt(clk, brgclk, reset, module pdp8_tt(clk, brgclk, reset,
iot, state, mb, iot, state, mb,
io_data_in, io_data_out, io_select, io_selected, io_data_in, io_data_out, io_select, io_selected,
io_data_avail, io_interrupt, io_skip); io_data_avail, io_interrupt, io_skip,
uart_in, uart_out);
input clk; input clk;
input brgclk; input brgclk;
@@ -22,15 +25,17 @@ module pdp8_tt(clk, brgclk, reset,
input [11:0] mb; input [11:0] mb;
input [11:0] io_data_in; input [11:0] io_data_in;
input [5:0] io_select; input [5:0] io_select;
input uart_in;
output reg [11:0] io_data_out; output reg [11:0] io_data_out;
output reg io_selected; output reg io_selected;
output io_data_avail; output io_data_avail;
output io_interrupt; output io_interrupt;
output reg io_skip; output reg io_skip;
output uart_out;
// internal state // internal state
reg [11:0] tx_data; reg [7:0] tx_data;
reg tx_int; reg tx_int;
wire tx_empty; wire tx_empty;
wire tx_ack; wire tx_ack;
@@ -80,7 +85,7 @@ module pdp8_tt(clk, brgclk, reset,
.tx_clk(uart_tx_clk), .tx_clk(uart_tx_clk),
.tx_req(tto_req), .tx_req(tto_req),
.tx_ack(tx_ack), .tx_ack(tx_ack),
.tx_data(tx_data[7:0]), .tx_data(tx_data),
.tx_empty(tx_empty), .tx_empty(tx_empty),
.rx_clk(uart_rx_clk), .rx_clk(uart_rx_clk),
@@ -96,14 +101,17 @@ module pdp8_tt(clk, brgclk, reset,
.tx_clk(uart_tx_clk), .tx_clk(uart_tx_clk),
.tx_req(tto_req), .tx_req(tto_req),
.tx_ack(tx_ack), .tx_ack(tx_ack),
.tx_data(tx_data[7:0]), .tx_data(tx_data),
.tx_empty(tx_empty), .tx_empty(tx_empty),
.rx_clk(uart_rx_clk), .rx_clk(uart_rx_clk),
.rx_req(tti_req), .rx_req(tti_req),
.rx_ack(rx_ack), .rx_ack(rx_ack),
.rx_data(rx_data[7:0]), .rx_data(rx_data[7:0]),
.rx_empty(rx_empty)); .rx_empty(rx_empty),
.rx_in(uart_in),
.tx_out(uart_out));
`endif `endif
// interrupt output // interrupt output
@@ -114,7 +122,8 @@ module pdp8_tt(clk, brgclk, reset,
assign rx_data[11:8] = 4'b0; assign rx_data[11:8] = 4'b0;
// combinatorial // combinatorial
always @(state or rx_int or tx_int) always @(state or iot or io_select or mb or
rx_int or tx_int or io_data_in or rx_data)
begin begin
// sampled during f1 // sampled during f1
io_skip = 1'b0; io_skip = 1'b0;
@@ -171,7 +180,7 @@ module pdp8_tt(clk, brgclk, reset,
rx_int <= 0; rx_int <= 0;
tx_int <= 0; tx_int <= 0;
tx_data <= 0; tx_data <= 8'b0;
end end
else else
begin begin
@@ -206,7 +215,7 @@ module pdp8_tt(clk, brgclk, reset,
end end
if (mb[2]) if (mb[2])
begin begin
tx_data <= io_data_in; tx_data <= io_data_in[7:0];
`ifdef debug_tt_data `ifdef debug_tt_data
$display("xxx tx_data %o", io_data_in); $display("xxx tx_data %o", io_data_in);
`endif `endif

8
rtl/top.v
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@@ -14,8 +14,8 @@ module top(rs232_txd, rs232_rxd,
sram2_io, sram2_ce_n, sram2_ub_n, sram2_lb_n, sram2_io, sram2_ce_n, sram2_ub_n, sram2_lb_n,
ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da); ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
output rs232_txd;
input rs232_rxd; input rs232_rxd;
output rs232_txd;
input [3:0] button; input [3:0] button;
@@ -96,7 +96,6 @@ module top(rs232_txd, rs232_rxd,
wire [14:0] ram_addr; wire [14:0] ram_addr;
wire [11:0] io_data_in; wire [11:0] io_data_in;
wire [11:0] io_data_out; wire [11:0] io_data_out;
wire [11:0] io_addr;
wire io_data_avail; wire io_data_avail;
wire io_interrupt; wire io_interrupt;
wire io_skip; wire io_skip;
@@ -147,6 +146,7 @@ module top(rs232_txd, rs232_rxd,
.ext_ram_out(ext_ram_in)); .ext_ram_out(ext_ram_in));
pdp8_io io(.clk(clk), pdp8_io io(.clk(clk),
.brgclk(clk),
.reset(reset), .reset(reset),
.iot(iot), .iot(iot),
.state(state), .state(state),
@@ -168,7 +168,9 @@ module top(rs232_txd, rs232_rxd,
.ide_diow(ide_diow), .ide_diow(ide_diow),
.ide_cs(ide_cs), .ide_cs(ide_cs),
.ide_da(ide_da), .ide_da(ide_da),
.ide_data_bus(ide_data_bus)); .ide_data_bus(ide_data_bus),
.rs232_in(rs232_rxd),
.rs232_out(rs232_txd));
pdp8_ram ram(.clk(clk), pdp8_ram ram(.clk(clk),
.reset(reset), .reset(reset),

14
rtl/uart.v
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@@ -4,8 +4,8 @@
module uart(clk, reset, module uart(clk, reset,
tx_clk, tx_req, tx_ack, tx_data, tx_empty, tx_clk, tx_req, tx_ack, tx_data, tx_empty,
rx_clk, rx_req, rx_ack, rx_data, rx_empty/*,*/ rx_clk, rx_req, rx_ack, rx_data, rx_empty,
/*rx_in, tx_out*/); rx_in, tx_out);
input clk; input clk;
input reset; input reset;
@@ -13,18 +13,18 @@ module uart(clk, reset,
input tx_req; input tx_req;
output tx_ack; output tx_ack;
input [7:0] tx_data; input [7:0] tx_data;
// input tx_enable; output tx_out;
// output tx_out;
output tx_empty; output tx_empty;
input rx_clk; input rx_clk;
input rx_req; input rx_req;
output rx_ack; output rx_ack;
output [7:0] rx_data; output [7:0] rx_data;
// input rx_enable; input rx_in;
// input rx_in;
wire rx_in;
output rx_empty; output rx_empty;
// input tx_enable;
// input rx_enable;
reg tx_ack; reg tx_ack;
reg rx_ack; reg rx_ack;