diff --git a/verif/NOTEs.txt b/verif/NOTEs.txt
index 3b8aae2..44a3f8b 100644
--- a/verif/NOTEs.txt
+++ b/verif/NOTEs.txt
@@ -317,3 +317,15 @@ rf: start! read disk_addr 0333400 (033 3400) (ma 37000 wc 7001)
 rf: start! write disk_addr 0016000 (001 6000) (ma 26000 wc 6001)
 
 rf: start! read disk_addr 0000000 (000 0000) (ma 20000 wc 0001)
+
+------------------
+
+61 60 15
+xxx int_req 7000020
+xxx int_req 7000020
+xxx int_req 7000020
+xxx int_req 7000020
+xxx int_req 7000020
+xxx int_req 7000020
+xxx int_req 7000010
+xxx rx input 114 (1/14)
diff --git a/verif/fake_uart.v b/verif/fake_uart.v
index eecc5e0..dabe4ab 100644
--- a/verif/fake_uart.v
+++ b/verif/fake_uart.v
@@ -55,24 +55,28 @@ module fake_uart(clk, reset, state,
 
    always @(posedge clk)
      begin
+`ifdef debug/*_fake_tx*/
+	if (t_state != 0)
+	  $display("t_state %d t_delay %d t_done %b tx_empty %b",
+		   t_state, t_delay, t_done, tx_empty);
+`endif
+
 	if (t_state == 1)
 	  begin
 	     t_delay = 38/*20*/;
 	  end
-	if (t_delay > 0)
+	if (t_state == 2)
 	  begin
-	     if (state == 4'b0001)
-	       t_delay = t_delay - 1;
-//	     t_delay = t_delay - 1;
-	     if (t_delay == 0)
+	     if (t_delay < 0)
 	       begin
 		  t_done = 1;
-		  //$display("xxx t_done; cycles %d", cycles);
+		  $display("xxx t_done; cycles %d", cycles);
 	       end
-`ifdef debug_fake_tx
-	     $display("t_state %d t_delay %d", t_state, t_delay);
-`endif
+
+	     if (state == 4'b0001)
+	       t_delay = t_delay - 1;
 	  end
+
 	if (t_state == 0)
 	  t_done = 0;
      end
@@ -80,6 +84,8 @@ module fake_uart(clk, reset, state,
    integer cycles;
    initial
      cycles = 0;
+
+   parameter BASE = 230000;
    
    always @(posedge clk)
      begin
@@ -91,28 +97,35 @@ module fake_uart(clk, reset, state,
 //	       begin
 //		  $display("xxx want input; cycles %d", cycles);
 //	       end
-	     if (r_index == r_count && cycles == 110000/*200000*/)
+
+	     if (r_index != r_count && cycles == BASE+10000)
 	       begin
-		  rdata[0] = "L";
-		  rdata[1] = "O";
-		  rdata[2] = "G";
-		  rdata[3] = "I";
-		  rdata[4] = "N";
-		  rdata[5] = " ";
-		  rdata[6] = "2";
-		  rdata[7] = " ";
-		  rdata[8] = "L";
-		  rdata[9] = "X";
-		  rdata[10] = "H";
-		  rdata[11] = "E";
-		  rdata[12] = "\215";
-		  rdata[13] = "\215";
+		  $display("xxx can't boom 1 %d %d", r_index, r_count);
+	       end
+	     if (r_index == r_count && cycles == BASE+10000)
+	       begin
+		  ii = 0;
+		  rdata[ii] = "L"; ii = ii + 1;
+		  rdata[ii] = "O"; ii = ii + 1;
+		  rdata[ii] = "G"; ii = ii + 1;
+		  rdata[ii] = "I"; ii = ii + 1;
+		  rdata[ii] = "N"; ii = ii + 1;
+		  rdata[ii] = " "; ii = ii + 1;
+		  rdata[ii] = "2"; ii = ii + 1;
+		  rdata[ii] = " "; ii = ii + 1;
+		  rdata[ii] = "L"; ii = ii + 1;
+		  rdata[ii] = "X"; ii = ii + 1;
+		  rdata[ii] = "H"; ii = ii + 1;
+		  rdata[ii] = "E"; ii = ii + 1;
+		  rdata[ii] = "\215"; ii = ii + 1;
+		  rdata[ii] = "\215"; ii = ii + 1;
 		  r_index = 0;
-		  r_count = 14;
+		  r_count = ii;
 		  r_refires = 1;
 		  $display("xxx boom 1; cycles %d", cycles);
 	       end
-	     if (r_index == r_count && cycles == 120000/*300000*/)
+
+	     if (r_index == r_count && cycles == BASE+300000)
 	       begin
 		  rdata[0] = "\215";
 		  r_index = 0;
@@ -120,7 +133,7 @@ module fake_uart(clk, reset, state,
 		  r_refires = 2;
 		  $display("xxx boom 2; cycles %d", cycles);
 	       end
-	     if (r_index == r_count && cycles == 130000/*400000*/)
+	     if (r_index == r_count && cycles == BASE+320000)
 	       begin
 		  rdata[0] = "\215";
 		  r_index = 0;
@@ -132,7 +145,7 @@ module fake_uart(clk, reset, state,
 //`define msg_rfocal 1
 //`define msg_rpald 1
 //`define msg_rpip 1
-	     if (r_index == r_count && cycles == 300000/*500000*/)
+	     if (r_index == r_count && cycles == BASE+400000)
 	       begin
 `ifdef msg_rcat
 		  rdata[0] = "R";
@@ -180,7 +193,7 @@ module fake_uart(clk, reset, state,
 		  r_refires = 4;
 		  $display("xxx boom 4; cycles %d", cycles);
 	       end
-	     if (r_index == r_count && cycles == 400000/*600000*/)
+	     if (r_index == r_count && cycles == BASE+500000/*600000*/)
 	       begin
 		  rdata[0] = "\215";
 		  r_index = 0;
@@ -201,7 +214,10 @@ module fake_uart(clk, reset, state,
 
    assign rx_ack = r_state == 1;
    
-   integer r_index, r_count, r_refires;
+   /* verilator lint_off UNOPTFLAT */
+   integer r_index;
+   /* verilator lint_off UNOPTFLAT */
+   integer r_count, r_refires;
 
    integer do_refire, refire_state;
    
@@ -247,18 +263,19 @@ module fake_uart(clk, reset, state,
 	rdata[ii] = "1"; ii=ii+1;
 	rdata[ii] = "0"; ii=ii+1;
 	rdata[ii] = "\215"; ii=ii+1;
+	rdata[ii] = "\215"; ii=ii+1;
 	
 	rx_data = 0;
      end
 
    
-   always @(*)
+    always @(posedge clk)
      begin
 	if (r_state == 2)
 	  begin
 `ifdef debug_fake_rx
-	     $display("xxx dispense %0d %o %t",
-		      r_index, rdata[r_index], $time);
+	     $display("xxx dispense %o %0d %t",
+		      rdata[r_index], r_index, $time);
 `endif
 	     rx_data = rdata[r_index];
 	     r_index = r_index + 1;
diff --git a/verif/ram_s3board.v b/verif/ram_s3board.v
index 39e50cd..d7e8d07 100644
--- a/verif/ram_s3board.v
+++ b/verif/ram_s3board.v
@@ -69,7 +69,7 @@ module ram_s3board(ram_a, ram_oe_n, ram_we_n,
    // synthesis translate_off
    integer 	 i;
    reg [15:0] 	 v;
-   integer 	 file;
+   reg [63:0] 	 file;
    reg [1023:0]  str;
    reg [1023:0]  testfilename;
    integer 	 n;
@@ -78,8 +78,8 @@ module ram_s3board(ram_a, ram_oe_n, ram_we_n,
      begin
 	for (i = 0; i < 32768/*8192*/; i=i+1)
 	  begin
-             ram1.ram_h[i] = 7'b0;
-	     ram1.ram_l[i] = 7'b0;
+             ram1.ram_h[i] = 8'b0;
+	     ram1.ram_l[i] = 8'b0;
 	  end
 
 	n = 0;
diff --git a/verif/run_rf.sh b/verif/run_rf.sh
new file mode 100755
index 0000000..ecf00b6
--- /dev/null
+++ b/verif/run_rf.sh
@@ -0,0 +1,11 @@
+../cver/gplcver-2.12a.src/bin/cver  \
+    +loadvpi=../pli/rf/pli_rf.so:vpi_compat_bootstrap \
+    +define+use_rf_pli=1 \
+    +define+use_fake_uart=1 \
+    +define+sim_time_kw=1 \
+    +showpc \
+    +cycles=2000000 \
+    +pc=07400 \
+    test_pdp8.v
+exit 0
+
diff --git a/verif/run_tt.sh b/verif/run_tt.sh
new file mode 100755
index 0000000..4b12403
--- /dev/null
+++ b/verif/run_tt.sh
@@ -0,0 +1,9 @@
+../cver/gplcver-2.12a.src/bin/cver  \
+    +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \
+    +test=../tests/basic/uart.mem +pc=00400 \
+    +define+debug_vcd=1 \
+    +showpc \
+    +cycles=100000 \
+    test_pdp8.v
+exit 0
+
diff --git a/verif/test_pdp8.v b/verif/test_pdp8.v
index 73f1704..5b882aa 100644
--- a/verif/test_pdp8.v
+++ b/verif/test_pdp8.v
@@ -97,7 +97,8 @@ module test;
    wire        sram2_ub_n;
    wire        sram2_lb_n;
 
-   wire [15:0] ide_data_bus;
+   wire [15:0] ide_data_in;
+   wire [15:0] ide_data_out;
    wire        ide_dior, ide_diow;
    wire [1:0]  ide_cs;
    wire [2:0]  ide_da;
@@ -152,11 +153,14 @@ module test;
 	      .io_ram_ma(ext_ram_ma),
 	      .io_ram_in(ext_ram_in),
 	      .io_ram_out(ext_ram_out),
+
    	      .ide_dior(ide_dior),
 	      .ide_diow(ide_diow),
 	      .ide_cs(ide_cs),
 	      .ide_da(ide_da),
-	      .ide_data_bus(ide_data_bus),
+	      .ide_data_in(ide_data_in),
+	      .ide_data_out(ide_data_out),
+
 	      .rs232_in(rs232_in),
 	      .rs232_out(rs232_out));
 
@@ -388,6 +392,11 @@ module test;
     end
 
 `ifndef use_rf_pli
+   wire [15:0] ide_data_bus;
+
+   assign ide_data_in = ide_data_bus;
+   assign ide_data_bus = ~ide_diow ? ide_data_out : 16'bz;
+
    always @(posedge clk)
      begin
 	$pli_ide(ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
diff --git a/verif/tss8.cmd b/verif/tss8.cmd
index 98effd4..24e516b 100644
--- a/verif/tss8.cmd
+++ b/verif/tss8.cmd
@@ -1,5 +1,13 @@
 set rf enabled
 set df disabled
+set lp disabled
+set ptr disabled
+set ptp disabled
+set ttix disabled
+set ttox disabled
+set rk disabled
+set rx disabled
+set mt disabled
 attach rf rf.dsk
 boot rf
 exit
diff --git a/verif/verilator.sh b/verif/verilator.sh
new file mode 100755
index 0000000..228e948
--- /dev/null
+++ b/verif/verilator.sh
@@ -0,0 +1,2 @@
+verilator -cc -exe --trace --Mdir ./tmp --top-module test verilator_pdp8.v ../verilator/test.cpp ../verilator/ide.cpp && \
+(cd tmp; make OPT="-O2" -f Vtest.mk)
diff --git a/verif/verilator_pdp8.v b/verif/verilator_pdp8.v
new file mode 100644
index 0000000..97b3bcd
--- /dev/null
+++ b/verif/verilator_pdp8.v
@@ -0,0 +1,245 @@
+// this is verilator_pdp8.v
+// test bench top end for pdp8.v
+
+`define debug
+`define sim_time
+`define debug_s3ram
+`define use_sim_ram_model
+`define use_fake_uart
+`define debug_ram
+//`define debug_vcd
+//`define debug_log
+
+`include "../rtl/pdp8_tt.v"
+`include "../rtl/pdp8_rf.v"
+`include "../rtl/pdp8_kw.v"
+`include "../rtl/pdp8_io.v"
+`include "../rtl/pdp8_ram.v"
+`include "../rtl/pdp8.v"
+
+`ifdef use_fake_uart
+ `include "../verif/fake_uart.v"
+`else
+ `include "../rtl/uart.v"
+`endif
+
+`include "../rtl/brg.v"
+
+`include "../rtl/ide_disk.v"
+`include "../rtl/ide.v"
+`include "../rtl/ram_256x12.v"
+
+`include "../rtl/bootrom.v"
+
+`ifdef use_sim_ram_model
+ `include "../rtl/ram_32kx12.v"
+`else
+`include "../verif/ram_s3board.v"
+`endif
+
+`timescale 1ns / 1ns
+
+module wrap_ide(clk, ide_data_in, ide_data_out,
+		ide_dior, ide_diow, ide_cs, ide_da);
+
+   input clk;
+   input [15:0]  ide_data_in;
+   output [15:0] ide_data_out;
+   input 	 ide_dior;
+   input 	 ide_diow;
+   input [1:0] 	 ide_cs;
+   input [2:0] 	 ide_da;
+		
+   import "DPI-C" function void dpi_ide(input integer data_in,
+					output integer data_out,
+				        input integer dior,
+				        input integer diow,
+				        input integer cs,
+				        input integer da);
+
+   integer dbi, dbo;
+   wire [31:0] dboo;
+      
+   assign dbi = {16'b0, ide_data_in};
+   assign dboo = dbo;
+
+   assign ide_data_out = dboo[15:0];
+
+   always @(posedge clk)
+     begin
+	dpi_ide(dbi,
+		dbo,
+		{31'b0, ide_dior}, 
+		{31'b0, ide_diow},
+		{30'b0, ide_cs},
+		{29'b0, ide_da});
+
+`ifdef debug_ide
+	if (ide_dior == 0)
+	  begin
+	     $display("wrap_ide: read (%b %b) %x %x %x %x",
+		      ide_dior, ide_diow, dbo, dboo, dboo[15:0], ide_data_out);
+	  end
+	if (ide_diow == 0)
+	  begin
+	     $display("wrap_ide: write (%b %b) %x %x %x",
+		      ide_dior, ide_diow, dbo, dboo, ide_data_out);
+	  end
+`endif
+     end
+
+endmodule
+
+module test;
+
+   reg sysclk/*verilator public_flat_rw @(clk)*/;
+   wire clk;
+   reg reset/*verilator public_flat_rw @(clk) */;
+   reg [11:0] switches;
+
+   wire [14:0] initial_pc;
+   wire [11:0] pc_out;
+   wire [11:0] ac_out;
+   
+   wire [11:0] ram_data_in;
+   wire        ram_rd;
+   wire        ram_wr;
+   wire [11:0] ram_data_out;
+   wire [14:0] ram_addr;
+   wire [11:0] io_data_in;
+   wire [11:0] io_data_out;
+   wire [11:0] io_addr;
+   wire        io_data_avail;
+   wire        io_interrupt;
+   wire        io_skip;
+   wire        io_clear_ac;
+   wire [5:0]  io_select;
+   
+   wire        iot;
+   wire [3:0]  state;
+   wire [11:0] mb;
+   
+   wire        ext_ram_read_req;
+   wire        ext_ram_write_req;
+   wire [14:0] ext_ram_ma;
+   wire [11:0] ext_ram_in;
+   wire        ext_ram_done;
+   wire [11:0] ext_ram_out;
+
+   wire [17:0] sram_a;
+   wire        sram_oe_n;
+   wire        sram_we_n;
+   wire [15:0] sram1_io;
+   wire        sram1_ce_n;
+   wire        sram1_ub_n;
+   wire        sram1_lb_n;
+   wire [15:0] sram2_io;
+   wire        sram2_ce_n;
+   wire        sram2_ub_n;
+   wire        sram2_lb_n;
+
+   wire [15:0] 	ide_data_in;
+   wire [15:0] 	ide_data_out;
+   wire 	ide_dior, ide_diow;
+   wire [1:0] 	ide_cs;
+   wire [2:0] 	ide_da;
+
+   reg 	       rs232_in;
+   wire        rs232_out;
+
+//   always @(posedge sysclk)
+//     clk <= ~clk;
+   assign clk = sysclk;
+      
+  pdp8 cpu(.clk(clk),
+	   .reset(reset),
+	   .initial_pc(initial_pc),
+	   .pc_out(pc_out),
+	   .ac_out(ac_out),
+	   .ram_addr(ram_addr),
+	   .ram_data_in(ram_data_out),
+	   .ram_data_out(ram_data_in),
+	   .ram_rd(ram_rd),
+	   .ram_wr(ram_wr),
+	   .io_select(io_select),
+	   .io_data_in(io_data_in),
+	   .io_data_out(io_data_out),
+	   .io_data_avail(io_data_avail),
+	   .io_interrupt(io_interrupt),
+	   .io_skip(io_skip),
+	   .io_clear_ac(io_clear_ac),
+	   .switches(switches),
+	   .iot(iot),
+	   .state(state),
+	   .mb(mb),
+	   .ext_ram_read_req(ext_ram_read_req),
+	   .ext_ram_write_req(ext_ram_write_req),
+	   .ext_ram_done(ext_ram_done),
+	   .ext_ram_ma(ext_ram_ma),
+	   .ext_ram_in(ext_ram_out),
+	   .ext_ram_out(ext_ram_in));
+   
+   pdp8_io io(.clk(clk),
+	      .brgclk(clk),
+	      .reset(reset),
+	      .iot(iot),
+	      .state(state),
+	      .mb(mb),
+	      .io_data_in(io_data_out),
+	      .io_data_out(io_data_in),
+	      .io_select(io_select),
+	      .io_data_avail(io_data_avail),
+	      .io_interrupt(io_interrupt),
+	      .io_skip(io_skip),
+   	      .io_clear_ac(io_clear_ac),
+   	      .io_ram_read_req(ext_ram_read_req),
+	      .io_ram_write_req(ext_ram_write_req),
+	      .io_ram_done(ext_ram_done),
+	      .io_ram_ma(ext_ram_ma),
+	      .io_ram_in(ext_ram_in),
+	      .io_ram_out(ext_ram_out),
+   	      .ide_dior(ide_dior),
+	      .ide_diow(ide_diow),
+	      .ide_cs(ide_cs),
+	      .ide_da(ide_da),
+	      .ide_data_in(ide_data_in),
+	      .ide_data_out(ide_data_out),
+	      .rs232_in(rs232_in),
+	      .rs232_out(rs232_out));
+
+   pdp8_ram ram(.clk(clk),
+		.reset(reset), 
+		.addr(ram_addr),
+		.data_in(ram_data_in),
+		.data_out(ram_data_out),
+		.rd(ram_rd),
+   		.wr(ram_wr),
+   		.sram_a(sram_a),
+		.sram_oe_n(sram_oe_n), .sram_we_n(sram_we_n),
+		.sram1_io(sram1_io), .sram1_ce_n(sram1_ce_n),
+		.sram1_ub_n(sram1_ub_n), .sram1_lb_n(sram1_lb_n),
+		.sram2_io(sram2_io), .sram2_ce_n(sram2_ce_n), 
+		.sram2_ub_n(sram2_ub_n), .sram2_lb_n(sram2_lb_n));
+   
+`ifndef use_sim_ram_model
+   ram_s3board sram(.ram_a(sram_a),
+		    .ram_oe_n(sram_oe_n),
+		    .ram_we_n(sram_we_n),
+		    .ram1_io(sram1_io),
+		    .ram1_ce_n(sram1_ce_n),
+		    .ram1_ub_n(sram1_ub_n), .ram1_lb_n(sram1_lb_n),
+		    .ram2_io(sram2_io),
+		    .ram2_ce_n(sram2_ce_n),
+		    .ram2_ub_n(sram2_ub_n), .ram2_lb_n(sram2_lb_n));
+`endif
+   
+   wrap_ide wrap_ide(.clk(clk),
+		     .ide_data_in(ide_data_out),
+		     .ide_data_out(ide_data_in),
+		     .ide_dior(ide_dior),
+		     .ide_diow(ide_diow),
+		     .ide_cs(ide_cs),
+		     .ide_da(ide_da));
+   
+endmodule
+