From 8abc1b644c62544bcff2250681ee78beba103e30 Mon Sep 17 00:00:00 2001 From: brad Date: Sat, 10 Apr 2010 19:27:21 +0000 Subject: [PATCH] changes for data-break --- verif/test_pdp8.v | 96 +++++++++++++++++++------------- verif/test_rf.v | 137 ++++++++++++++++++++++++++++++++++++---------- 2 files changed, 166 insertions(+), 67 deletions(-) diff --git a/verif/test_pdp8.v b/verif/test_pdp8.v index a2e1845..472320d 100644 --- a/verif/test_pdp8.v +++ b/verif/test_pdp8.v @@ -1,5 +1,5 @@ -// run.v -// testing top end for pdp8.v +// test_pdp8.v +// test bench top end for pdp8.v // `include "../rtl/pdp8_tt.v" @@ -33,6 +33,13 @@ module test; wire [3:0] state; wire [11:0] mb; + wire ext_ram_read_req; + wire ext_ram_write_req; + wire [14:0] ext_ram_ma; + wire [11:0] ext_ram_in; + wire ext_ram_done; + wire [11:0] ext_ram_out; + pdp8 cpu(.clk(clk), .reset(reset), .ram_addr(ram_addr), @@ -50,7 +57,13 @@ module test; .switches(switches), .iot(iot), .state(state), - .mb(mb)); + .mb(mb), + .ext_ram_read_req(ext_ram_read_req), + .ext_ram_write_req(ext_ram_write_req), + .ext_ram_done(ext_ram_done), + .ext_ram_ma(ext_ram_ma), + .ext_ram_in(ext_ram_out), + .ext_ram_out(ext_ram_in)); pdp8_io io(.clk(clk), .reset(reset), @@ -63,7 +76,13 @@ module test; .io_data_avail(io_data_avail), .io_interrupt(io_interrupt), .io_skip(io_skip), - .io_clear_ac(io_clear_ac)); + .io_clear_ac(io_clear_ac), + .io_ram_read_req(ext_ram_read_req), + .io_ram_write_req(ext_ram_write_req), + .io_ram_done(ext_ram_done), + .io_ram_ma(ext_ram_ma), + .io_ram_in(ext_ram_in), + .io_ram_out(ext_ram_out)); pdp8_ram ram(.clk(clk), .reset(reset), @@ -94,6 +113,9 @@ module test; switches = 0; max_cycles = 0; + max_cycles = 100; + starting_pc = 12'o0200; + `ifdef __ICARUS__ n = $value$plusargs("pc=%o", arg); if (n > 0) @@ -144,7 +166,7 @@ module test; reset = 1; end - #50 begin + #60 begin reset = 0; end @@ -163,16 +185,17 @@ module test; integer cycle; integer max_cycles; integer sample; - integer showpc; + integer show_pc; + integer show_state; initial begin cycle = 0; sample = 0; - showpc = 0; + show_pc = 0; + show_state = 0; end - always @(posedge cpu.clk) begin if (cpu.state == 4'b0000) @@ -181,30 +204,24 @@ module test; if (sample >= 50000) begin sample = 0; - showpc = 1; + show_pc = 1; end - if (0) showpc = 1; - + if (1) show_pc = 1; + if (0) show_state = 1; + cycle = cycle + 1; if (max_cycles > 0 && cycle >= max_cycles) $finish; -`ifdef xxx - #1 $display("#%d, r%b s%d, pc %o ir%o ma %o mb %o j%b l%b ac %o, i%b/%b", - cycle, cpu.run, cpu.state, cpu.pc, - cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac, - cpu.interrupt_enable, cpu.interrupt); -`else - if (showpc) + if (show_pc) #1 $display("pc %o ir %o l%b ac %o ion %o (IF%o DF%o UF%o SF%o IB%o UB%o) %b", cpu.pc, cpu.mb, cpu.l, cpu.ac, cpu.interrupt_enable, cpu.IF, cpu.DF, cpu.UF, cpu.SF, cpu.IB, cpu.UB, cpu.interrupt_inhibit_delay); - showpc = 0; -`endif + show_pc = 0; end if (cpu.state == 4'b1100) @@ -216,25 +233,26 @@ module test; $finish; end -//`define xx -`ifdef xx - #2 case (state) - 4'b0000: $display("F0"); - 4'b0001: $display("F1"); - 4'b0010: $display("F2"); - 4'b0011: $display("F3"); - 4'b0100: $display("D0"); - 4'b0101: $display("D1"); - 4'b0110: $display("D2"); - 4'b0111: $display("D3"); - 4'b1000: $display("E0"); - 4'b1001: $display("E1"); - 4'b1010: $display("E2 %b%b%b%b%b r%bw%b", - cpu.i_and, cpu.tad, cpu.isz, cpu.dca, cpu.jms, - cpu.ram_rd, cpu.ram_wr); - 4'b1011: $display("E3"); - endcase // case(state) -`endif + if (show_state) + begin + #2 case (state) + 4'b0000: $display("F0"); + 4'b0001: $display("F1"); + 4'b0010: $display("F2"); + 4'b0011: $display("F3"); + 4'b0100: $display("D0"); + 4'b0101: $display("D1"); + 4'b0110: $display("D2"); + 4'b0111: $display("D3"); + 4'b1000: $display("E0"); + 4'b1001: $display("E1"); + 4'b1010: $display("E2 %b%b%b%b%b r%bw%b", + cpu.i_and, cpu.tad, cpu.isz, + cpu.dca, cpu.jms, + cpu.ram_rd, cpu.ram_wr); + 4'b1011: $display("E3"); + endcase // case(state) + end end endmodule diff --git a/verif/test_rf.v b/verif/test_rf.v index b2f4cc1..598f26c 100644 --- a/verif/test_rf.v +++ b/verif/test_rf.v @@ -11,52 +11,133 @@ module test; reg clk, reset; - wire [11:0] io_data_in; wire [11:0] io_data_out; wire io_data_avail; wire io_interrupt; wire io_skip; - wire [5:0] io_select; - - wire iot; - wire [3:0] state; - wire [11:0] mb; + + wire ram_read_req; + wire ram_write_req; + reg ram_done; + + wire [14:0] ram_ma; + wire [11:0] ram_out; + reg [11:0] ram_in; + + reg [5:0] io_select; + reg [11:0] io_data_in; + reg iot; + reg [3:0] state; + reg [11:0] mb_in; pdp8_rf rf(.clk(clk), .reset(reset), .iot(iot), .state(state), - .mb(mb), - .io_data_in(io_data_out), - .io_data_out(io_data_in), + .mb(mb_in), + .io_data_in(io_data_in), + .io_data_out(io_data_out), .io_select(io_select), .io_data_avail(io_data_avail), .io_interrupt(io_interrupt), - .io_skip(io_skip)); + .io_skip(io_skip), + .ram_read_req(ram_read_req), + .ram_write_req(ram_write_req), + .ram_done(ram_done), + .ram_ma(ram_ma), + .ram_in(ram_in), + .ram_out(ram_out)); - initial - begin - $timeformat(-9, 0, "ns", 7); + // + task write_rf_reg; + input [11:0] isn; + input [11:0] data; - $dumpfile("pdp8_rf.vcd"); - $dumpvars(0, test.rf); - end + begin + @(posedge clk); + begin + state = 4'h0; + mb_in = isn; + io_select = isn[8:3]; + io_data_in = data; + iot = 1; + end + #20 state = 4'h1; + #20 state = 4'h2; + #20 state = 4'h3; + #20 begin + state = 4'h0; + iot = 0; + end + end + endtask - initial - begin - clk = 0; - reset = 0; + // + task read_rf_reg; + input [11:0] isn; + output [11:0] data; - #1 begin - reset = 1; - end + begin + @(posedge clk); + begin + state = 4'h0; + mb_in = isn; + io_select = isn[8:3]; + io_data_in = 0; + iot = 1; + end + #20 state = 4'h1; + #20 begin + data = io_data_out; + state = 4'h2; + end + #20 state = 4'h3; + #20 begin + state = 4'h0; + iot = 0; + end + end + endtask - #50 begin - reset = 0; - end + initial + begin + $timeformat(-9, 0, "ns", 7); + + $dumpfile("pdp8_rf.vcd"); + $dumpvars(0, test.rf); + end + + reg [11:0] data; + + initial + begin + clk = 0; + reset = 0; + ram_done = 1; + ram_in = 0; + + #1 begin + reset = 1; + end + + #50 begin + reset = 0; + end + + write_rf_reg(12'o6000, 12'o0000); + write_rf_reg(12'o6601, 12'o0000); + write_rf_reg(12'o6611, 12'o0000); + write_rf_reg(12'o6615, 12'o0000); + write_rf_reg(12'o6641, 12'o0000); + write_rf_reg(12'o6643, 12'o0000); + read_rf_reg(12'o6616, data); + + write_rf_reg(12'o6603, 12'o0000); // DMAR + write_rf_reg(12'o6000, 12'o0000); + write_rf_reg(12'o6000, 12'o0000); - #3000 $finish; - end + #3000 $finish; + end always begin