From 9cf9fbd73a5ba9bc26b83aafd558537d2e0c67a4 Mon Sep 17 00:00:00 2001 From: brad Date: Wed, 3 Jan 2007 12:30:19 +0000 Subject: [PATCH] added basic cpu; simulates correctly --- cpu/Makefile | 36 + cpu/NOTES.txt | 75 ++ cpu/README | 1 + cpu/focal.v | 2740 +++++++++++++++++++++++++++++++++++++++++++++ cpu/maketraces.sh | 1 + cpu/pdp8.v | 728 ++++++++++++ cpu/pdp8_io.v | 419 +++++++ cpu/run.v | 68 ++ 8 files changed, 4068 insertions(+) create mode 100644 cpu/Makefile create mode 100644 cpu/NOTES.txt create mode 100644 cpu/README create mode 100644 cpu/focal.v create mode 100755 cpu/maketraces.sh create mode 100644 cpu/pdp8.v create mode 100644 cpu/pdp8_io.v create mode 100644 cpu/run.v diff --git a/cpu/Makefile b/cpu/Makefile new file mode 100644 index 0000000..1fcdb22 --- /dev/null +++ b/cpu/Makefile @@ -0,0 +1,36 @@ +# +# +# + +IVERILOG=iverilog +VERILOG=cver + +#all: igo +all: go + +pdp8.o: pdp8.v + $(VERILOG) -o pdp8.o $(PARTS) + +irun: $(PARTS) run.v pdp8.v + $(IVERILOG) -o run run.v + +crun: $(PARTS) run.v pdp8.v + $(VERILOG) +change_port_type run.v + echo "exit 0" > run + chmod +x run + +go: crun + ./run + +igo: irun + ./run + +display: + ./maketraces.sh >traces + gtkwave caddr.vcd traces + +snapshot: + (suffix=`date +%Y%m%d`; \ + cd ..; \ + tar cfz pdp8_verilog_$$suffix.tar.gz pdp8/*.v pdp8/Makefile ; \ + mv pdp8_verilog* ~/html/heeltoe/html/download/pdp8) diff --git a/cpu/NOTES.txt b/cpu/NOTES.txt new file mode 100644 index 0000000..83dfde2 --- /dev/null +++ b/cpu/NOTES.txt @@ -0,0 +1,75 @@ +DEC-8I-H8NA-D KT8/I Time-Sharing Option Functional Description +DEC-8I-HOCA-D KE8/I Extended Arithmetic Element + +interrupt occurs here + + 510 00516 7141 CLL CIA + 511 00517 1155 TAD LASTV + 512 00520 7630 SZL CLA + 513 00521 4526 ERROR /STORAGE FILLED BY PUSHDOWN LIST + + +6000 PWS The contents of the AC register are loaded into the SW +register. This instruction performs no operation if the IM +flag is 1. + +6001 ION The IE flag is set to 1, enabling interrupts, after a one +instruction delay. + +6002 IOF The IE flag is set to 0, disabling interrupts. + +6003 PSI Skip if the IE flag is 1. This instruction performs no +operation if the IM flag is 1. + +6004 PAI The contents of the IB register are loaded into the IF +register, and the II flag is set to 0, just as if a JMP or +JMS was executed when the IM flag is 1. This instruction +performs no operation if the IM flag is 1. + +6005 PAS The contents of the DF register are loaded into bits +[03..05] of the SF register, and the contents of the IF +register are loaded into bits [00..02] of the SF register, +just as they would be loaded on an interrupt. This +instruction performs no operation of the IM flag is 1. + +6006 PDX The DM flag is set to 1 for the execution of the next +instruction. This instruction executes normally if IM is 1, +but since DM is 1 anytime IM is 1, it effectively performs +no operation. + +6007 PEX The IM flag is set to 1, switching the CPU into normal mode, +after a one instruction delay. This instruction executes +notmally if IM is 1, but effectively performs no operation. + +62x1 CDF Bits [06..08] of the instruction are loaded into the DF +register. +62x2 CIF Bits [06..08] of the instruction are loaded into the IB +register, and the II flag is set to 1. The contents of the +IB register will be loaded into the IF register, and the II +flag will be set to 0, when the next JMP or JMS instruction +is executed. The reload happens after any instruction and/or +indirect address words are read, but before the JMS writes +its return address; the return address is written to the new +instruction field. The II flag blocks interrupts between the +CIF and the JMP/JMS (page 53 of the 1970 small computer +handbook describes the effect of the II flag, even though +the flag itself is not described clearly). + +6214 RDF The contents of the DF register are logically ORed into +bits [06..08] of the AC register. + +6224 RIF The contents of the IF register are logically ORed into +bits [06..08] of the AC register. + +6234 RIB The contents of the SF register are logically ORed into +bits [06..11] of the AC register; if the AC register is +initially 0, then bits [09..11] of the AC register get the +value which was in the DF register at the time of the last +interrupt, and bits [06..08] of the AC register get the +value which was in the IF register at the time of the last +interrupt. + +6244 RMF Bits [03..05] of the SF register are loaded into the DF +register, bits [00..02] of the SF register are loaded into +the IB register, and the II flag is set to 1. The next JMP +or JMS instruction completes the restore. diff --git a/cpu/README b/cpu/README new file mode 100644 index 0000000..908f0b6 --- /dev/null +++ b/cpu/README @@ -0,0 +1 @@ +focal.v -cd win \ No newline at end of file diff --git a/cpu/focal.v b/cpu/focal.v new file mode 100644 index 0000000..68a25cd --- /dev/null +++ b/cpu/focal.v @@ -0,0 +1,2740 @@ +ram[12'o1] = 12'o5402; +ram[12'o2] = 12'o2603; +ram[12'o3] = 12'o7477; +ram[12'o4] = 12'o0; +ram[12'o5] = 12'o13; +ram[12'o6] = 12'o100; +ram[12'o7] = 12'o6600; +ram[12'o10] = 12'o0; +ram[12'o11] = 12'o0; +ram[12'o12] = 12'o0; +ram[12'o13] = 12'o0; +ram[12'o14] = 12'o3377; +ram[12'o15] = 12'o200; +ram[12'o16] = 12'o0; +ram[12'o17] = 12'o3430; +ram[12'o20] = 12'o0; +ram[12'o21] = 12'o0; +ram[12'o22] = 12'o256; +ram[12'o23] = 12'o7701; +ram[12'o24] = 12'o7600; +ram[12'o25] = 12'o7760; +ram[12'o26] = 12'o177; +ram[12'o27] = 12'o5577; +ram[12'o30] = 12'o7332; +ram[12'o31] = 12'o17; +ram[12'o32] = 12'o277; +ram[12'o33] = 12'o240; +ram[12'o34] = 12'o7776; +ram[12'o35] = 12'o2; +ram[12'o36] = 12'o260; +ram[12'o37] = 12'o0; +ram[12'o40] = 12'o0; +ram[12'o41] = 12'o0; +ram[12'o42] = 12'o0; +ram[12'o43] = 12'o0; +ram[12'o44] = 12'o0; +ram[12'o45] = 12'o0; +ram[12'o46] = 12'o0; +ram[12'o47] = 12'o0; +ram[12'o50] = 12'o6676; +ram[12'o51] = 12'o10; +ram[12'o52] = 12'o7311; +ram[12'o53] = 12'o0; +ram[12'o54] = 12'o337; +ram[12'o55] = 12'o214; +ram[12'o56] = 12'o207; +ram[12'o57] = 12'o212; +ram[12'o60] = 12'o215; +ram[12'o61] = 12'o0; +ram[12'o62] = 12'o7700; +ram[12'o63] = 12'o7540; +ram[12'o64] = 12'o7522; +ram[12'o65] = 12'o7563; +ram[12'o66] = 12'o7775; +ram[12'o67] = 12'o7773; +ram[12'o70] = 12'o7767; +ram[12'o71] = 12'o77; +ram[12'o72] = 12'o6170; +ram[12'o73] = 12'o5600; +ram[12'o74] = 12'o2527; +ram[12'o75] = 12'o3420; +ram[12'o76] = 12'o3432; +ram[12'o77] = 12'o3432; +ram[12'o100] = 12'o2056; +ram[12'o101] = 12'o523; +ram[12'o102] = 12'o1556; +ram[12'o103] = 12'o501; +ram[12'o104] = 12'o532; +ram[12'o105] = 12'o550; +ram[12'o106] = 12'o2315; +ram[12'o107] = 12'o3023; +ram[12'o110] = 12'o1333; +ram[12'o111] = 12'o733; +ram[12'o112] = 12'o2477; +ram[12'o113] = 12'o2463; +ram[12'o114] = 12'o6151; +ram[12'o115] = 12'o312; +ram[12'o116] = 12'o2265; +ram[12'o117] = 12'o2417; +ram[12'o120] = 12'o305; +ram[12'o121] = 12'o1524; +ram[12'o122] = 12'o1533; +ram[12'o123] = 12'o2077; +ram[12'o124] = 12'o2451; +ram[12'o125] = 12'o713; +ram[12'o126] = 12'o2736; +ram[12'o127] = 12'o0; +ram[12'o130] = 12'o0; +ram[12'o131] = 12'o0; +ram[12'o132] = 12'o7760; +ram[12'o133] = 12'o4; +ram[12'o134] = 12'o3432; +ram[12'o135] = 12'o0; +ram[12'o136] = 12'o0; +ram[12'o137] = 12'o2675; +ram[12'o140] = 12'o2665; +ram[12'o141] = 12'o1; +ram[12'o142] = 12'o215; +ram[12'o143] = 12'o0; +ram[12'o144] = 12'o5; +ram[12'o145] = 12'o1575; +ram[12'o146] = 12'o0; +ram[12'o147] = 12'o0; +ram[12'o150] = 12'o0; +ram[12'o151] = 12'o1; +ram[12'o152] = 12'o1; +ram[12'o153] = 12'o0; +ram[12'o154] = 12'o0; +ram[12'o155] = 12'o3432; +ram[12'o156] = 12'o0; +ram[12'o157] = 12'o0; +ram[12'o160] = 12'o2034; +ram[12'o161] = 12'o2463; +ram[12'o162] = 12'o0; +ram[12'o163] = 12'o0; +ram[12'o164] = 12'o0; +ram[12'o165] = 12'o2514; +ram[12'o176] = 12'o3432; +ram[12'o177] = 12'o7610; +ram[12'o200] = 12'o5576; +ram[12'o201] = 12'o1227; +ram[12'o202] = 12'o3145; +ram[12'o203] = 12'o3151; +ram[12'o204] = 12'o1226; +ram[12'o205] = 12'o3013; +ram[12'o206] = 12'o2152; +ram[12'o207] = 12'o3061; +ram[12'o210] = 12'o1054; +ram[12'o211] = 12'o4512; +ram[12'o212] = 12'o1074; +ram[12'o213] = 12'o3010; +ram[12'o214] = 12'o3136; +ram[12'o215] = 12'o1074; +ram[12'o216] = 12'o3153; +ram[12'o217] = 12'o4513; +ram[12'o220] = 12'o4510; +ram[12'o221] = 12'o53; +ram[12'o222] = 12'o510; +ram[12'o223] = 12'o4507; +ram[12'o224] = 12'o5217; +ram[12'o225] = 12'o4000; +ram[12'o226] = 12'o2612; +ram[12'o227] = 12'o1575; +ram[12'o230] = 12'o4507; +ram[12'o231] = 12'o4507; +ram[12'o232] = 12'o1074; +ram[12'o233] = 12'o3017; +ram[12'o234] = 12'o3020; +ram[12'o235] = 12'o4506; +ram[12'o236] = 12'o1027; +ram[12'o237] = 12'o3013; +ram[12'o240] = 12'o4521; +ram[12'o241] = 12'o4522; +ram[12'o242] = 12'o4526; +ram[12'o243] = 12'o5274; +ram[12'o244] = 12'o6002; +ram[12'o245] = 12'o2151; +ram[12'o246] = 12'o4515; +ram[12'o247] = 12'o1141; +ram[12'o250] = 12'o1225; +ram[12'o251] = 12'o7640; +ram[12'o252] = 12'o4526; +ram[12'o253] = 12'o1134; +ram[12'o254] = 12'o3010; +ram[12'o255] = 12'o3136; +ram[12'o256] = 12'o1143; +ram[12'o257] = 12'o3410; +ram[12'o260] = 12'o4521; +ram[12'o261] = 12'o7410; +ram[12'o262] = 12'o4506; +ram[12'o263] = 12'o4507; +ram[12'o264] = 12'o1142; +ram[12'o265] = 12'o1065; +ram[12'o266] = 12'o7640; +ram[12'o267] = 12'o5262; +ram[12'o270] = 12'o4501; +ram[12'o271] = 12'o2111; +ram[12'o272] = 12'o4517; +ram[12'o273] = 12'o5177; +ram[12'o274] = 12'o4501; +ram[12'o275] = 12'o616; +ram[12'o276] = 12'o1545; +ram[12'o277] = 12'o7450; +ram[12'o300] = 12'o5177; +ram[12'o301] = 12'o3145; +ram[12'o302] = 12'o1145; +ram[12'o303] = 12'o7001; +ram[12'o304] = 12'o5233; +ram[12'o305] = 12'o0; +ram[12'o306] = 12'o7106; +ram[12'o307] = 12'o7006; +ram[12'o310] = 12'o7006; +ram[12'o311] = 12'o5705; +ram[12'o312] = 12'o0; +ram[12'o313] = 12'o4521; +ram[12'o314] = 12'o1225; +ram[12'o315] = 12'o3141; +ram[12'o316] = 12'o4511; +ram[12'o317] = 12'o6114; +ram[12'o320] = 12'o5370; +ram[12'o321] = 12'o4766; +ram[12'o322] = 12'o4522; +ram[12'o323] = 12'o4506; +ram[12'o324] = 12'o4356; +ram[12'o325] = 12'o7106; +ram[12'o326] = 12'o1127; +ram[12'o327] = 12'o7004; +ram[12'o330] = 12'o4356; +ram[12'o331] = 12'o1143; +ram[12'o332] = 12'o7450; +ram[12'o333] = 12'o3141; +ram[12'o334] = 12'o3143; +ram[12'o335] = 12'o1164; +ram[12'o336] = 12'o7450; +ram[12'o337] = 12'o5347; +ram[12'o340] = 12'o4520; +ram[12'o341] = 12'o7004; +ram[12'o342] = 12'o1143; +ram[12'o343] = 12'o3143; +ram[12'o344] = 12'o1164; +ram[12'o345] = 12'o367; +ram[12'o346] = 12'o5351; +ram[12'o347] = 12'o2141; +ram[12'o350] = 12'o1143; +ram[12'o351] = 12'o7650; +ram[12'o352] = 12'o4522; +ram[12'o353] = 12'o5361; +ram[12'o354] = 12'o5712; +ram[12'o355] = 12'o5361; +ram[12'o356] = 12'o0; +ram[12'o357] = 12'o3143; +ram[12'o360] = 12'o4522; +ram[12'o361] = 12'o4526; +ram[12'o362] = 12'o5331; +ram[12'o363] = 12'o4506; +ram[12'o364] = 12'o1127; +ram[12'o365] = 12'o5756; +ram[12'o366] = 12'o6010; +ram[12'o367] = 12'o7760; +ram[12'o370] = 12'o4501; +ram[12'o371] = 12'o1601; +ram[12'o372] = 12'o4452; +ram[12'o373] = 12'o4503; +ram[12'o374] = 12'o1045; +ram[12'o375] = 12'o7640; +ram[12'o376] = 12'o5361; +ram[12'o377] = 12'o4407; +ram[12'o400] = 12'o7000; +ram[12'o401] = 12'o2560; +ram[12'o402] = 12'o3614; +ram[12'o403] = 12'o3614; +ram[12'o404] = 12'o2615; +ram[12'o405] = 12'o0; +ram[12'o406] = 12'o4450; +ram[12'o407] = 12'o1413; +ram[12'o410] = 12'o3164; +ram[12'o411] = 12'o4452; +ram[12'o412] = 12'o5613; +ram[12'o413] = 12'o332; +ram[12'o414] = 12'o5770; +ram[12'o415] = 12'o5773; +ram[12'o416] = 12'o4515; +ram[12'o417] = 12'o1145; +ram[12'o420] = 12'o4503; +ram[12'o421] = 12'o4504; +ram[12'o422] = 12'o17; +ram[12'o423] = 12'o4504; +ram[12'o424] = 12'o141; +ram[12'o425] = 12'o1141; +ram[12'o426] = 12'o7710; +ram[12'o427] = 12'o5254; +ram[12'o430] = 12'o4516; +ram[12'o431] = 12'o5273; +ram[12'o432] = 12'o4501; +ram[12'o433] = 12'o613; +ram[12'o434] = 12'o4505; +ram[12'o435] = 12'o141; +ram[12'o436] = 12'o1545; +ram[12'o437] = 12'o7450; +ram[12'o440] = 12'o5262; +ram[12'o441] = 12'o7001; +ram[12'o442] = 12'o3154; +ram[12'o443] = 12'o1141; +ram[12'o444] = 12'o7740; +ram[12'o445] = 12'o5251; +ram[12'o446] = 12'o1554; +ram[12'o447] = 12'o4524; +ram[12'o450] = 12'o5262; +ram[12'o451] = 12'o1554; +ram[12'o452] = 12'o3143; +ram[12'o453] = 12'o5223; +ram[12'o454] = 12'o4516; +ram[12'o455] = 12'o4526; +ram[12'o456] = 12'o4501; +ram[12'o457] = 12'o615; +ram[12'o460] = 12'o4505; +ram[12'o461] = 12'o141; +ram[12'o462] = 12'o4505; +ram[12'o463] = 12'o17; +ram[12'o464] = 12'o1413; +ram[12'o465] = 12'o3145; +ram[12'o466] = 12'o4565; +ram[12'o467] = 12'o5266; +ram[12'o470] = 12'o5672; +ram[12'o471] = 12'o5216; +ram[12'o472] = 12'o616; +ram[12'o473] = 12'o1146; +ram[12'o474] = 12'o3011; +ram[12'o475] = 12'o1411; +ram[12'o476] = 12'o4524; +ram[12'o477] = 12'o4526; +ram[12'o500] = 12'o5232; +ram[12'o501] = 12'o0; +ram[12'o502] = 12'o3332; +ram[12'o503] = 12'o7040; +ram[12'o504] = 12'o4310; +ram[12'o505] = 12'o1332; +ram[12'o506] = 12'o3416; +ram[12'o507] = 12'o5701; +ram[12'o510] = 12'o0; +ram[12'o511] = 12'o1013; +ram[12'o512] = 12'o3013; +ram[12'o513] = 12'o1013; +ram[12'o514] = 12'o3016; +ram[12'o515] = 12'o1013; +ram[12'o516] = 12'o7141; +ram[12'o517] = 12'o1155; +ram[12'o520] = 12'o7630; +ram[12'o521] = 12'o4526; +ram[12'o522] = 12'o5710; +ram[12'o523] = 12'o0; +ram[12'o524] = 12'o7201; +ram[12'o525] = 12'o1323; +ram[12'o526] = 12'o4301; +ram[12'o527] = 12'o1723; +ram[12'o530] = 12'o3323; +ram[12'o531] = 12'o5723; +ram[12'o532] = 12'o0; +ram[12'o533] = 12'o7240; +ram[12'o534] = 12'o1732; +ram[12'o535] = 12'o3011; +ram[12'o536] = 12'o2332; +ram[12'o537] = 12'o1066; +ram[12'o540] = 12'o4310; +ram[12'o541] = 12'o1411; +ram[12'o542] = 12'o3416; +ram[12'o543] = 12'o1411; +ram[12'o544] = 12'o3416; +ram[12'o545] = 12'o1411; +ram[12'o546] = 12'o3416; +ram[12'o547] = 12'o5732; +ram[12'o550] = 12'o0; +ram[12'o551] = 12'o7240; +ram[12'o552] = 12'o1750; +ram[12'o553] = 12'o2350; +ram[12'o554] = 12'o3011; +ram[12'o555] = 12'o1413; +ram[12'o556] = 12'o3411; +ram[12'o557] = 12'o1413; +ram[12'o560] = 12'o3411; +ram[12'o561] = 12'o1413; +ram[12'o562] = 12'o3411; +ram[12'o563] = 12'o5750; +ram[12'o564] = 12'o212; +ram[12'o565] = 12'o223; +ram[12'o566] = 12'o223; +ram[12'o567] = 12'o217; +ram[12'o570] = 12'o230; +ram[12'o571] = 12'o2053; +ram[12'o572] = 12'o7535; +ram[12'o573] = 12'o1156; +ram[12'o574] = 12'o1145; +ram[12'o575] = 12'o7351; +ram[12'o576] = 12'o1153; +ram[12'o577] = 12'o2414; +ram[12'o600] = 12'o2735; +ram[12'o601] = 12'o2735; +ram[12'o602] = 12'o2735; +ram[12'o603] = 12'o2735; +ram[12'o604] = 12'o2735; +ram[12'o605] = 12'o7462; +ram[12'o606] = 12'o2735; +ram[12'o607] = 12'o7472; +ram[12'o610] = 12'o4515; +ram[12'o611] = 12'o4516; +ram[12'o612] = 12'o4526; +ram[12'o613] = 12'o1146; +ram[12'o614] = 12'o3145; +ram[12'o615] = 12'o4506; +ram[12'o616] = 12'o4511; +ram[12'o617] = 12'o57; +ram[12'o620] = 12'o5502; +ram[12'o621] = 12'o4511; +ram[12'o622] = 12'o1140; +ram[12'o623] = 12'o5215; +ram[12'o624] = 12'o1142; +ram[12'o625] = 12'o4503; +ram[12'o626] = 12'o4506; +ram[12'o627] = 12'o4511; +ram[12'o630] = 12'o2002; +ram[12'o631] = 12'o7410; +ram[12'o632] = 12'o5226; +ram[12'o633] = 12'o4521; +ram[12'o634] = 12'o1413; +ram[12'o635] = 12'o4510; +ram[12'o636] = 12'o755; +ram[12'o637] = 12'o206; +ram[12'o640] = 12'o4526; +ram[12'o641] = 12'o4711; +ram[12'o642] = 12'o4515; +ram[12'o643] = 12'o2151; +ram[12'o644] = 12'o4516; +ram[12'o645] = 12'o5274; +ram[12'o646] = 12'o1143; +ram[12'o647] = 12'o7640; +ram[12'o650] = 12'o4514; +ram[12'o651] = 12'o4506; +ram[12'o652] = 12'o4512; +ram[12'o653] = 12'o1142; +ram[12'o654] = 12'o1065; +ram[12'o655] = 12'o7640; +ram[12'o656] = 12'o5251; +ram[12'o657] = 12'o1546; +ram[12'o660] = 12'o7450; +ram[12'o661] = 12'o5303; +ram[12'o662] = 12'o7001; +ram[12'o663] = 12'o3154; +ram[12'o664] = 12'o1141; +ram[12'o665] = 12'o7700; +ram[12'o666] = 12'o1554; +ram[12'o667] = 12'o4524; +ram[12'o670] = 12'o5276; +ram[12'o671] = 12'o1554; +ram[12'o672] = 12'o3143; +ram[12'o673] = 12'o5244; +ram[12'o674] = 12'o1146; +ram[12'o675] = 12'o5260; +ram[12'o676] = 12'o1141; +ram[12'o677] = 12'o7750; +ram[12'o700] = 12'o5303; +ram[12'o701] = 12'o4512; +ram[12'o702] = 12'o5271; +ram[12'o703] = 12'o4712; +ram[12'o704] = 12'o3151; +ram[12'o705] = 12'o4565; +ram[12'o706] = 12'o5305; +ram[12'o707] = 12'o5216; +ram[12'o710] = 12'o5241; +ram[12'o711] = 12'o2435; +ram[12'o712] = 12'o2443; +ram[12'o713] = 12'o0; +ram[12'o714] = 12'o4521; +ram[12'o715] = 12'o4511; +ram[12'o716] = 12'o2005; +ram[12'o717] = 12'o5713; +ram[12'o720] = 12'o2313; +ram[12'o721] = 12'o4522; +ram[12'o722] = 12'o5713; +ram[12'o723] = 12'o7410; +ram[12'o724] = 12'o5713; +ram[12'o725] = 12'o1142; +ram[12'o726] = 12'o1207; +ram[12'o727] = 12'o7640; +ram[12'o730] = 12'o2313; +ram[12'o731] = 12'o2313; +ram[12'o732] = 12'o5713; +ram[12'o733] = 12'o0; +ram[12'o734] = 12'o1733; +ram[12'o735] = 12'o3012; +ram[12'o736] = 12'o1412; +ram[12'o737] = 12'o7510; +ram[12'o740] = 12'o5352; +ram[12'o741] = 12'o7041; +ram[12'o742] = 12'o1142; +ram[12'o743] = 12'o7640; +ram[12'o744] = 12'o5336; +ram[12'o745] = 12'o1733; +ram[12'o746] = 12'o7040; +ram[12'o747] = 12'o1012; +ram[12'o750] = 12'o3127; +ram[12'o751] = 12'o7410; +ram[12'o752] = 12'o2333; +ram[12'o753] = 12'o2333; +ram[12'o754] = 12'o7300; +ram[12'o755] = 12'o5733; +ram[12'o756] = 12'o323; +ram[12'o757] = 12'o306; +ram[12'o760] = 12'o311; +ram[12'o761] = 12'o304; +ram[12'o762] = 12'o307; +ram[12'o763] = 12'o303; +ram[12'o764] = 12'o301; +ram[12'o765] = 12'o324; +ram[12'o766] = 12'o314; +ram[12'o767] = 12'o305; +ram[12'o770] = 12'o327; +ram[12'o771] = 12'o315; +ram[12'o772] = 12'o321; +ram[12'o773] = 12'o322; +ram[12'o774] = 12'o317; +ram[12'o775] = 12'o310; +ram[12'o776] = 12'o4511; +ram[12'o777] = 12'o1022; +ram[12'o1000] = 12'o7410; +ram[12'o1001] = 12'o4526; +ram[12'o1002] = 12'o4501; +ram[12'o1003] = 12'o1600; +ram[12'o1004] = 12'o4506; +ram[12'o1005] = 12'o1045; +ram[12'o1006] = 12'o7710; +ram[12'o1007] = 12'o5622; +ram[12'o1010] = 12'o4565; +ram[12'o1011] = 12'o5210; +ram[12'o1012] = 12'o5703; +ram[12'o1013] = 12'o1045; +ram[12'o1014] = 12'o7650; +ram[12'o1015] = 12'o5622; +ram[12'o1016] = 12'o4565; +ram[12'o1017] = 12'o5216; +ram[12'o1020] = 12'o5703; +ram[12'o1021] = 12'o5622; +ram[12'o1022] = 12'o610; +ram[12'o1023] = 12'o250; +ram[12'o1024] = 12'o4501; +ram[12'o1025] = 12'o1404; +ram[12'o1026] = 12'o4521; +ram[12'o1027] = 12'o4511; +ram[12'o1030] = 12'o2024; +ram[12'o1031] = 12'o7410; +ram[12'o1032] = 12'o4526; +ram[12'o1033] = 12'o1154; +ram[12'o1034] = 12'o3332; +ram[12'o1035] = 12'o4501; +ram[12'o1036] = 12'o1600; +ram[12'o1037] = 12'o4407; +ram[12'o1040] = 12'o6732; +ram[12'o1041] = 12'o0; +ram[12'o1042] = 12'o4565; +ram[12'o1043] = 12'o4526; +ram[12'o1044] = 12'o5703; +ram[12'o1045] = 12'o1332; +ram[12'o1046] = 12'o4503; +ram[12'o1047] = 12'o4501; +ram[12'o1050] = 12'o1601; +ram[12'o1051] = 12'o4565; +ram[12'o1052] = 12'o4526; +ram[12'o1053] = 12'o5317; +ram[12'o1054] = 12'o4504; +ram[12'o1055] = 12'o2034; +ram[12'o1056] = 12'o4501; +ram[12'o1057] = 12'o1601; +ram[12'o1060] = 12'o4504; +ram[12'o1061] = 12'o2034; +ram[12'o1062] = 12'o4724; +ram[12'o1063] = 12'o4430; +ram[12'o1064] = 12'o4407; +ram[12'o1065] = 12'o1732; +ram[12'o1066] = 12'o6732; +ram[12'o1067] = 12'o2560; +ram[12'o1070] = 12'o0; +ram[12'o1071] = 12'o1013; +ram[12'o1072] = 12'o1322; +ram[12'o1073] = 12'o3332; +ram[12'o1074] = 12'o1732; +ram[12'o1075] = 12'o7710; +ram[12'o1076] = 12'o4450; +ram[12'o1077] = 12'o1045; +ram[12'o1100] = 12'o7740; +ram[12'o1101] = 12'o5326; +ram[12'o1102] = 12'o4501; +ram[12'o1103] = 12'o616; +ram[12'o1104] = 12'o4725; +ram[12'o1105] = 12'o4505; +ram[12'o1106] = 12'o2034; +ram[12'o1107] = 12'o4505; +ram[12'o1110] = 12'o44; +ram[12'o1111] = 12'o1413; +ram[12'o1112] = 12'o3332; +ram[12'o1113] = 12'o1323; +ram[12'o1114] = 12'o1013; +ram[12'o1115] = 12'o3013; +ram[12'o1116] = 12'o5264; +ram[12'o1117] = 12'o4504; +ram[12'o1120] = 12'o1573; +ram[12'o1121] = 12'o5260; +ram[12'o1122] = 12'o11; +ram[12'o1123] = 12'o7765; +ram[12'o1124] = 12'o2435; +ram[12'o1125] = 12'o2443; +ram[12'o1126] = 12'o1005; +ram[12'o1127] = 12'o1013; +ram[12'o1130] = 12'o3013; +ram[12'o1131] = 12'o5502; +ram[12'o1132] = 12'o0; +ram[12'o1133] = 12'o246; +ram[12'o1134] = 12'o245; +ram[12'o1135] = 12'o242; +ram[12'o1136] = 12'o241; +ram[12'o1137] = 12'o243; +ram[12'o1140] = 12'o244; +ram[12'o1141] = 12'o240; +ram[12'o1142] = 12'o254; +ram[12'o1143] = 12'o273; +ram[12'o1144] = 12'o215; +ram[12'o1145] = 12'o4452; +ram[12'o1146] = 12'o6063; +ram[12'o1147] = 12'o7200; +ram[12'o1150] = 12'o1361; +ram[12'o1151] = 12'o6053; +ram[12'o1152] = 12'o7410; +ram[12'o1153] = 12'o4452; +ram[12'o1154] = 12'o3361; +ram[12'o1155] = 12'o5500; +ram[12'o1156] = 12'o4452; +ram[12'o1157] = 12'o7200; +ram[12'o1160] = 12'o5500; +ram[12'o1161] = 12'o0; +ram[12'o1162] = 12'o1252; +ram[12'o1163] = 12'o1210; +ram[12'o1164] = 12'o1024; +ram[12'o1165] = 12'o1024; +ram[12'o1166] = 12'o776; +ram[12'o1167] = 12'o416; +ram[12'o1170] = 12'o610; +ram[12'o1171] = 12'o620; +ram[12'o1172] = 12'o1206; +ram[12'o1173] = 12'o1207; +ram[12'o1174] = 12'o2735; +ram[12'o1175] = 12'o2226; +ram[12'o1176] = 12'o641; +ram[12'o1177] = 12'o1273; +ram[12'o1200] = 12'o177; +ram[12'o1201] = 12'o1554; +ram[12'o1202] = 12'o6446; +ram[12'o1203] = 12'o3274; +ram[12'o1204] = 12'o3040; +ram[12'o1205] = 12'o3065; +ram[12'o1206] = 12'o7240; +ram[12'o1207] = 12'o3131; +ram[12'o1210] = 12'o3151; +ram[12'o1211] = 12'o4510; +ram[12'o1212] = 12'o1132; +ram[12'o1213] = 12'o426; +ram[12'o1214] = 12'o2131; +ram[12'o1215] = 12'o5227; +ram[12'o1216] = 12'o4501; +ram[12'o1217] = 12'o1404; +ram[12'o1220] = 12'o4636; +ram[12'o1221] = 12'o1233; +ram[12'o1222] = 12'o4512; +ram[12'o1223] = 12'o4626; +ram[12'o1224] = 12'o4637; +ram[12'o1225] = 12'o5206; +ram[12'o1226] = 12'o3306; +ram[12'o1227] = 12'o4501; +ram[12'o1230] = 12'o1601; +ram[12'o1231] = 12'o4565; +ram[12'o1232] = 12'o4526; +ram[12'o1233] = 12'o272; +ram[12'o1234] = 12'o4640; +ram[12'o1235] = 12'o5207; +ram[12'o1236] = 12'o2435; +ram[12'o1237] = 12'o2443; +ram[12'o1240] = 12'o3365; +ram[12'o1241] = 12'o2151; +ram[12'o1242] = 12'o4506; +ram[12'o1243] = 12'o4510; +ram[12'o1244] = 12'o1404; +ram[12'o1245] = 12'o7555; +ram[12'o1246] = 12'o4512; +ram[12'o1247] = 12'o5242; +ram[12'o1250] = 12'o1060; +ram[12'o1251] = 12'o4512; +ram[12'o1252] = 12'o4506; +ram[12'o1253] = 12'o5210; +ram[12'o1254] = 12'o1060; +ram[12'o1255] = 12'o4537; +ram[12'o1256] = 12'o1015; +ram[12'o1257] = 12'o5251; +ram[12'o1260] = 12'o4506; +ram[12'o1261] = 12'o4672; +ram[12'o1262] = 12'o1164; +ram[12'o1263] = 12'o3051; +ram[12'o1264] = 12'o4522; +ram[12'o1265] = 12'o4506; +ram[12'o1266] = 12'o4672; +ram[12'o1267] = 12'o1164; +ram[12'o1270] = 12'o3133; +ram[12'o1271] = 12'o5210; +ram[12'o1272] = 12'o6010; +ram[12'o1273] = 12'o4515; +ram[12'o1274] = 12'o4516; +ram[12'o1275] = 12'o4526; +ram[12'o1276] = 12'o1134; +ram[12'o1277] = 12'o3010; +ram[12'o1300] = 12'o3136; +ram[12'o1301] = 12'o1143; +ram[12'o1302] = 12'o7450; +ram[12'o1303] = 12'o5275; +ram[12'o1304] = 12'o3410; +ram[12'o1305] = 12'o1010; +ram[12'o1306] = 12'o3153; +ram[12'o1307] = 12'o4540; +ram[12'o1310] = 12'o3061; +ram[12'o1311] = 12'o2151; +ram[12'o1312] = 12'o4506; +ram[12'o1313] = 12'o4512; +ram[12'o1314] = 12'o4510; +ram[12'o1315] = 12'o57; +ram[12'o1316] = 12'o1322; +ram[12'o1317] = 12'o4507; +ram[12'o1320] = 12'o5312; +ram[12'o1321] = 12'o1134; +ram[12'o1322] = 12'o7001; +ram[12'o1323] = 12'o3010; +ram[12'o1324] = 12'o3136; +ram[12'o1325] = 12'o4513; +ram[12'o1326] = 12'o4510; +ram[12'o1327] = 12'o53; +ram[12'o1330] = 12'o1322; +ram[12'o1331] = 12'o4507; +ram[12'o1332] = 12'o5325; +ram[12'o1333] = 12'o0; +ram[12'o1334] = 12'o7450; +ram[12'o1335] = 12'o1142; +ram[12'o1336] = 12'o7041; +ram[12'o1337] = 12'o3157; +ram[12'o1340] = 12'o1733; +ram[12'o1341] = 12'o2333; +ram[12'o1342] = 12'o3012; +ram[12'o1343] = 12'o1412; +ram[12'o1344] = 12'o7510; +ram[12'o1345] = 12'o5357; +ram[12'o1346] = 12'o1157; +ram[12'o1347] = 12'o7640; +ram[12'o1350] = 12'o5343; +ram[12'o1351] = 12'o1012; +ram[12'o1352] = 12'o1733; +ram[12'o1353] = 12'o3333; +ram[12'o1354] = 12'o1733; +ram[12'o1355] = 12'o3333; +ram[12'o1356] = 12'o7410; +ram[12'o1357] = 12'o2333; +ram[12'o1360] = 12'o7300; +ram[12'o1361] = 12'o5733; +ram[12'o1362] = 12'o4501; +ram[12'o1363] = 12'o1600; +ram[12'o1364] = 12'o4452; +ram[12'o1365] = 12'o7141; +ram[12'o1366] = 12'o7001; +ram[12'o1367] = 12'o1053; +ram[12'o1370] = 12'o7630; +ram[12'o1371] = 12'o5210; +ram[12'o1372] = 12'o1033; +ram[12'o1373] = 12'o4512; +ram[12'o1374] = 12'o1046; +ram[12'o1375] = 12'o5365; +ram[12'o1376] = 12'o1321; +ram[12'o1377] = 12'o1312; +ram[12'o1400] = 12'o1307; +ram[12'o1401] = 12'o1310; +ram[12'o1402] = 12'o263; +ram[12'o1403] = 12'o1331; +ram[12'o1404] = 12'o4525; +ram[12'o1405] = 12'o242; +ram[12'o1406] = 12'o215; +ram[12'o1407] = 12'o4526; +ram[12'o1410] = 12'o7240; +ram[12'o1411] = 12'o4503; +ram[12'o1412] = 12'o3136; +ram[12'o1413] = 12'o4507; +ram[12'o1414] = 12'o4506; +ram[12'o1415] = 12'o4511; +ram[12'o1416] = 12'o2005; +ram[12'o1417] = 12'o5222; +ram[12'o1420] = 12'o1142; +ram[12'o1421] = 12'o71; +ram[12'o1422] = 12'o1135; +ram[12'o1423] = 12'o4503; +ram[12'o1424] = 12'o4511; +ram[12'o1425] = 12'o2005; +ram[12'o1426] = 12'o5231; +ram[12'o1427] = 12'o4506; +ram[12'o1430] = 12'o5224; +ram[12'o1431] = 12'o4523; +ram[12'o1432] = 12'o5243; +ram[12'o1433] = 12'o1130; +ram[12'o1434] = 12'o4503; +ram[12'o1435] = 12'o4501; +ram[12'o1436] = 12'o1600; +ram[12'o1437] = 12'o4506; +ram[12'o1440] = 12'o1413; +ram[12'o1441] = 12'o3130; +ram[12'o1442] = 12'o4452; +ram[12'o1443] = 12'o3324; +ram[12'o1444] = 12'o1413; +ram[12'o1445] = 12'o3135; +ram[12'o1446] = 12'o1134; +ram[12'o1447] = 12'o3154; +ram[12'o1450] = 12'o1154; +ram[12'o1451] = 12'o3011; +ram[12'o1452] = 12'o1154; +ram[12'o1453] = 12'o7041; +ram[12'o1454] = 12'o1155; +ram[12'o1455] = 12'o7750; +ram[12'o1456] = 12'o5267; +ram[12'o1457] = 12'o1554; +ram[12'o1460] = 12'o7041; +ram[12'o1461] = 12'o1135; +ram[12'o1462] = 12'o7650; +ram[12'o1463] = 12'o5312; +ram[12'o1464] = 12'o1154; +ram[12'o1465] = 12'o1144; +ram[12'o1466] = 12'o5247; +ram[12'o1467] = 12'o2413; +ram[12'o1470] = 12'o4526; +ram[12'o1471] = 12'o1155; +ram[12'o1472] = 12'o1005; +ram[12'o1473] = 12'o7141; +ram[12'o1474] = 12'o1013; +ram[12'o1475] = 12'o7620; +ram[12'o1476] = 12'o4526; +ram[12'o1477] = 12'o1155; +ram[12'o1500] = 12'o1144; +ram[12'o1501] = 12'o3155; +ram[12'o1502] = 12'o1135; +ram[12'o1503] = 12'o3554; +ram[12'o1504] = 12'o1324; +ram[12'o1505] = 12'o3411; +ram[12'o1506] = 12'o3411; +ram[12'o1507] = 12'o3411; +ram[12'o1510] = 12'o3411; +ram[12'o1511] = 12'o5320; +ram[12'o1512] = 12'o1411; +ram[12'o1513] = 12'o7041; +ram[12'o1514] = 12'o1324; +ram[12'o1515] = 12'o7640; +ram[12'o1516] = 12'o5264; +ram[12'o1517] = 12'o2013; +ram[12'o1520] = 12'o2154; +ram[12'o1521] = 12'o2154; +ram[12'o1522] = 12'o5502; +ram[12'o1523] = 12'o1575; +ram[12'o1524] = 12'o0; +ram[12'o1525] = 12'o1142; +ram[12'o1526] = 12'o1063; +ram[12'o1527] = 12'o7640; +ram[12'o1530] = 12'o5724; +ram[12'o1531] = 12'o4506; +ram[12'o1532] = 12'o5325; +ram[12'o1533] = 12'o0; +ram[12'o1534] = 12'o1142; +ram[12'o1535] = 12'o1064; +ram[12'o1536] = 12'o7440; +ram[12'o1537] = 12'o2333; +ram[12'o1540] = 12'o1352; +ram[12'o1541] = 12'o7500; +ram[12'o1542] = 12'o5350; +ram[12'o1543] = 12'o1353; +ram[12'o1544] = 12'o7510; +ram[12'o1545] = 12'o5350; +ram[12'o1546] = 12'o3127; +ram[12'o1547] = 12'o2333; +ram[12'o1550] = 12'o7300; +ram[12'o1551] = 12'o5733; +ram[12'o1552] = 12'o7764; +ram[12'o1553] = 12'o12; +ram[12'o1554] = 12'o1323; +ram[12'o1555] = 12'o3145; +ram[12'o1556] = 12'o1413; +ram[12'o1557] = 12'o3157; +ram[12'o1560] = 12'o5557; +ram[12'o1561] = 12'o1362; +ram[12'o1562] = 12'o1260; +ram[12'o1563] = 12'o1241; +ram[12'o1564] = 12'o1250; +ram[12'o1565] = 12'o1254; +ram[12'o1566] = 12'o3125; +ram[12'o1567] = 12'o1252; +ram[12'o1570] = 12'o1252; +ram[12'o1571] = 12'o615; +ram[12'o1572] = 12'o620; +ram[12'o1573] = 12'o1; +ram[12'o1574] = 12'o2000; +ram[12'o1575] = 12'o0; +ram[12'o1576] = 12'o0; +ram[12'o1577] = 12'o0; +ram[12'o1600] = 12'o4506; +ram[12'o1601] = 12'o3130; +ram[12'o1602] = 12'o4525; +ram[12'o1603] = 12'o5215; +ram[12'o1604] = 12'o5332; +ram[12'o1605] = 12'o5342; +ram[12'o1606] = 12'o4501; +ram[12'o1607] = 12'o1411; +ram[12'o1610] = 12'o4525; +ram[12'o1611] = 12'o5236; +ram[12'o1612] = 12'o212; +ram[12'o1613] = 12'o377; +ram[12'o1614] = 12'o4526; +ram[12'o1615] = 12'o4504; +ram[12'o1616] = 12'o1575; +ram[12'o1617] = 12'o4505; +ram[12'o1620] = 12'o2034; +ram[12'o1621] = 12'o1160; +ram[12'o1622] = 12'o3154; +ram[12'o1623] = 12'o1034; +ram[12'o1624] = 12'o1127; +ram[12'o1625] = 12'o7450; +ram[12'o1626] = 12'o5241; +ram[12'o1627] = 12'o7001; +ram[12'o1630] = 12'o7650; +ram[12'o1631] = 12'o5323; +ram[12'o1632] = 12'o1127; +ram[12'o1633] = 12'o1070; +ram[12'o1634] = 12'o7710; +ram[12'o1635] = 12'o5353; +ram[12'o1636] = 12'o4523; +ram[12'o1637] = 12'o7410; +ram[12'o1640] = 12'o4526; +ram[12'o1641] = 12'o1127; +ram[12'o1642] = 12'o3147; +ram[12'o1643] = 12'o1147; +ram[12'o1644] = 12'o1070; +ram[12'o1645] = 12'o7700; +ram[12'o1646] = 12'o3147; +ram[12'o1647] = 12'o7201; +ram[12'o1650] = 12'o147; +ram[12'o1651] = 12'o1147; +ram[12'o1652] = 12'o7041; +ram[12'o1653] = 12'o3274; +ram[12'o1654] = 12'o7001; +ram[12'o1655] = 12'o130; +ram[12'o1656] = 12'o1130; +ram[12'o1657] = 12'o1274; +ram[12'o1660] = 12'o7710; +ram[12'o1661] = 12'o5310; +ram[12'o1662] = 12'o1130; +ram[12'o1663] = 12'o1331; +ram[12'o1664] = 12'o3274; +ram[12'o1665] = 12'o1674; +ram[12'o1666] = 12'o3274; +ram[12'o1667] = 12'o1130; +ram[12'o1670] = 12'o7640; +ram[12'o1671] = 12'o4505; +ram[12'o1672] = 12'o44; +ram[12'o1673] = 12'o4407; +ram[12'o1674] = 12'o0; +ram[12'o1675] = 12'o6560; +ram[12'o1676] = 12'o0; +ram[12'o1677] = 12'o1160; +ram[12'o1700] = 12'o3154; +ram[12'o1701] = 12'o1147; +ram[12'o1702] = 12'o1130; +ram[12'o1703] = 12'o7650; +ram[12'o1704] = 12'o5502; +ram[12'o1705] = 12'o1413; +ram[12'o1706] = 12'o3130; +ram[12'o1707] = 12'o5247; +ram[12'o1710] = 12'o4523; +ram[12'o1711] = 12'o7410; +ram[12'o1712] = 12'o5355; +ram[12'o1713] = 12'o1130; +ram[12'o1714] = 12'o4503; +ram[12'o1715] = 12'o1154; +ram[12'o1716] = 12'o3320; +ram[12'o1717] = 12'o4504; +ram[12'o1720] = 12'o0; +ram[12'o1721] = 12'o1147; +ram[12'o1722] = 12'o3130; +ram[12'o1723] = 12'o4506; +ram[12'o1724] = 12'o4525; +ram[12'o1725] = 12'o5353; +ram[12'o1726] = 12'o5332; +ram[12'o1727] = 12'o5342; +ram[12'o1730] = 12'o5206; +ram[12'o1731] = 12'o2026; +ram[12'o1732] = 12'o4504; +ram[12'o1733] = 12'o44; +ram[12'o1734] = 12'o1160; +ram[12'o1735] = 12'o3154; +ram[12'o1736] = 12'o4473; +ram[12'o1737] = 12'o4505; +ram[12'o1740] = 12'o44; +ram[12'o1741] = 12'o5210; +ram[12'o1742] = 12'o3274; +ram[12'o1743] = 12'o4506; +ram[12'o1744] = 12'o4511; +ram[12'o1745] = 12'o2005; +ram[12'o1746] = 12'o5364; +ram[12'o1747] = 12'o1274; +ram[12'o1750] = 12'o7104; +ram[12'o1751] = 12'o1142; +ram[12'o1752] = 12'o5342; +ram[12'o1753] = 12'o4523; +ram[12'o1754] = 12'o4526; +ram[12'o1755] = 12'o1127; +ram[12'o1756] = 12'o4503; +ram[12'o1757] = 12'o1130; +ram[12'o1760] = 12'o4503; +ram[12'o1761] = 12'o4501; +ram[12'o1762] = 12'o1600; +ram[12'o1763] = 12'o5500; +ram[12'o1764] = 12'o1127; +ram[12'o1765] = 12'o4503; +ram[12'o1766] = 12'o1130; +ram[12'o1767] = 12'o4503; +ram[12'o1770] = 12'o1274; +ram[12'o1771] = 12'o4503; +ram[12'o1772] = 12'o4523; +ram[12'o1773] = 12'o4526; +ram[12'o1774] = 12'o4501; +ram[12'o1775] = 12'o1600; +ram[12'o1776] = 12'o1413; +ram[12'o1777] = 12'o4510; +ram[12'o2000] = 12'o2207; +ram[12'o2001] = 12'o6361; +ram[12'o2002] = 12'o4526; +ram[12'o2003] = 12'o241; +ram[12'o2004] = 12'o242; +ram[12'o2005] = 12'o256; +ram[12'o2006] = 12'o240; +ram[12'o2007] = 12'o253; +ram[12'o2010] = 12'o255; +ram[12'o2011] = 12'o257; +ram[12'o2012] = 12'o252; +ram[12'o2013] = 12'o336; +ram[12'o2014] = 12'o250; +ram[12'o2015] = 12'o333; +ram[12'o2016] = 12'o274; +ram[12'o2017] = 12'o251; +ram[12'o2020] = 12'o335; +ram[12'o2021] = 12'o276; +ram[12'o2022] = 12'o254; +ram[12'o2023] = 12'o273; +ram[12'o2024] = 12'o215; +ram[12'o2025] = 12'o275; +ram[12'o2026] = 12'o5554; +ram[12'o2027] = 12'o1554; +ram[12'o2030] = 12'o2554; +ram[12'o2031] = 12'o4554; +ram[12'o2032] = 12'o3554; +ram[12'o2033] = 12'o554; +ram[12'o2034] = 12'o0; +ram[12'o2035] = 12'o0; +ram[12'o2036] = 12'o0; +ram[12'o2037] = 12'o7056; +ram[12'o2040] = 12'o6473; +ram[12'o2041] = 12'o1740; +ram[12'o2042] = 12'o1354; +ram[12'o2043] = 12'o2454; +ram[12'o2044] = 12'o1154; +ram[12'o2045] = 12'o554; +ram[12'o2046] = 12'o7254; +ram[12'o2047] = 12'o2373; +ram[12'o2050] = 12'o540; +ram[12'o2051] = 12'o177; +ram[12'o2052] = 12'o1500; +ram[12'o2053] = 12'o1045; +ram[12'o2054] = 12'o7710; +ram[12'o2055] = 12'o4450; +ram[12'o2056] = 12'o1413; +ram[12'o2057] = 12'o3130; +ram[12'o2060] = 12'o4407; +ram[12'o2061] = 12'o7000; +ram[12'o2062] = 12'o6234; +ram[12'o2063] = 12'o0; +ram[12'o2064] = 12'o1160; +ram[12'o2065] = 12'o3154; +ram[12'o2066] = 12'o1413; +ram[12'o2067] = 12'o7041; +ram[12'o2070] = 12'o1066; +ram[12'o2071] = 12'o1127; +ram[12'o2072] = 12'o7640; +ram[12'o2073] = 12'o4526; +ram[12'o2074] = 12'o4506; +ram[12'o2075] = 12'o5676; +ram[12'o2076] = 12'o1610; +ram[12'o2077] = 12'o0; +ram[12'o2100] = 12'o1127; +ram[12'o2101] = 12'o1070; +ram[12'o2102] = 12'o7700; +ram[12'o2103] = 12'o5677; +ram[12'o2104] = 12'o1127; +ram[12'o2105] = 12'o1067; +ram[12'o2106] = 12'o7740; +ram[12'o2107] = 12'o2277; +ram[12'o2110] = 12'o5677; +ram[12'o2111] = 12'o4516; +ram[12'o2112] = 12'o5502; +ram[12'o2113] = 12'o2151; +ram[12'o2114] = 12'o4506; +ram[12'o2115] = 12'o1142; +ram[12'o2116] = 12'o1065; +ram[12'o2117] = 12'o7640; +ram[12'o2120] = 12'o5314; +ram[12'o2121] = 12'o1017; +ram[12'o2122] = 12'o7040; +ram[12'o2123] = 12'o1146; +ram[12'o2124] = 12'o3132; +ram[12'o2125] = 12'o1546; +ram[12'o2126] = 12'o3550; +ram[12'o2127] = 12'o1075; +ram[12'o2130] = 12'o3157; +ram[12'o2131] = 12'o1557; +ram[12'o2132] = 12'o7450; +ram[12'o2133] = 12'o5346; +ram[12'o2134] = 12'o3156; +ram[12'o2135] = 12'o1146; +ram[12'o2136] = 12'o7141; +ram[12'o2137] = 12'o1156; +ram[12'o2140] = 12'o7630; +ram[12'o2141] = 12'o1132; +ram[12'o2142] = 12'o1156; +ram[12'o2143] = 12'o3557; +ram[12'o2144] = 12'o1156; +ram[12'o2145] = 12'o5330; +ram[12'o2146] = 12'o7040; +ram[12'o2147] = 12'o1146; +ram[12'o2150] = 12'o3011; +ram[12'o2151] = 12'o1132; +ram[12'o2152] = 12'o7040; +ram[12'o2153] = 12'o1146; +ram[12'o2154] = 12'o3012; +ram[12'o2155] = 12'o1132; +ram[12'o2156] = 12'o1134; +ram[12'o2157] = 12'o3134; +ram[12'o2160] = 12'o1010; +ram[12'o2161] = 12'o7040; +ram[12'o2162] = 12'o1012; +ram[12'o2163] = 12'o3156; +ram[12'o2164] = 12'o1010; +ram[12'o2165] = 12'o1132; +ram[12'o2166] = 12'o3010; +ram[12'o2167] = 12'o1412; +ram[12'o2170] = 12'o3411; +ram[12'o2171] = 12'o2156; +ram[12'o2172] = 12'o5367; +ram[12'o2173] = 12'o5311; +ram[12'o2174] = 12'o6457; +ram[12'o2175] = 12'o6453; +ram[12'o2176] = 12'o3237; +ram[12'o2177] = 12'o3234; +ram[12'o2200] = 12'o3303; +ram[12'o2201] = 12'o3302; +ram[12'o2202] = 12'o3244; +ram[12'o2203] = 12'o3243; +ram[12'o2204] = 12'o3252; +ram[12'o2205] = 12'o3253; +ram[12'o2206] = 12'o3256; +ram[12'o2207] = 12'o3271; +ram[12'o2210] = 12'o2533; +ram[12'o2211] = 12'o2650; +ram[12'o2212] = 12'o2636; +ram[12'o2213] = 12'o2565; +ram[12'o2214] = 12'o2630; +ram[12'o2215] = 12'o2623; +ram[12'o2216] = 12'o2517; +ram[12'o2217] = 12'o2572; +ram[12'o2220] = 12'o2624; +ram[12'o2221] = 12'o2625; +ram[12'o2222] = 12'o2654; +ram[12'o2223] = 12'o2575; +ram[12'o2224] = 12'o2702; +ram[12'o2225] = 12'o2631; +ram[12'o2226] = 12'o1142; +ram[12'o2227] = 12'o1003; +ram[12'o2230] = 12'o7640; +ram[12'o2231] = 12'o5240; +ram[12'o2232] = 12'o1077; +ram[12'o2233] = 12'o3134; +ram[12'o2234] = 12'o3475; +ram[12'o2235] = 12'o1134; +ram[12'o2236] = 12'o3155; +ram[12'o2237] = 12'o5177; +ram[12'o2240] = 12'o4515; +ram[12'o2241] = 12'o1143; +ram[12'o2242] = 12'o7640; +ram[12'o2243] = 12'o5250; +ram[12'o2244] = 12'o1134; +ram[12'o2245] = 12'o3155; +ram[12'o2246] = 12'o5647; +ram[12'o2247] = 12'o616; +ram[12'o2250] = 12'o1134; +ram[12'o2251] = 12'o3010; +ram[12'o2252] = 12'o4501; +ram[12'o2253] = 12'o2111; +ram[12'o2254] = 12'o2146; +ram[12'o2255] = 12'o1141; +ram[12'o2256] = 12'o7700; +ram[12'o2257] = 12'o1546; +ram[12'o2260] = 12'o4524; +ram[12'o2261] = 12'o5235; +ram[12'o2262] = 12'o1546; +ram[12'o2263] = 12'o3143; +ram[12'o2264] = 12'o5252; +ram[12'o2265] = 12'o0; +ram[12'o2266] = 12'o1075; +ram[12'o2267] = 12'o3150; +ram[12'o2270] = 12'o1075; +ram[12'o2271] = 12'o3146; +ram[12'o2272] = 12'o1146; +ram[12'o2273] = 12'o3012; +ram[12'o2274] = 12'o1143; +ram[12'o2275] = 12'o7041; +ram[12'o2276] = 12'o1412; +ram[12'o2277] = 12'o7450; +ram[12'o2300] = 12'o2265; +ram[12'o2301] = 12'o7700; +ram[12'o2302] = 12'o5310; +ram[12'o2303] = 12'o1146; +ram[12'o2304] = 12'o3150; +ram[12'o2305] = 12'o1546; +ram[12'o2306] = 12'o7440; +ram[12'o2307] = 12'o5271; +ram[12'o2310] = 12'o1146; +ram[12'o2311] = 12'o7001; +ram[12'o2312] = 12'o3017; +ram[12'o2313] = 12'o3020; +ram[12'o2314] = 12'o5665; +ram[12'o2315] = 12'o0; +ram[12'o2316] = 12'o4351; +ram[12'o2317] = 12'o7710; +ram[12'o2320] = 12'o1006; +ram[12'o2321] = 12'o1377; +ram[12'o2322] = 12'o1142; +ram[12'o2323] = 12'o7450; +ram[12'o2324] = 12'o5337; +ram[12'o2325] = 12'o1054; +ram[12'o2326] = 12'o3142; +ram[12'o2327] = 12'o1151; +ram[12'o2330] = 12'o1152; +ram[12'o2331] = 12'o7650; +ram[12'o2332] = 12'o4512; +ram[12'o2333] = 12'o5715; +ram[12'o2334] = 12'o4351; +ram[12'o2335] = 12'o7040; +ram[12'o2336] = 12'o5317; +ram[12'o2337] = 12'o1151; +ram[12'o2340] = 12'o7640; +ram[12'o2341] = 12'o5347; +ram[12'o2342] = 12'o1152; +ram[12'o2343] = 12'o7650; +ram[12'o2344] = 12'o7001; +ram[12'o2345] = 12'o3152; +ram[12'o2346] = 12'o5316; +ram[12'o2347] = 12'o1032; +ram[12'o2350] = 12'o5326; +ram[12'o2351] = 12'o0; +ram[12'o2352] = 12'o2020; +ram[12'o2353] = 12'o5366; +ram[12'o2354] = 12'o1021; +ram[12'o2355] = 12'o71; +ram[12'o2356] = 12'o3142; +ram[12'o2357] = 12'o1142; +ram[12'o2360] = 12'o1023; +ram[12'o2361] = 12'o7650; +ram[12'o2362] = 12'o5334; +ram[12'o2363] = 12'o1142; +ram[12'o2364] = 12'o1376; +ram[12'o2365] = 12'o5751; +ram[12'o2366] = 12'o1417; +ram[12'o2367] = 12'o3021; +ram[12'o2370] = 12'o7040; +ram[12'o2371] = 12'o3020; +ram[12'o2372] = 12'o1021; +ram[12'o2373] = 12'o4520; +ram[12'o2374] = 12'o7004; +ram[12'o2375] = 12'o5355; +ram[12'o2376] = 12'o7740; +ram[12'o2377] = 12'o7641; +ram[12'o2400] = 12'o313; +ram[12'o2401] = 12'o322; +ram[12'o2402] = 12'o324; +ram[12'o2403] = 12'o320; +ram[12'o2404] = 12'o311; +ram[12'o2405] = 12'o303; +ram[12'o2406] = 12'o272; +ram[12'o2407] = 12'o330; +ram[12'o2410] = 12'o305; +ram[12'o2411] = 12'o316; +ram[12'o2412] = 12'o323; +ram[12'o2413] = 12'o315; +ram[12'o2414] = 12'o6004; +ram[12'o2415] = 12'o3045; +ram[12'o2416] = 12'o5500; +ram[12'o2417] = 12'o0; +ram[12'o2420] = 12'o1550; +ram[12'o2421] = 12'o3534; +ram[12'o2422] = 12'o1134; +ram[12'o2423] = 12'o3550; +ram[12'o2424] = 12'o1135; +ram[12'o2425] = 12'o7440; +ram[12'o2426] = 12'o3410; +ram[12'o2427] = 12'o1010; +ram[12'o2430] = 12'o7001; +ram[12'o2431] = 12'o3134; +ram[12'o2432] = 12'o1134; +ram[12'o2433] = 12'o3155; +ram[12'o2434] = 12'o5617; +ram[12'o2435] = 12'o0; +ram[12'o2436] = 12'o4504; +ram[12'o2437] = 12'o17; +ram[12'o2440] = 12'o1142; +ram[12'o2441] = 12'o4503; +ram[12'o2442] = 12'o5635; +ram[12'o2443] = 12'o0; +ram[12'o2444] = 12'o1413; +ram[12'o2445] = 12'o3142; +ram[12'o2446] = 12'o4505; +ram[12'o2447] = 12'o17; +ram[12'o2450] = 12'o5643; +ram[12'o2451] = 12'o0; +ram[12'o2452] = 12'o24; +ram[12'o2453] = 12'o7041; +ram[12'o2454] = 12'o3157; +ram[12'o2455] = 12'o1143; +ram[12'o2456] = 12'o24; +ram[12'o2457] = 12'o1157; +ram[12'o2460] = 12'o7650; +ram[12'o2461] = 12'o2251; +ram[12'o2462] = 12'o5651; +ram[12'o2463] = 12'o0; +ram[12'o2464] = 12'o4540; +ram[12'o2465] = 12'o3142; +ram[12'o2466] = 12'o4511; +ram[12'o2467] = 12'o1611; +ram[12'o2470] = 12'o5663; +ram[12'o2471] = 12'o4512; +ram[12'o2472] = 12'o1142; +ram[12'o2473] = 12'o1024; +ram[12'o2474] = 12'o7640; +ram[12'o2475] = 12'o5663; +ram[12'o2476] = 12'o5264; +ram[12'o2477] = 12'o0; +ram[12'o2500] = 12'o7450; +ram[12'o2501] = 12'o1142; +ram[12'o2502] = 12'o1065; +ram[12'o2503] = 12'o7450; +ram[12'o2504] = 12'o5310; +ram[12'o2505] = 12'o1060; +ram[12'o2506] = 12'o4537; +ram[12'o2507] = 12'o5677; +ram[12'o2510] = 12'o1060; +ram[12'o2511] = 12'o4537; +ram[12'o2512] = 12'o1057; +ram[12'o2513] = 12'o5306; +ram[12'o2514] = 12'o0; +ram[12'o2515] = 12'o4511; +ram[12'o2516] = 12'o1141; +ram[12'o2517] = 12'o7410; +ram[12'o2520] = 12'o5326; +ram[12'o2521] = 12'o1127; +ram[12'o2522] = 12'o2314; +ram[12'o2523] = 12'o7640; +ram[12'o2524] = 12'o5714; +ram[12'o2525] = 12'o2314; +ram[12'o2526] = 12'o4506; +ram[12'o2527] = 12'o5714; +ram[12'o2600] = 12'o0; +ram[12'o2601] = 12'o0; +ram[12'o2602] = 12'o7575; +ram[12'o2603] = 12'o3200; +ram[12'o2604] = 12'o7010; +ram[12'o2605] = 12'o3201; +ram[12'o2606] = 12'o6031; +ram[12'o2607] = 12'o5225; +ram[12'o2610] = 12'o6036; +ram[12'o2611] = 12'o26; +ram[12'o2612] = 12'o1015; +ram[12'o2613] = 12'o3306; +ram[12'o2614] = 12'o1306; +ram[12'o2615] = 12'o1202; +ram[12'o2616] = 12'o7650; +ram[12'o2617] = 12'o5345; +ram[12'o2620] = 12'o1264; +ram[12'o2621] = 12'o7640; +ram[12'o2622] = 12'o4526; +ram[12'o2623] = 12'o1306; +ram[12'o2624] = 12'o3264; +ram[12'o2625] = 12'o6041; +ram[12'o2626] = 12'o5244; +ram[12'o2627] = 12'o6042; +ram[12'o2630] = 12'o3260; +ram[12'o2631] = 12'o1663; +ram[12'o2632] = 12'o7450; +ram[12'o2633] = 12'o5244; +ram[12'o2634] = 12'o6044; +ram[12'o2635] = 12'o3260; +ram[12'o2636] = 12'o3663; +ram[12'o2637] = 12'o1263; +ram[12'o2640] = 12'o7001; +ram[12'o2641] = 12'o31; +ram[12'o2642] = 12'o1261; +ram[12'o2643] = 12'o3263; +ram[12'o2644] = 12'o6244; +ram[12'o2645] = 12'o6101; +ram[12'o2646] = 12'o7000; +ram[12'o2647] = 12'o6011; +ram[12'o2650] = 12'o5253; +ram[12'o2651] = 12'o6012; +ram[12'o2652] = 12'o3037; +ram[12'o2653] = 12'o1201; +ram[12'o2654] = 12'o7104; +ram[12'o2655] = 12'o1200; +ram[12'o2656] = 12'o6001; +ram[12'o2657] = 12'o5400; +ram[12'o2660] = 12'o1; +ram[12'o2661] = 12'o3400; +ram[12'o2662] = 12'o3400; +ram[12'o2663] = 12'o3400; +ram[12'o2664] = 12'o0; +ram[12'o2665] = 12'o0; +ram[12'o2666] = 12'o1264; +ram[12'o2667] = 12'o7550; +ram[12'o2670] = 12'o5266; +ram[12'o2671] = 12'o3275; +ram[12'o2672] = 12'o3264; +ram[12'o2673] = 12'o1275; +ram[12'o2674] = 12'o5665; +ram[12'o2675] = 12'o0; +ram[12'o2676] = 12'o3265; +ram[12'o2677] = 12'o1265; +ram[12'o2700] = 12'o1065; +ram[12'o2701] = 12'o7650; +ram[12'o2702] = 12'o3053; +ram[12'o2703] = 12'o1265; +ram[12'o2704] = 12'o4732; +ram[12'o2705] = 12'o2053; +ram[12'o2706] = 12'o0; +ram[12'o2707] = 12'o6001; +ram[12'o2710] = 12'o1662; +ram[12'o2711] = 12'o7640; +ram[12'o2712] = 12'o5310; +ram[12'o2713] = 12'o1260; +ram[12'o2714] = 12'o7640; +ram[12'o2715] = 12'o5322; +ram[12'o2716] = 12'o1265; +ram[12'o2717] = 12'o6046; +ram[12'o2720] = 12'o3260; +ram[12'o2721] = 12'o5675; +ram[12'o2722] = 12'o1265; +ram[12'o2723] = 12'o3662; +ram[12'o2724] = 12'o1262; +ram[12'o2725] = 12'o7001; +ram[12'o2726] = 12'o31; +ram[12'o2727] = 12'o1261; +ram[12'o2730] = 12'o3262; +ram[12'o2731] = 12'o5675; +ram[12'o2732] = 12'o3014; +ram[12'o2733] = 12'o3225; +ram[12'o2734] = 12'o3203; +ram[12'o2735] = 12'o3336; +ram[12'o2736] = 12'o0; +ram[12'o2737] = 12'o7240; +ram[12'o2740] = 12'o1336; +ram[12'o2741] = 12'o3143; +ram[12'o2742] = 12'o4733; +ram[12'o2743] = 12'o6002; +ram[12'o2744] = 12'o5347; +ram[12'o2745] = 12'o1015; +ram[12'o2746] = 12'o3143; +ram[12'o2747] = 12'o2260; +ram[12'o2750] = 12'o1025; +ram[12'o2751] = 12'o3132; +ram[12'o2752] = 12'o7040; +ram[12'o2753] = 12'o1261; +ram[12'o2754] = 12'o3011; +ram[12'o2755] = 12'o3411; +ram[12'o2756] = 12'o2132; +ram[12'o2757] = 12'o5355; +ram[12'o2760] = 12'o3264; +ram[12'o2761] = 12'o1261; +ram[12'o2762] = 12'o3263; +ram[12'o2763] = 12'o1261; +ram[12'o2764] = 12'o3262; +ram[12'o2765] = 12'o4734; +ram[12'o2766] = 12'o1161; +ram[12'o2767] = 12'o3113; +ram[12'o2770] = 12'o7040; +ram[12'o2771] = 12'o6046; +ram[12'o2772] = 12'o7200; +ram[12'o2773] = 12'o1060; +ram[12'o2774] = 12'o4512; +ram[12'o2775] = 12'o1032; +ram[12'o2776] = 12'o4512; +ram[12'o2777] = 12'o4514; +ram[12'o3000] = 12'o2145; +ram[12'o3001] = 12'o1545; +ram[12'o3002] = 12'o7450; +ram[12'o3003] = 12'o5211; +ram[12'o3004] = 12'o3143; +ram[12'o3005] = 12'o1062; +ram[12'o3006] = 12'o4512; +ram[12'o3007] = 12'o4512; +ram[12'o3010] = 12'o4514; +ram[12'o3011] = 12'o1060; +ram[12'o3012] = 12'o4512; +ram[12'o3013] = 12'o5177; +ram[12'o3014] = 12'o0; +ram[12'o3015] = 12'o4520; +ram[12'o3016] = 12'o7710; +ram[12'o3017] = 12'o7020; +ram[12'o3020] = 12'o7420; +ram[12'o3021] = 12'o2214; +ram[12'o3022] = 12'o5614; +ram[12'o3023] = 12'o0; +ram[12'o3024] = 12'o4510; +ram[12'o3025] = 12'o3055; +ram[12'o3026] = 12'o6126; +ram[12'o3027] = 12'o1142; +ram[12'o3030] = 12'o4214; +ram[12'o3031] = 12'o5234; +ram[12'o3032] = 12'o1071; +ram[12'o3033] = 12'o4242; +ram[12'o3034] = 12'o1142; +ram[12'o3035] = 12'o71; +ram[12'o3036] = 12'o4242; +ram[12'o3037] = 12'o5623; +ram[12'o3040] = 12'o1054; +ram[12'o3041] = 12'o5235; +ram[12'o3042] = 12'o0; +ram[12'o3043] = 12'o2136; +ram[12'o3044] = 12'o5260; +ram[12'o3045] = 12'o1135; +ram[12'o3046] = 12'o3410; +ram[12'o3047] = 12'o1013; +ram[12'o3050] = 12'o7141; +ram[12'o3051] = 12'o1005; +ram[12'o3052] = 12'o1010; +ram[12'o3053] = 12'o7630; +ram[12'o3054] = 12'o4526; +ram[12'o3055] = 12'o5642; +ram[12'o3056] = 12'o277; +ram[12'o3057] = 12'o377; +ram[12'o3060] = 12'o4520; +ram[12'o3061] = 12'o3135; +ram[12'o3062] = 12'o7040; +ram[12'o3063] = 12'o3136; +ram[12'o3064] = 12'o5642; +ram[12'o3065] = 12'o1010; +ram[12'o3066] = 12'o3242; +ram[12'o3067] = 12'o1136; +ram[12'o3070] = 12'o7640; +ram[12'o3071] = 12'o5277; +ram[12'o3072] = 12'o1010; +ram[12'o3073] = 12'o7041; +ram[12'o3074] = 12'o1153; +ram[12'o3075] = 12'o7700; +ram[12'o3076] = 12'o5322; +ram[12'o3077] = 12'o1324; +ram[12'o3100] = 12'o4512; +ram[12'o3101] = 12'o2136; +ram[12'o3102] = 12'o5310; +ram[12'o3103] = 12'o1642; +ram[12'o3104] = 12'o71; +ram[12'o3105] = 12'o1023; +ram[12'o3106] = 12'o7640; +ram[12'o3107] = 12'o5322; +ram[12'o3110] = 12'o1642; +ram[12'o3111] = 12'o62; +ram[12'o3112] = 12'o3135; +ram[12'o3113] = 12'o7040; +ram[12'o3114] = 12'o1010; +ram[12'o3115] = 12'o3010; +ram[12'o3116] = 12'o1135; +ram[12'o3117] = 12'o1006; +ram[12'o3120] = 12'o7640; +ram[12'o3121] = 12'o7040; +ram[12'o3122] = 12'o3136; +ram[12'o3123] = 12'o5623; +ram[12'o3124] = 12'o334; +ram[12'o3125] = 12'o4504; +ram[12'o3126] = 12'o17; +ram[12'o3127] = 12'o7040; +ram[12'o3130] = 12'o1134; +ram[12'o3131] = 12'o3014; +ram[12'o3132] = 12'o1014; +ram[12'o3133] = 12'o7040; +ram[12'o3134] = 12'o1155; +ram[12'o3135] = 12'o7650; +ram[12'o3136] = 12'o5370; +ram[12'o3137] = 12'o1375; +ram[12'o3140] = 12'o3017; +ram[12'o3141] = 12'o3020; +ram[12'o3142] = 12'o1414; +ram[12'o3143] = 12'o3376; +ram[12'o3144] = 12'o4501; +ram[12'o3145] = 12'o1241; +ram[12'o3146] = 12'o1414; +ram[12'o3147] = 12'o4774; +ram[12'o3150] = 12'o4501; +ram[12'o3151] = 12'o1241; +ram[12'o3152] = 12'o1005; +ram[12'o3153] = 12'o3046; +ram[12'o3154] = 12'o4501; +ram[12'o3155] = 12'o1374; +ram[12'o3156] = 12'o2014; +ram[12'o3157] = 12'o4407; +ram[12'o3160] = 12'o5414; +ram[12'o3161] = 12'o0; +ram[12'o3162] = 12'o4472; +ram[12'o3163] = 12'o1060; +ram[12'o3164] = 12'o4512; +ram[12'o3165] = 12'o1014; +ram[12'o3166] = 12'o1035; +ram[12'o3167] = 12'o5331; +ram[12'o3170] = 12'o4505; +ram[12'o3171] = 12'o17; +ram[12'o3172] = 12'o5773; +ram[12'o3173] = 12'o1252; +ram[12'o3174] = 12'o6100; +ram[12'o3175] = 12'o3175; +ram[12'o3176] = 12'o0; +ram[12'o3177] = 12'o5077; +ram[12'o3200] = 12'o1551; +ram[12'o3201] = 12'o7577; +ram[12'o3202] = 12'o1500; +ram[12'o3203] = 12'o0; +ram[12'o3204] = 12'o1220; +ram[12'o3205] = 12'o3621; +ram[12'o3206] = 12'o1621; +ram[12'o3207] = 12'o7001; +ram[12'o3210] = 12'o3622; +ram[12'o3211] = 12'o1622; +ram[12'o3212] = 12'o1035; +ram[12'o3213] = 12'o3623; +ram[12'o3214] = 12'o1623; +ram[12'o3215] = 12'o1035; +ram[12'o3216] = 12'o3624; +ram[12'o3217] = 12'o5603; +ram[12'o3220] = 12'o6041; +ram[12'o3221] = 12'o2625; +ram[12'o3222] = 12'o2627; +ram[12'o3223] = 12'o2634; +ram[12'o3224] = 12'o2717; +ram[12'o3225] = 12'o0; +ram[12'o3226] = 12'o6001; +ram[12'o3227] = 12'o1633; +ram[12'o3230] = 12'o7640; +ram[12'o3231] = 12'o5226; +ram[12'o3232] = 12'o5625; +ram[12'o3233] = 12'o2660; +ram[12'o3234] = 12'o4225; +ram[12'o3235] = 12'o1025; +ram[12'o3236] = 12'o7410; +ram[12'o3237] = 12'o4225; +ram[12'o3240] = 12'o4203; +ram[12'o3241] = 12'o5642; +ram[12'o3242] = 12'o6461; +ram[12'o3243] = 12'o1250; +ram[12'o3244] = 12'o1247; +ram[12'o3245] = 12'o3651; +ram[12'o3246] = 12'o5241; +ram[12'o3247] = 12'o4512; +ram[12'o3250] = 12'o2466; +ram[12'o3251] = 12'o1222; +ram[12'o3252] = 12'o1247; +ram[12'o3253] = 12'o3655; +ram[12'o3254] = 12'o5241; +ram[12'o3255] = 12'o2471; +ram[12'o3256] = 12'o4506; +ram[12'o3257] = 12'o4511; +ram[12'o3260] = 12'o2003; +ram[12'o3261] = 12'o7410; +ram[12'o3262] = 12'o5256; +ram[12'o3263] = 12'o4501; +ram[12'o3264] = 12'o1601; +ram[12'o3265] = 12'o4452; +ram[12'o3266] = 12'o3670; +ram[12'o3267] = 12'o5241; +ram[12'o3270] = 12'o6002; +ram[12'o3271] = 12'o4225; +ram[12'o3272] = 12'o6002; +ram[12'o3273] = 12'o5424; +ram[12'o3274] = 12'o1301; +ram[12'o3275] = 12'o3017; +ram[12'o3276] = 12'o3020; +ram[12'o3277] = 12'o4501; +ram[12'o3300] = 12'o1260; +ram[12'o3301] = 12'o2036; +ram[12'o3302] = 12'o7240; +ram[12'o3303] = 12'o3305; +ram[12'o3304] = 12'o5241; +ram[12'o3305] = 12'o0; +ram[12'o3306] = 12'o0; +ram[12'o3307] = 12'o1154; +ram[12'o3310] = 12'o3225; +ram[12'o3311] = 12'o1305; +ram[12'o3312] = 12'o7650; +ram[12'o3313] = 12'o5323; +ram[12'o3314] = 12'o4513; +ram[12'o3315] = 12'o1142; +ram[12'o3316] = 12'o4430; +ram[12'o3317] = 12'o4407; +ram[12'o3320] = 12'o6625; +ram[12'o3321] = 12'o0; +ram[12'o3322] = 12'o5706; +ram[12'o3323] = 12'o1013; +ram[12'o3324] = 12'o3203; +ram[12'o3325] = 12'o1364; +ram[12'o3326] = 12'o3013; +ram[12'o3327] = 12'o2151; +ram[12'o3330] = 12'o1363; +ram[12'o3331] = 12'o3010; +ram[12'o3332] = 12'o3136; +ram[12'o3333] = 12'o1363; +ram[12'o3334] = 12'o3153; +ram[12'o3335] = 12'o4513; +ram[12'o3336] = 12'o4511; +ram[12'o3337] = 12'o32; +ram[12'o3340] = 12'o5335; +ram[12'o3341] = 12'o4510; +ram[12'o3342] = 12'o5775; +ram[12'o3343] = 12'o774; +ram[12'o3344] = 12'o4507; +ram[12'o3345] = 12'o4513; +ram[12'o3346] = 12'o5341; +ram[12'o3347] = 12'o1060; +ram[12'o3350] = 12'o3142; +ram[12'o3351] = 12'o4507; +ram[12'o3352] = 12'o4507; +ram[12'o3353] = 12'o1203; +ram[12'o3354] = 12'o3013; +ram[12'o3355] = 12'o1363; +ram[12'o3356] = 12'o3017; +ram[12'o3357] = 12'o3020; +ram[12'o3360] = 12'o4501; +ram[12'o3361] = 12'o1600; +ram[12'o3362] = 12'o5317; +ram[12'o3363] = 12'o7550; +ram[12'o3364] = 12'o7612; +ram[12'o3365] = 12'o0; +ram[12'o3366] = 12'o1305; +ram[12'o3367] = 12'o7640; +ram[12'o3370] = 12'o5373; +ram[12'o3371] = 12'o4472; +ram[12'o3372] = 12'o5765; +ram[12'o3373] = 12'o4452; +ram[12'o3374] = 12'o7450; +ram[12'o3375] = 12'o7130; +ram[12'o3376] = 12'o4537; +ram[12'o3377] = 12'o5765; +ram[12'o3420] = 12'o0; +ram[12'o3421] = 12'o0; +ram[12'o3422] = 12'o355; +ram[12'o3423] = 12'o617; +ram[12'o3424] = 12'o301; +ram[12'o3425] = 12'o1454; +ram[12'o3426] = 12'o4040; +ram[12'o3427] = 12'o6557; +ram[12'o3430] = 12'o6671; +ram[12'o3431] = 12'o7715; +ram[12'o3432] = 12'o7300; +ram[12'o3433] = 12'o1377; +ram[12'o3434] = 12'o3176; +ram[12'o3435] = 12'o6002; +ram[12'o3436] = 12'o6022; +ram[12'o3437] = 12'o6032; +ram[12'o3440] = 12'o6203; +ram[12'o3441] = 12'o6402; +ram[12'o3442] = 12'o6412; +ram[12'o3443] = 12'o6422; +ram[12'o3444] = 12'o6432; +ram[12'o3445] = 12'o6442; +ram[12'o3446] = 12'o6452; +ram[12'o3447] = 12'o6462; +ram[12'o3450] = 12'o6472; +ram[12'o3451] = 12'o6764; +ram[12'o3452] = 12'o6772; +ram[12'o3453] = 12'o7200; +ram[12'o3454] = 12'o6046; +ram[12'o3455] = 12'o3414; +ram[12'o3456] = 12'o2376; +ram[12'o3457] = 12'o5255; +ram[12'o3460] = 12'o1027; +ram[12'o3461] = 12'o3013; +ram[12'o3462] = 12'o6001; +ram[12'o3463] = 12'o4512; +ram[12'o3464] = 12'o4512; +ram[12'o3465] = 12'o4512; +ram[12'o3466] = 12'o4501; +ram[12'o3467] = 12'o641; +ram[12'o3470] = 12'o5671; +ram[12'o3471] = 12'o2232; +ram[12'o3576] = 12'o7760; +ram[12'o3577] = 12'o2746; +ram[12'o5600] = 12'o0; +ram[12'o5601] = 12'o4430; +ram[12'o5602] = 12'o3364; +ram[12'o5603] = 12'o7040; +ram[12'o5604] = 12'o3260; +ram[12'o5605] = 12'o1363; +ram[12'o5606] = 12'o3044; +ram[12'o5607] = 12'o4755; +ram[12'o5610] = 12'o3365; +ram[12'o5611] = 12'o5215; +ram[12'o5612] = 12'o2260; +ram[12'o5613] = 12'o4526; +ram[12'o5614] = 12'o4506; +ram[12'o5615] = 12'o4522; +ram[12'o5616] = 12'o5212; +ram[12'o5617] = 12'o5250; +ram[12'o5620] = 12'o1260; +ram[12'o5621] = 12'o7700; +ram[12'o5622] = 12'o7040; +ram[12'o5623] = 12'o1364; +ram[12'o5624] = 12'o3364; +ram[12'o5625] = 12'o4342; +ram[12'o5626] = 12'o1127; +ram[12'o5627] = 12'o3043; +ram[12'o5630] = 12'o3042; +ram[12'o5631] = 12'o3041; +ram[12'o5632] = 12'o4313; +ram[12'o5633] = 12'o1162; +ram[12'o5634] = 12'o7640; +ram[12'o5635] = 12'o5241; +ram[12'o5636] = 12'o1045; +ram[12'o5637] = 12'o7700; +ram[12'o5640] = 12'o5214; +ram[12'o5641] = 12'o1361; +ram[12'o5642] = 12'o3760; +ram[12'o5643] = 12'o1162; +ram[12'o5644] = 12'o7110; +ram[12'o5645] = 12'o3162; +ram[12'o5646] = 12'o1045; +ram[12'o5647] = 12'o5762; +ram[12'o5650] = 12'o4511; +ram[12'o5651] = 12'o6145; +ram[12'o5652] = 12'o5301; +ram[12'o5653] = 12'o2365; +ram[12'o5654] = 12'o4450; +ram[12'o5655] = 12'o1366; +ram[12'o5656] = 12'o3260; +ram[12'o5657] = 12'o4407; +ram[12'o5660] = 12'o7000; +ram[12'o5661] = 12'o6554; +ram[12'o5662] = 12'o0; +ram[12'o5663] = 12'o1364; +ram[12'o5664] = 12'o7450; +ram[12'o5665] = 12'o5600; +ram[12'o5666] = 12'o7500; +ram[12'o5667] = 12'o5273; +ram[12'o5670] = 12'o7001; +ram[12'o5671] = 12'o3364; +ram[12'o5672] = 12'o5277; +ram[12'o5673] = 12'o7240; +ram[12'o5674] = 12'o1364; +ram[12'o5675] = 12'o3364; +ram[12'o5676] = 12'o1066; +ram[12'o5677] = 12'o1367; +ram[12'o5700] = 12'o5256; +ram[12'o5701] = 12'o4506; +ram[12'o5702] = 12'o4755; +ram[12'o5703] = 12'o3040; +ram[12'o5704] = 12'o4757; +ram[12'o5705] = 12'o1164; +ram[12'o5706] = 12'o2040; +ram[12'o5707] = 12'o7041; +ram[12'o5710] = 12'o1364; +ram[12'o5711] = 12'o3364; +ram[12'o5712] = 12'o5253; +ram[12'o5713] = 12'o0; +ram[12'o5714] = 12'o7300; +ram[12'o5715] = 12'o1043; +ram[12'o5716] = 12'o1047; +ram[12'o5717] = 12'o3047; +ram[12'o5720] = 12'o7004; +ram[12'o5721] = 12'o1042; +ram[12'o5722] = 12'o1046; +ram[12'o5723] = 12'o3046; +ram[12'o5724] = 12'o7004; +ram[12'o5725] = 12'o1041; +ram[12'o5726] = 12'o1045; +ram[12'o5727] = 12'o3045; +ram[12'o5730] = 12'o7004; +ram[12'o5731] = 12'o1162; +ram[12'o5732] = 12'o3162; +ram[12'o5733] = 12'o5713; +ram[12'o5734] = 12'o0; +ram[12'o5735] = 12'o4756; +ram[12'o5736] = 12'o1162; +ram[12'o5737] = 12'o7004; +ram[12'o5740] = 12'o3162; +ram[12'o5741] = 12'o5734; +ram[12'o5742] = 12'o0; +ram[12'o5743] = 12'o4504; +ram[12'o5744] = 12'o45; +ram[12'o5745] = 12'o4505; +ram[12'o5746] = 12'o41; +ram[12'o5747] = 12'o3162; +ram[12'o5750] = 12'o4334; +ram[12'o5751] = 12'o4334; +ram[12'o5752] = 12'o4313; +ram[12'o5753] = 12'o4334; +ram[12'o5754] = 12'o5742; +ram[12'o5755] = 12'o6030; +ram[12'o5756] = 12'o7037; +ram[12'o5757] = 12'o6010; +ram[12'o5760] = 12'o7251; +ram[12'o5761] = 12'o5633; +ram[12'o5762] = 12'o7256; +ram[12'o5763] = 12'o43; +ram[12'o5764] = 12'o0; +ram[12'o5765] = 12'o0; +ram[12'o5766] = 12'o7000; +ram[12'o5767] = 12'o3373; +ram[12'o5770] = 12'o4; +ram[12'o5771] = 12'o2400; +ram[12'o5772] = 12'o0; +ram[12'o5773] = 12'o7775; +ram[12'o5774] = 12'o3146; +ram[12'o5775] = 12'o3147; +ram[12'o5776] = 12'o215; +ram[12'o5777] = 12'o214; +ram[12'o6000] = 12'o337; +ram[12'o6001] = 12'o254; +ram[12'o6002] = 12'o0; +ram[12'o6003] = 12'o212; +ram[12'o6004] = 12'o6030; +ram[12'o6005] = 12'o7634; +ram[12'o6006] = 12'o7766; +ram[12'o6007] = 12'o7777; +ram[12'o6010] = 12'o0; +ram[12'o6011] = 12'o3164; +ram[12'o6012] = 12'o4522; +ram[12'o6013] = 12'o7000; +ram[12'o6014] = 12'o5610; +ram[12'o6015] = 12'o4506; +ram[12'o6016] = 12'o1164; +ram[12'o6017] = 12'o7106; +ram[12'o6020] = 12'o7530; +ram[12'o6021] = 12'o5226; +ram[12'o6022] = 12'o1164; +ram[12'o6023] = 12'o7004; +ram[12'o6024] = 12'o1127; +ram[12'o6025] = 12'o7530; +ram[12'o6026] = 12'o4526; +ram[12'o6027] = 12'o5211; +ram[12'o6030] = 12'o0; +ram[12'o6031] = 12'o4521; +ram[12'o6032] = 12'o3127; +ram[12'o6033] = 12'o4511; +ram[12'o6034] = 12'o6114; +ram[12'o6035] = 12'o4506; +ram[12'o6036] = 12'o4521; +ram[12'o6037] = 12'o7240; +ram[12'o6040] = 12'o1127; +ram[12'o6041] = 12'o5630; +ram[12'o6042] = 12'o0; +ram[12'o6043] = 12'o3164; +ram[12'o6044] = 12'o1314; +ram[12'o6045] = 12'o3260; +ram[12'o6046] = 12'o3210; +ram[12'o6047] = 12'o4255; +ram[12'o6050] = 12'o4255; +ram[12'o6051] = 12'o2210; +ram[12'o6052] = 12'o4255; +ram[12'o6053] = 12'o4255; +ram[12'o6054] = 12'o5642; +ram[12'o6055] = 12'o0; +ram[12'o6056] = 12'o3163; +ram[12'o6057] = 12'o1164; +ram[12'o6060] = 12'o1204; +ram[12'o6061] = 12'o7510; +ram[12'o6062] = 12'o5267; +ram[12'o6063] = 12'o3164; +ram[12'o6064] = 12'o2163; +ram[12'o6065] = 12'o2210; +ram[12'o6066] = 12'o5257; +ram[12'o6067] = 12'o7300; +ram[12'o6070] = 12'o2260; +ram[12'o6071] = 12'o1210; +ram[12'o6072] = 12'o7650; +ram[12'o6073] = 12'o5655; +ram[12'o6074] = 12'o1163; +ram[12'o6075] = 12'o1036; +ram[12'o6076] = 12'o4512; +ram[12'o6077] = 12'o5655; +ram[12'o6100] = 12'o0; +ram[12'o6101] = 12'o3164; +ram[12'o6102] = 12'o1164; +ram[12'o6103] = 12'o7710; +ram[12'o6104] = 12'o1035; +ram[12'o6105] = 12'o1315; +ram[12'o6106] = 12'o4512; +ram[12'o6107] = 12'o1164; +ram[12'o6110] = 12'o7510; +ram[12'o6111] = 12'o7041; +ram[12'o6112] = 12'o4242; +ram[12'o6113] = 12'o5700; +ram[12'o6114] = 12'o1204; +ram[12'o6115] = 12'o253; +ram[12'o6116] = 12'o255; +ram[12'o6117] = 12'o7200; +ram[12'o6120] = 12'o1051; +ram[12'o6121] = 12'o7410; +ram[12'o6122] = 12'o1133; +ram[12'o6123] = 12'o7041; +ram[12'o6124] = 12'o7450; +ram[12'o6125] = 12'o1347; +ram[12'o6126] = 12'o3164; +ram[12'o6127] = 12'o1022; +ram[12'o6130] = 12'o4512; +ram[12'o6131] = 12'o1412; +ram[12'o6132] = 12'o2157; +ram[12'o6133] = 12'o5336; +ram[12'o6134] = 12'o7240; +ram[12'o6135] = 12'o3157; +ram[12'o6136] = 12'o4750; +ram[12'o6137] = 12'o7410; +ram[12'o6140] = 12'o5331; +ram[12'o6141] = 12'o1346; +ram[12'o6142] = 12'o4512; +ram[12'o6143] = 12'o1156; +ram[12'o6144] = 12'o4300; +ram[12'o6145] = 12'o5770; +ram[12'o6146] = 12'o305; +ram[12'o6147] = 12'o7772; +ram[12'o6150] = 12'o6437; +ram[12'o6151] = 12'o0; +ram[12'o6152] = 12'o1143; +ram[12'o6153] = 12'o4520; +ram[12'o6154] = 12'o71; +ram[12'o6155] = 12'o4242; +ram[12'o6156] = 12'o1022; +ram[12'o6157] = 12'o4512; +ram[12'o6160] = 12'o1143; +ram[12'o6161] = 12'o26; +ram[12'o6162] = 12'o4242; +ram[12'o6163] = 12'o1033; +ram[12'o6164] = 12'o3142; +ram[12'o6165] = 12'o4512; +ram[12'o6166] = 12'o5751; +ram[12'o6167] = 12'o15; +ram[12'o6170] = 12'o0; +ram[12'o6171] = 12'o1045; +ram[12'o6172] = 12'o7700; +ram[12'o6173] = 12'o5376; +ram[12'o6174] = 12'o4450; +ram[12'o6175] = 12'o1367; +ram[12'o6176] = 12'o1033; +ram[12'o6177] = 12'o4512; +ram[12'o6200] = 12'o7240; +ram[12'o6201] = 12'o1044; +ram[12'o6202] = 12'o3044; +ram[12'o6203] = 12'o3156; +ram[12'o6204] = 12'o1044; +ram[12'o6205] = 12'o7500; +ram[12'o6206] = 12'o5220; +ram[12'o6207] = 12'o1631; +ram[12'o6210] = 12'o7700; +ram[12'o6211] = 12'o5244; +ram[12'o6212] = 12'o4407; +ram[12'o6213] = 12'o3631; +ram[12'o6214] = 12'o0; +ram[12'o6215] = 12'o7240; +ram[12'o6216] = 12'o1156; +ram[12'o6217] = 12'o5203; +ram[12'o6220] = 12'o4407; +ram[12'o6221] = 12'o3632; +ram[12'o6222] = 12'o0; +ram[12'o6223] = 12'o7001; +ram[12'o6224] = 12'o5216; +ram[12'o6225] = 12'o7771; +ram[12'o6226] = 12'o7772; +ram[12'o6227] = 12'o7; +ram[12'o6230] = 12'o7766; +ram[12'o6231] = 12'o5770; +ram[12'o6232] = 12'o5773; +ram[12'o6233] = 12'o5734; +ram[12'o6234] = 12'o5742; +ram[12'o6235] = 12'o7544; +ram[12'o6236] = 12'o6122; +ram[12'o6237] = 12'o6117; +ram[12'o6240] = 12'o7040; +ram[12'o6241] = 12'o1040; +ram[12'o6242] = 12'o3040; +ram[12'o6243] = 12'o5351; +ram[12'o6244] = 12'o4633; +ram[12'o6245] = 12'o1235; +ram[12'o6246] = 12'o3012; +ram[12'o6247] = 12'o4634; +ram[12'o6250] = 12'o1162; +ram[12'o6251] = 12'o5266; +ram[12'o6252] = 12'o7110; +ram[12'o6253] = 12'o3004; +ram[12'o6254] = 12'o1045; +ram[12'o6255] = 12'o7010; +ram[12'o6256] = 12'o3045; +ram[12'o6257] = 12'o1046; +ram[12'o6260] = 12'o7010; +ram[12'o6261] = 12'o3046; +ram[12'o6262] = 12'o1047; +ram[12'o6263] = 12'o7010; +ram[12'o6264] = 12'o3047; +ram[12'o6265] = 12'o1004; +ram[12'o6266] = 12'o2044; +ram[12'o6267] = 12'o5252; +ram[12'o6270] = 12'o7440; +ram[12'o6271] = 12'o5301; +ram[12'o6272] = 12'o7240; +ram[12'o6273] = 12'o1156; +ram[12'o6274] = 12'o3156; +ram[12'o6275] = 12'o1045; +ram[12'o6276] = 12'o7650; +ram[12'o6277] = 12'o3156; +ram[12'o6300] = 12'o7410; +ram[12'o6301] = 12'o3412; +ram[12'o6302] = 12'o1225; +ram[12'o6303] = 12'o3044; +ram[12'o6304] = 12'o4634; +ram[12'o6305] = 12'o1162; +ram[12'o6306] = 12'o3412; +ram[12'o6307] = 12'o2044; +ram[12'o6310] = 12'o5304; +ram[12'o6311] = 12'o1235; +ram[12'o6312] = 12'o3012; +ram[12'o6313] = 12'o1225; +ram[12'o6314] = 12'o3157; +ram[12'o6315] = 12'o1051; +ram[12'o6316] = 12'o7450; +ram[12'o6317] = 12'o5340; +ram[12'o6320] = 12'o7041; +ram[12'o6321] = 12'o1133; +ram[12'o6322] = 12'o7550; +ram[12'o6323] = 12'o5327; +ram[12'o6324] = 12'o7200; +ram[12'o6325] = 12'o1051; +ram[12'o6326] = 12'o3133; +ram[12'o6327] = 12'o1156; +ram[12'o6330] = 12'o7500; +ram[12'o6331] = 12'o7200; +ram[12'o6332] = 12'o1051; +ram[12'o6333] = 12'o7510; +ram[12'o6334] = 12'o5362; +ram[12'o6335] = 12'o1226; +ram[12'o6336] = 12'o7500; +ram[12'o6337] = 12'o7200; +ram[12'o6340] = 12'o1227; +ram[12'o6341] = 12'o3004; +ram[12'o6342] = 12'o1235; +ram[12'o6343] = 12'o1004; +ram[12'o6344] = 12'o3040; +ram[12'o6345] = 12'o1004; +ram[12'o6346] = 12'o7041; +ram[12'o6347] = 12'o3004; +ram[12'o6350] = 12'o1631; +ram[12'o6351] = 12'o2440; +ram[12'o6352] = 12'o1440; +ram[12'o6353] = 12'o1230; +ram[12'o6354] = 12'o7710; +ram[12'o6355] = 12'o5364; +ram[12'o6356] = 12'o3440; +ram[12'o6357] = 12'o2004; +ram[12'o6360] = 12'o5240; +ram[12'o6361] = 12'o2440; +ram[12'o6362] = 12'o2156; +ram[12'o6363] = 12'o7200; +ram[12'o6364] = 12'o1051; +ram[12'o6365] = 12'o7450; +ram[12'o6366] = 12'o5636; +ram[12'o6367] = 12'o7041; +ram[12'o6370] = 12'o3164; +ram[12'o6371] = 12'o1164; +ram[12'o6372] = 12'o1156; +ram[12'o6373] = 12'o7540; +ram[12'o6374] = 12'o5637; +ram[12'o6375] = 12'o1133; +ram[12'o6376] = 12'o7500; +ram[12'o6377] = 12'o7200; +ram[12'o6400] = 12'o7041; +ram[12'o6401] = 12'o1156; +ram[12'o6402] = 12'o7141; +ram[12'o6403] = 12'o3004; +ram[12'o6404] = 12'o7430; +ram[12'o6405] = 12'o5222; +ram[12'o6406] = 12'o1156; +ram[12'o6407] = 12'o1004; +ram[12'o6410] = 12'o7650; +ram[12'o6411] = 12'o5225; +ram[12'o6412] = 12'o1004; +ram[12'o6413] = 12'o7001; +ram[12'o6414] = 12'o7710; +ram[12'o6415] = 12'o1025; +ram[12'o6416] = 12'o4237; +ram[12'o6417] = 12'o5645; +ram[12'o6420] = 12'o2004; +ram[12'o6421] = 12'o5206; +ram[12'o6422] = 12'o1022; +ram[12'o6423] = 12'o4512; +ram[12'o6424] = 12'o5206; +ram[12'o6425] = 12'o7040; +ram[12'o6426] = 12'o1156; +ram[12'o6427] = 12'o3156; +ram[12'o6430] = 12'o2157; +ram[12'o6431] = 12'o5235; +ram[12'o6432] = 12'o7040; +ram[12'o6433] = 12'o3157; +ram[12'o6434] = 12'o5216; +ram[12'o6435] = 12'o1412; +ram[12'o6436] = 12'o5216; +ram[12'o6437] = 12'o0; +ram[12'o6440] = 12'o1036; +ram[12'o6441] = 12'o4512; +ram[12'o6442] = 12'o2164; +ram[12'o6443] = 12'o2237; +ram[12'o6444] = 12'o5637; +ram[12'o6445] = 12'o6145; +ram[12'o6446] = 12'o4521; +ram[12'o6447] = 12'o4510; +ram[12'o6450] = 12'o2377; +ram[12'o6451] = 12'o7574; +ram[12'o6452] = 12'o4526; +ram[12'o6453] = 12'o7240; +ram[12'o6454] = 12'o3037; +ram[12'o6455] = 12'o6014; +ram[12'o6456] = 12'o1317; +ram[12'o6457] = 12'o1161; +ram[12'o6460] = 12'o3113; +ram[12'o6461] = 12'o4565; +ram[12'o6462] = 12'o5261; +ram[12'o6463] = 12'o5665; +ram[12'o6464] = 12'o5246; +ram[12'o6465] = 12'o616; +ram[12'o6466] = 12'o0; +ram[12'o6467] = 12'o1067; +ram[12'o6470] = 12'o3156; +ram[12'o6471] = 12'o3157; +ram[12'o6472] = 12'o6001; +ram[12'o6473] = 12'o1037; +ram[12'o6474] = 12'o7700; +ram[12'o6475] = 12'o5306; +ram[12'o6476] = 12'o2157; +ram[12'o6477] = 12'o5272; +ram[12'o6500] = 12'o2156; +ram[12'o6501] = 12'o5272; +ram[12'o6502] = 12'o1161; +ram[12'o6503] = 12'o3113; +ram[12'o6504] = 12'o1054; +ram[12'o6505] = 12'o5315; +ram[12'o6506] = 12'o7040; +ram[12'o6507] = 12'o3037; +ram[12'o6510] = 12'o6016; +ram[12'o6511] = 12'o26; +ram[12'o6512] = 12'o7450; +ram[12'o6513] = 12'o5267; +ram[12'o6514] = 12'o1015; +ram[12'o6515] = 12'o3142; +ram[12'o6516] = 12'o5666; +ram[12'o6517] = 12'o4003; +ram[12'o6600] = 12'o0; +ram[12'o6601] = 12'o7300; +ram[12'o6602] = 12'o1600; +ram[12'o6603] = 12'o7450; +ram[12'o6604] = 12'o5600; +ram[12'o6605] = 12'o15; +ram[12'o6606] = 12'o7640; +ram[12'o6607] = 12'o1200; +ram[12'o6610] = 12'o24; +ram[12'o6611] = 12'o3231; +ram[12'o6612] = 12'o1600; +ram[12'o6613] = 12'o26; +ram[12'o6614] = 12'o1231; +ram[12'o6615] = 12'o3231; +ram[12'o6616] = 12'o1600; +ram[12'o6617] = 12'o2200; +ram[12'o6620] = 12'o7106; +ram[12'o6621] = 12'o7006; +ram[12'o6622] = 12'o31; +ram[12'o6623] = 12'o1236; +ram[12'o6624] = 12'o3235; +ram[12'o6625] = 12'o1631; +ram[12'o6626] = 12'o7430; +ram[12'o6627] = 12'o3231; +ram[12'o6630] = 12'o4504; +ram[12'o6631] = 12'o0; +ram[12'o6632] = 12'o4505; +ram[12'o6633] = 12'o40; +ram[12'o6634] = 12'o3043; +ram[12'o6635] = 12'o5637; +ram[12'o6636] = 12'o5637; +ram[12'o6637] = 12'o7406; +ram[12'o6640] = 12'o6720; +ram[12'o6641] = 12'o6717; +ram[12'o6642] = 12'o7077; +ram[12'o6643] = 12'o7171; +ram[12'o6644] = 12'o6647; +ram[12'o6645] = 12'o6653; +ram[12'o6646] = 12'o6762; +ram[12'o6647] = 12'o4504; +ram[12'o6650] = 12'o40; +ram[12'o6651] = 12'o1254; +ram[12'o6652] = 12'o5256; +ram[12'o6653] = 12'o4504; +ram[12'o6654] = 12'o44; +ram[12'o6655] = 12'o1231; +ram[12'o6656] = 12'o3260; +ram[12'o6657] = 12'o4505; +ram[12'o6660] = 12'o0; +ram[12'o6661] = 12'o5201; +ram[12'o6662] = 12'o0; +ram[12'o6663] = 12'o1042; +ram[12'o6664] = 12'o7141; +ram[12'o6665] = 12'o3042; +ram[12'o6666] = 12'o7024; +ram[12'o6667] = 12'o1041; +ram[12'o6670] = 12'o7041; +ram[12'o6671] = 12'o3041; +ram[12'o6672] = 12'o1004; +ram[12'o6673] = 12'o7140; +ram[12'o6674] = 12'o3004; +ram[12'o6675] = 12'o5662; +ram[12'o6676] = 12'o0; +ram[12'o6677] = 12'o7300; +ram[12'o6700] = 12'o1047; +ram[12'o6701] = 12'o7041; +ram[12'o6702] = 12'o3047; +ram[12'o6703] = 12'o7024; +ram[12'o6704] = 12'o1046; +ram[12'o6705] = 12'o7041; +ram[12'o6706] = 12'o3046; +ram[12'o6707] = 12'o7024; +ram[12'o6710] = 12'o1045; +ram[12'o6711] = 12'o7041; +ram[12'o6712] = 12'o3045; +ram[12'o6713] = 12'o1004; +ram[12'o6714] = 12'o7140; +ram[12'o6715] = 12'o3004; +ram[12'o6716] = 12'o5676; +ram[12'o6717] = 12'o4262; +ram[12'o6720] = 12'o1045; +ram[12'o6721] = 12'o7650; +ram[12'o6722] = 12'o5247; +ram[12'o6723] = 12'o1041; +ram[12'o6724] = 12'o7650; +ram[12'o6725] = 12'o5201; +ram[12'o6726] = 12'o1040; +ram[12'o6727] = 12'o7041; +ram[12'o6730] = 12'o1044; +ram[12'o6731] = 12'o7450; +ram[12'o6732] = 12'o5357; +ram[12'o6733] = 12'o7500; +ram[12'o6734] = 12'o5346; +ram[12'o6735] = 12'o1365; +ram[12'o6736] = 12'o7510; +ram[12'o6737] = 12'o5247; +ram[12'o6740] = 12'o1364; +ram[12'o6741] = 12'o3235; +ram[12'o6742] = 12'o4767; +ram[12'o6743] = 12'o2235; +ram[12'o6744] = 12'o5342; +ram[12'o6745] = 12'o5357; +ram[12'o6746] = 12'o7041; +ram[12'o6747] = 12'o1365; +ram[12'o6750] = 12'o7510; +ram[12'o6751] = 12'o5201; +ram[12'o6752] = 12'o1364; +ram[12'o6753] = 12'o3235; +ram[12'o6754] = 12'o4766; +ram[12'o6755] = 12'o2235; +ram[12'o6756] = 12'o5354; +ram[12'o6757] = 12'o4767; +ram[12'o6760] = 12'o4766; +ram[12'o6761] = 12'o4770; +ram[12'o6762] = 12'o4771; +ram[12'o6763] = 12'o5201; +ram[12'o6764] = 12'o7751; +ram[12'o6765] = 12'o27; +ram[12'o6766] = 12'o7271; +ram[12'o6767] = 12'o7251; +ram[12'o6770] = 12'o5713; +ram[12'o6771] = 12'o7000; +ram[12'o6772] = 12'o3347; +ram[12'o6773] = 12'o3347; +ram[12'o6774] = 12'o3330; +ram[12'o6775] = 12'o3347; +ram[12'o6776] = 12'o3347; +ram[12'o6777] = 12'o3345; +ram[12'o7000] = 12'o0; +ram[12'o7001] = 12'o7340; +ram[12'o7002] = 12'o3004; +ram[12'o7003] = 12'o1045; +ram[12'o7004] = 12'o7450; +ram[12'o7005] = 12'o1046; +ram[12'o7006] = 12'o7450; +ram[12'o7007] = 12'o1047; +ram[12'o7010] = 12'o7650; +ram[12'o7011] = 12'o5232; +ram[12'o7012] = 12'o1045; +ram[12'o7013] = 12'o7710; +ram[12'o7014] = 12'o4450; +ram[12'o7015] = 12'o3255; +ram[12'o7016] = 12'o1045; +ram[12'o7017] = 12'o7104; +ram[12'o7020] = 12'o7710; +ram[12'o7021] = 12'o5225; +ram[12'o7022] = 12'o4237; +ram[12'o7023] = 12'o2255; +ram[12'o7024] = 12'o5216; +ram[12'o7025] = 12'o2004; +ram[12'o7026] = 12'o4450; +ram[12'o7027] = 12'o1255; +ram[12'o7030] = 12'o7041; +ram[12'o7031] = 12'o1044; +ram[12'o7032] = 12'o3044; +ram[12'o7033] = 12'o3047; +ram[12'o7034] = 12'o5600; +ram[12'o7035] = 12'o6601; +ram[12'o7036] = 12'o6662; +ram[12'o7037] = 12'o0; +ram[12'o7040] = 12'o1047; +ram[12'o7041] = 12'o7104; +ram[12'o7042] = 12'o3047; +ram[12'o7043] = 12'o4245; +ram[12'o7044] = 12'o5637; +ram[12'o7045] = 12'o0; +ram[12'o7046] = 12'o1046; +ram[12'o7047] = 12'o7004; +ram[12'o7050] = 12'o3046; +ram[12'o7051] = 12'o1045; +ram[12'o7052] = 12'o7004; +ram[12'o7053] = 12'o3045; +ram[12'o7054] = 12'o5645; +ram[12'o7055] = 12'o0; +ram[12'o7056] = 12'o7340; +ram[12'o7057] = 12'o3004; +ram[12'o7060] = 12'o1045; +ram[12'o7061] = 12'o7450; +ram[12'o7062] = 12'o5635; +ram[12'o7063] = 12'o7710; +ram[12'o7064] = 12'o4450; +ram[12'o7065] = 12'o1045; +ram[12'o7066] = 12'o3162; +ram[12'o7067] = 12'o1046; +ram[12'o7070] = 12'o3163; +ram[12'o7071] = 12'o1041; +ram[12'o7072] = 12'o7710; +ram[12'o7073] = 12'o4636; +ram[12'o7074] = 12'o1004; +ram[12'o7075] = 12'o3157; +ram[12'o7076] = 12'o5655; +ram[12'o7077] = 12'o1263; +ram[12'o7100] = 12'o3272; +ram[12'o7101] = 12'o4255; +ram[12'o7102] = 12'o1042; +ram[12'o7103] = 12'o4333; +ram[12'o7104] = 12'o7301; +ram[12'o7105] = 12'o1044; +ram[12'o7106] = 12'o1040; +ram[12'o7107] = 12'o3044; +ram[12'o7110] = 12'o1272; +ram[12'o7111] = 12'o3047; +ram[12'o7112] = 12'o1237; +ram[12'o7113] = 12'o3046; +ram[12'o7114] = 12'o1041; +ram[12'o7115] = 12'o4333; +ram[12'o7116] = 12'o1047; +ram[12'o7117] = 12'o3047; +ram[12'o7120] = 12'o7004; +ram[12'o7121] = 12'o1272; +ram[12'o7122] = 12'o1046; +ram[12'o7123] = 12'o3046; +ram[12'o7124] = 12'o7004; +ram[12'o7125] = 12'o1237; +ram[12'o7126] = 12'o3045; +ram[12'o7127] = 12'o4200; +ram[12'o7130] = 12'o2157; +ram[12'o7131] = 12'o4450; +ram[12'o7132] = 12'o5635; +ram[12'o7133] = 12'o0; +ram[12'o7134] = 12'o3200; +ram[12'o7135] = 12'o3237; +ram[12'o7136] = 12'o3272; +ram[12'o7137] = 12'o1370; +ram[12'o7140] = 12'o3255; +ram[12'o7141] = 12'o7100; +ram[12'o7142] = 12'o1200; +ram[12'o7143] = 12'o7010; +ram[12'o7144] = 12'o3200; +ram[12'o7145] = 12'o7420; +ram[12'o7146] = 12'o5355; +ram[12'o7147] = 12'o7100; +ram[12'o7150] = 12'o1163; +ram[12'o7151] = 12'o1272; +ram[12'o7152] = 12'o3272; +ram[12'o7153] = 12'o7004; +ram[12'o7154] = 12'o1162; +ram[12'o7155] = 12'o1237; +ram[12'o7156] = 12'o7010; +ram[12'o7157] = 12'o3237; +ram[12'o7160] = 12'o1272; +ram[12'o7161] = 12'o7010; +ram[12'o7162] = 12'o3272; +ram[12'o7163] = 12'o2255; +ram[12'o7164] = 12'o5342; +ram[12'o7165] = 12'o1200; +ram[12'o7166] = 12'o7010; +ram[12'o7167] = 12'o5733; +ram[12'o7170] = 12'o7764; +ram[12'o7171] = 12'o1041; +ram[12'o7172] = 12'o7650; +ram[12'o7173] = 12'o4526; +ram[12'o7174] = 12'o1062; +ram[12'o7175] = 12'o3272; +ram[12'o7176] = 12'o4255; +ram[12'o7177] = 12'o1040; +ram[12'o7200] = 12'o7041; +ram[12'o7201] = 12'o1044; +ram[12'o7202] = 12'o7001; +ram[12'o7203] = 12'o3044; +ram[12'o7204] = 12'o3045; +ram[12'o7205] = 12'o3046; +ram[12'o7206] = 12'o1314; +ram[12'o7207] = 12'o3271; +ram[12'o7210] = 12'o5226; +ram[12'o7211] = 12'o7420; +ram[12'o7212] = 12'o5216; +ram[12'o7213] = 12'o3162; +ram[12'o7214] = 12'o1164; +ram[12'o7215] = 12'o3163; +ram[12'o7216] = 12'o7200; +ram[12'o7217] = 12'o4647; +ram[12'o7220] = 12'o1163; +ram[12'o7221] = 12'o7004; +ram[12'o7222] = 12'o3163; +ram[12'o7223] = 12'o1162; +ram[12'o7224] = 12'o7004; +ram[12'o7225] = 12'o3162; +ram[12'o7226] = 12'o7100; +ram[12'o7227] = 12'o1042; +ram[12'o7230] = 12'o1163; +ram[12'o7231] = 12'o3164; +ram[12'o7232] = 12'o7004; +ram[12'o7233] = 12'o1041; +ram[12'o7234] = 12'o1162; +ram[12'o7235] = 12'o2271; +ram[12'o7236] = 12'o5211; +ram[12'o7237] = 12'o7210; +ram[12'o7240] = 12'o3047; +ram[12'o7241] = 12'o4650; +ram[12'o7242] = 12'o2157; +ram[12'o7243] = 12'o5646; +ram[12'o7244] = 12'o4450; +ram[12'o7245] = 12'o5646; +ram[12'o7246] = 12'o6601; +ram[12'o7247] = 12'o7045; +ram[12'o7250] = 12'o7000; +ram[12'o7251] = 12'o0; +ram[12'o7252] = 12'o7300; +ram[12'o7253] = 12'o1045; +ram[12'o7254] = 12'o7510; +ram[12'o7255] = 12'o7020; +ram[12'o7256] = 12'o7010; +ram[12'o7257] = 12'o3045; +ram[12'o7260] = 12'o1046; +ram[12'o7261] = 12'o7010; +ram[12'o7262] = 12'o3046; +ram[12'o7263] = 12'o1047; +ram[12'o7264] = 12'o7010; +ram[12'o7265] = 12'o3047; +ram[12'o7266] = 12'o2044; +ram[12'o7267] = 12'o5651; +ram[12'o7270] = 12'o5651; +ram[12'o7271] = 12'o0; +ram[12'o7272] = 12'o7300; +ram[12'o7273] = 12'o1041; +ram[12'o7274] = 12'o7510; +ram[12'o7275] = 12'o7020; +ram[12'o7276] = 12'o7010; +ram[12'o7277] = 12'o3041; +ram[12'o7300] = 12'o1042; +ram[12'o7301] = 12'o7010; +ram[12'o7302] = 12'o3042; +ram[12'o7303] = 12'o1043; +ram[12'o7304] = 12'o7010; +ram[12'o7305] = 12'o3043; +ram[12'o7306] = 12'o2040; +ram[12'o7307] = 12'o5671; +ram[12'o7310] = 12'o5671; +ram[12'o7311] = 12'o0; +ram[12'o7312] = 12'o7300; +ram[12'o7313] = 12'o1044; +ram[12'o7314] = 12'o7750; +ram[12'o7315] = 12'o3044; +ram[12'o7316] = 12'o1044; +ram[12'o7317] = 12'o1331; +ram[12'o7320] = 12'o3271; +ram[12'o7321] = 12'o7430; +ram[12'o7322] = 12'o5711; +ram[12'o7323] = 12'o4251; +ram[12'o7324] = 12'o2271; +ram[12'o7325] = 12'o5323; +ram[12'o7326] = 12'o3047; +ram[12'o7327] = 12'o1046; +ram[12'o7330] = 12'o5711; +ram[12'o7331] = 12'o7751; +ram[12'o7332] = 12'o0; +ram[12'o7333] = 12'o3045; +ram[12'o7334] = 12'o3046; +ram[12'o7335] = 12'o3047; +ram[12'o7336] = 12'o1005; +ram[12'o7337] = 12'o3044; +ram[12'o7340] = 12'o4251; +ram[12'o7341] = 12'o4650; +ram[12'o7342] = 12'o5732; +ram[12'o7343] = 12'o7037; +ram[12'o7344] = 12'o5713; +ram[12'o7345] = 12'o7774; +ram[12'o7346] = 12'o4421; +ram[12'o7347] = 12'o3040; +ram[12'o7350] = 12'o1; +ram[12'o7351] = 12'o4407; +ram[12'o7352] = 12'o5346; +ram[12'o7353] = 12'o0; +ram[12'o7354] = 12'o4504; +ram[12'o7355] = 12'o7346; +ram[12'o7356] = 12'o4505; +ram[12'o7357] = 12'o41; +ram[12'o7360] = 12'o1345; +ram[12'o7361] = 12'o3156; +ram[12'o7362] = 12'o4743; +ram[12'o7363] = 12'o2156; +ram[12'o7364] = 12'o5362; +ram[12'o7365] = 12'o4744; +ram[12'o7366] = 12'o4743; +ram[12'o7367] = 12'o4744; +ram[12'o7370] = 12'o4504; +ram[12'o7371] = 12'o45; +ram[12'o7372] = 12'o4505; +ram[12'o7373] = 12'o7346; +ram[12'o7374] = 12'o3047; +ram[12'o7375] = 12'o3044; +ram[12'o7376] = 12'o1045; +ram[12'o7377] = 12'o7700; +ram[12'o7400] = 12'o5500; +ram[12'o7401] = 12'o2046; +ram[12'o7402] = 12'o7410; +ram[12'o7403] = 12'o2045; +ram[12'o7404] = 12'o4450; +ram[12'o7405] = 12'o5500; +ram[12'o7406] = 12'o1407; +ram[12'o7407] = 12'o4503; +ram[12'o7410] = 12'o4504; +ram[12'o7411] = 12'o44; +ram[12'o7412] = 12'o4505; +ram[12'o7413] = 12'o7545; +ram[12'o7414] = 12'o4504; +ram[12'o7415] = 12'o40; +ram[12'o7416] = 12'o4505; +ram[12'o7417] = 12'o44; +ram[12'o7420] = 12'o4452; +ram[12'o7421] = 12'o7710; +ram[12'o7422] = 12'o7001; +ram[12'o7423] = 12'o1045; +ram[12'o7424] = 12'o7640; +ram[12'o7425] = 12'o4526; +ram[12'o7426] = 12'o1046; +ram[12'o7427] = 12'o3350; +ram[12'o7430] = 12'o4407; +ram[12'o7431] = 12'o5661; +ram[12'o7432] = 12'o0; +ram[12'o7433] = 12'o1350; +ram[12'o7434] = 12'o7450; +ram[12'o7435] = 12'o5255; +ram[12'o7436] = 12'o7500; +ram[12'o7437] = 12'o5246; +ram[12'o7440] = 12'o4407; +ram[12'o7441] = 12'o4345; +ram[12'o7442] = 12'o6345; +ram[12'o7443] = 12'o5661; +ram[12'o7444] = 12'o0; +ram[12'o7445] = 12'o5250; +ram[12'o7446] = 12'o7041; +ram[12'o7447] = 12'o3350; +ram[12'o7450] = 12'o4407; +ram[12'o7451] = 12'o3345; +ram[12'o7452] = 12'o0; +ram[12'o7453] = 12'o2350; +ram[12'o7454] = 12'o5250; +ram[12'o7455] = 12'o1413; +ram[12'o7456] = 12'o3407; +ram[12'o7457] = 12'o5660; +ram[12'o7460] = 12'o6601; +ram[12'o7461] = 12'o1573; +ram[12'o7462] = 12'o1045; +ram[12'o7463] = 12'o7510; +ram[12'o7464] = 12'o4526; +ram[12'o7465] = 12'o7650; +ram[12'o7466] = 12'o5500; +ram[12'o7467] = 12'o1044; +ram[12'o7470] = 12'o7510; +ram[12'o7471] = 12'o7020; +ram[12'o7472] = 12'o7010; +ram[12'o7473] = 12'o3044; +ram[12'o7474] = 12'o1334; +ram[12'o7475] = 12'o3045; +ram[12'o7476] = 12'o4407; +ram[12'o7477] = 12'o6345; +ram[12'o7500] = 12'o5560; +ram[12'o7501] = 12'o4345; +ram[12'o7502] = 12'o1345; +ram[12'o7503] = 12'o0; +ram[12'o7504] = 12'o7040; +ram[12'o7505] = 12'o1044; +ram[12'o7506] = 12'o3044; +ram[12'o7507] = 12'o1044; +ram[12'o7510] = 12'o7041; +ram[12'o7511] = 12'o1345; +ram[12'o7512] = 12'o7640; +ram[12'o7513] = 12'o5276; +ram[12'o7514] = 12'o1045; +ram[12'o7515] = 12'o7041; +ram[12'o7516] = 12'o1346; +ram[12'o7517] = 12'o7640; +ram[12'o7520] = 12'o5276; +ram[12'o7521] = 12'o1046; +ram[12'o7522] = 12'o7041; +ram[12'o7523] = 12'o1347; +ram[12'o7524] = 12'o7450; +ram[12'o7525] = 12'o5500; +ram[12'o7526] = 12'o7500; +ram[12'o7527] = 12'o7041; +ram[12'o7530] = 12'o7001; +ram[12'o7531] = 12'o7650; +ram[12'o7532] = 12'o5500; +ram[12'o7533] = 12'o5276; +ram[12'o7534] = 12'o3015; +ram[12'o7535] = 12'o1045; +ram[12'o7536] = 12'o7450; +ram[12'o7537] = 12'o5343; +ram[12'o7540] = 12'o7710; +ram[12'o7541] = 12'o1034; +ram[12'o7542] = 12'o7001; +ram[12'o7543] = 12'o4430; +ram[12'o7544] = 12'o5500; +ram[12'o7545] = 12'o0; +ram[12'o7546] = 12'o0; +ram[12'o7547] = 12'o0; +ram[12'o7550] = 12'o0; diff --git a/cpu/maketraces.sh b/cpu/maketraces.sh new file mode 100755 index 0000000..1a24852 --- /dev/null +++ b/cpu/maketraces.sh @@ -0,0 +1 @@ +#!/bin/sh diff --git a/cpu/pdp8.v b/cpu/pdp8.v new file mode 100644 index 0000000..9072579 --- /dev/null +++ b/cpu/pdp8.v @@ -0,0 +1,728 @@ +// PDP-8 +// Based on descriptions in "Computer Engineering" +// Nov 2005 Brad Parker brad@heeltoe.com +// initial work; runs focal a bit +// Dec 2006 +// cleaned up a little; now runs focal to prompt +// moved i/o out to pdp8_io.v +// added IF, DF, user mode +// + +// TODO: +// fully implement extended memory (IF & DF), user mode (KT8/I) +// add df32/rf08 +// 6000 pws ac <= switches +// + +// +// Instruction format: +// +// 0 1 2 3 4 5 6 7 8 9 10 11 +// 11 10 9 8 7 6 5 4 3 2 1 0 +// |--op--| +// 0 and +// 1 tad +// 2 isz +// 3 dca +// 4 jms +// 5 jmp +// 6 iot +// 7 opr +// 11 10 9 8 7 6 5 4 3 2 1 0 +// group 1 +// 0 +// |cla|clf| | | +// | | |cma cml| | +// |bsw 001 | +// |ral 010 | +// |rtl 011 | +// |rar 100 | +// |rtr 101 | +// | |iac +// +// 11 10 9 8 7 6 5 4 3 2 1 0 +// group 2 +// 1 0 +// |sma|sza|snl|skp| | +// |cla| +// |osr|hlt +// +// group 3 +// 11 10 9 8 7 6 5 4 3 2 1 0 +// eae +// 1 1 +// |cla| +// |mqa|sca|mql| +// |isn | +// +// + +/* + cpu states + + F0 fetch + F1 incr pc + F2 write + F3 dispatch + + E0 read + E1 decode + E2 write + E3 load + +or + + D0 read + D1 wait + D2 write + D3 load + + ------ + + F0 fetch + check for interrupt + F1 incr pc + if opr + group 1 processing + group 2 processing + + if iot + + incr pc or skip (incr pc by 2) + + F2 write + ma <= pc + + F3 dispatch + if opr + group1 processing + + if !opr && !iot + possible defer + + + D0 + mb <= memory + D1 +*/ + +// extended memory +// +// 62n1 cdf change data field; df <= mb[5:3] +// 62n2 cif change instruction field; if <= mb[5:3], after next jmp or jms +// 6214 rdf read df into ac[5:3] +// 6224 rif read if into ac[5:3] +// 6234 rib read sf into ac[5:0], which is {if,df} +// 6244 rmf restore memory field, sf => ib, df +// (remember that on interrupt, sf <= {if,df}) +// + +`include "pdp8_io.v" + +module pdp8(clk, reset_n, switches); + +input clk, reset_n; +input[11:0] switches; + +// memory buffer, holds data, instructions +reg[11:0] mb; + +// hold address of work in memory being accessed +reg[14:0] ma; + +// accumulator & link +reg[11:0] ac; +reg l; + +// MQ +reg [11:0] mq; + +// program counter +reg[11:0] pc; +wire pc_incr, pc_skip; + +// instruction register +reg[2:0] ir; + +// extended memory - instruction field & data field +reg [2:0] IF; +reg [2:0] DF; +reg [2:0] IB; +reg [5:0] SF; +reg ib_pending; + +// user mode +reg UB; +reg UF; + +// +wire[11:0] memory_bus; +reg ram_we_n; + +// processor state +reg[3:0] state, next_state; + +reg run; +reg interrupt_enable; +reg interrupt_cycle; +reg interrupt_inhibit; +reg interrupt_skip; + +reg interrupt; +reg user_interrupt; + +reg io_pulse_1, io_pulse_2, io_pulse_4; + +wire [11:0] io_data; +wire io_data_avail; +wire io_interrupt; +wire io_skip; + +wire[5:0] io_select; +assign io_select = mb[8:3]; + +wire skip_condition; + +wire fetch; // memory cycle to fetch instruction +wire deferred; // memory cycle to get address of operand +wire execute; // memory cycle to getch (store) operand and execute isn + +assign {fetch, deferred, execute} = + (state[3:2] == 2'b00) ? 3'b100 : + (state[3:2] == 2'b01) ? 3'b010 : + (state[3:2] == 2'b10) ? 3'b001 : + 3'b000 ; + +wire and,tad,isz,dca,jms,jmp,iot,opr; + +assign {and,tad,isz,dca,jms,jmp,iot,opr} = + (ir == 3'b000) ? 8'b10000000 : + (ir == 3'b001) ? 8'b01000000 : + (ir == 3'b010) ? 8'b00100000 : + (ir == 3'b011) ? 8'b00010000 : + (ir == 3'b100) ? 8'b00001000 : + (ir == 3'b101) ? 8'b00000100 : + (ir == 3'b110) ? 8'b00000010 : + 8'b00000001 ; + + +//------------- + +parameter F0 = 4'b0000; +parameter F1 = 4'b0001; +parameter F2 = 4'b0010; +parameter F3 = 4'b0011; + +parameter D0 = 4'b0100; +parameter D1 = 4'b0101; +parameter D2 = 4'b0110; +parameter D3 = 4'b0111; + +parameter E0 = 4'b1000; +parameter E1 = 4'b1001; +parameter E2 = 4'b1010; +parameter E3 = 4'b1011; + +ram_4kx12 ram( + .A(ma), + .DI(mb), + .DO(memory_bus), + .CE_N(1'b0), + .WE_N(ram_we_n)); + +/* + * note: bit numbering is opposite that used in "Computer Engineering" + * + * F1 + * if opr + * if MB[8] and !MB[0] + * begin + * if skip.conditions ^ MB[3] + * pc <= pc + 2 + * if skip.conditions == MB[3] + * pc <= pc + 1 next + * if MB[7] + * ac <= 0 + */ +assign skip_condition = + (mb[6] && ac[11]) || + (mb[5] && ac == 0) || + (mb[4] && l == 1); + +assign pc_incr = + (opr & !mb[8]) || + (opr && (mb[8] && !mb[0]) && (skip_condition == mb[3])) || + iot || + (!(opr || iot) && !interrupt_cycle); + +assign pc_skip = + (opr && (mb[8] && !mb[0]) && (skip_condition ^ mb[3])) || + (iot && (io_skip || interrupt_skip)); +// (iot && mb[0] && io_skip); + + +pdp8_io io(.clk(clk), .reset_n(reset_n), + .iot(iot), .state(state), .pc(pc), .ac(ac), .mb(mb), + .io_select(io_select), + .io_data_out(io_data), + .io_data_avail(io_data_avail), + .io_interrupt(io_interrupt), + .io_skip(io_skip)); + +always @(reset_n) + if (reset_n == 0) + begin + pc <= 0; + ma <= 0; + mb <= 0; + ac <= 0; + mq <= 0; + l <= 0; + ir <= 0; + ram_we_n <= 1; + state <= 0; + next_state <= 0; + run <= 1; + interrupt_enable <= 0; + interrupt_cycle <= 0; + interrupt_inhibit <= 0; + interrupt_skip <= 0; + interrupt <= 0; + user_interrupt <= 0; + io_pulse_1 <= 0; + io_pulse_2 <= 0; + io_pulse_4 <= 0; + IF <= 0; + DF <= 0; + IB <= 0; + SF <= 0; + UF <= 0; + UB <= 0; + ib_pending <= 0; + end + +initial + begin + ram_we_n = 1; + end + +/* + * cpu state state machine + * + * clock next cpu state at rising edge of clock + */ + +always @(posedge clk) + state <= #1 next_state; + +always @(state) + begin + case (state) + + // FETCH + F0: + begin + interrupt_skip <= 0; + + if (interrupt && interrupt_enable && + !interrupt_inhibit && !interrupt_cycle) + begin + $display("interrupt; %b %b %b", + interrupt, interrupt_enable, interrupt_cycle); + interrupt_cycle <= 1; + interrupt <= 0; + mb <= 12'o4000; + ir <= 3'o4; + SF <= {IF,DF}; + IF <= #1 3'b000; + DF <= #1 3'b000; + end + else + begin + interrupt_cycle <= 0; + mb <= memory_bus; + ir <= memory_bus[11:9]; + end + + next_state <= F1; + end + + F1: + begin +//$display("f1: io_skip %b", io_skip); +//$display("f1 - ma %o, mb %o, ir %o", ma, mb, ir); + if (opr) + begin + // group 1 + if (!mb[8]) + begin +// $display("f1/g1 - ma %o, mb %o, ac %o l %o", ma, mb, ac,l); + + if (mb[7]) ac <= 0; + if (mb[6]) l <= 0; + if (mb[5]) ac <= ~ac; + if (mb[4]) l <= ~l; + end + + // group 2 + if (mb[8] & !mb[0]) + begin +// $display("f1/g2 - ma %o, mb %o, sc %o, i %o s %o, ac %o l %o", +// ma, mb, skip_condition, pc_incr, pc_skip, ac, l); + + if (mb[7]) + ac <= 0; + end + + // group 3 + if (mb[8] & mb[0]) + begin + if (mb[7]) ac <= 0; + end + end + + if (iot) + begin + + $display("iot %t, run %b, state %b, pc %o, ir %o, mb %o, io_select %o", + $time, run, state, pc, ir, mb, io_select); + + if (mb[0]) io_pulse_1 <= 1; + if (mb[1]) io_pulse_2 <= 1; + if (mb[2]) io_pulse_4 <= 1; + + case (io_select) + 6'b000000: // ION, IOF + case (mb[2:0]) + 3'b001: interrupt_enable <= 1; + 3'b010: interrupt_enable <= 0; + 3'b011: if (interrupt_enable) interrupt_skip <= 1; + endcase // case(mb[2:0]) + + 6'b010xxx: // CDF..RMF + begin + case (mb[2:0]) + 3'b001: DF <= mb[5:3]; // CDF + 3'b010: // CIF + begin + IB <= mb[5:3]; + ib_pending <= 1; + interrupt_inhibit <= 1; + end + 3'b100: + case (io_select[2:0]) + 3'b001: ac <= { 6'b0, DF, 3'b0 }; // RDF + 3'b010: ac <= { 6'b0, IF, 3'b0 }; // RIF + 3'b011: ac <= { 6'b0, SF }; // RIB + 3'b100: begin // RMF + IB <= SF[5:3]; + DF <= SF[2:0]; + end + endcase // case(io_select[2:0]) + endcase // case(mb[2:0]) + end + endcase + + if (io_data_avail) + begin + ac <= io_data; + end + end + + if (io_interrupt) + interrupt <= 1; + + //$display("f1 io_skip %b skip %b, incr %b", io_skip, pc_skip, pc_incr); + if (pc_skip) + pc <= pc + 2; + else + if (pc_incr) + pc <= pc + 1; + + next_state <= F2; + end + + F2: + begin + io_pulse_1 <= 0; + io_pulse_2 <= 0; + io_pulse_4 <= 0; + + if (opr) + begin + ma <= {IF,pc}; + + // group 3 + if (mb[8] & mb[0]) + begin + $display("f2/g3 - ma %o, mb %o, ac %o l %o", ma, mb, ac,l); + + case ({mb[6:4]}) + 3'b001: mq <= ac; + 3'b100: ac <= ac | mq; +// 3'b101: tmq <= mq; + 3'b100: ac <= mq; + 3'b101: ac <= mq; + endcase // case({mb[6:4]}) + end // if (mb[8] & mb[0]) + end // if (opr) + + if (iot) + ma <= {IF,pc}; + + if (!(opr || iot)) + begin + ma[6:0] <= mb[6:0]; + if (!mb[7]) + ma[11:7] <= 0; + end + + next_state <= F3; + end + + F3: + begin + if (opr) + begin + // group 1 + if (!mb[8]) + begin + if (mb[0]) // IAC + {l,ac} <= {l,ac} + 1'b1; + if (mb[3:1] == 3'b001) // BSW + {l,ac} <= {l,ac[5:0],ac[11:6]}; + if (mb[3] && !mb[1]) // RAR + {l,ac} <= {ac[0],l,ac[11:1]}; + if (mb[3] && mb[1]) // RTR + {l,ac} <= {ac[1:0],l,ac[11:2]}; + if (mb[2] && !mb[1]) // RAL + {l,ac} <= {ac[11:0],l}; + if (mb[2] && mb[1]) // RTL + {l,ac} <= {ac[10:0],l,ac[11]}; + end + + if (!UF) + begin + // group 2 + if (mb[8] & !mb[0]) + if (mb[2]) + ac <= ac | switches; + if (mb[1]) + run <= 0; + end + + if (UF) + begin + // group 2 - user mode (halt & osr) + if (mb[8] & !mb[0]) + if (mb[2]) + user_interrupt <= 1; + if (mb[1]) + user_interrupt <= 1; + end + + // group 3 + if (mb[8] & mb[0]) + begin + if (mb[7:4] == 4'b1101) mq <= 0; + end + + ir <= 0; + mb <= 0; + next_state <= F0; + end + + if (iot) + begin + ir <= 0; + mb <= 0; + next_state <= F0; + end + + if (!(opr || iot)) + begin + if (!mb[8] & jmp) + begin + pc <= ma; + ir <= 0; + mb <= 0; + next_state <= F0; + end + + if (mb[8]) + begin + mb <= 0; + next_state <= D0; /* defer */ + end + + if (!mb[8] & !jmp) + begin + mb <= 0; + next_state <= E0; + end + end + end + + // DEFER + + D0: + begin + mb <= memory_bus; + next_state <= D1; + end + + D1: + begin + // auto increment regs + if (ma[11:3] == 8'h01) + mb <= mb + 1; + + next_state <= D2; + end + + D2: + begin + // write back + if (ma[11:3] == 8'h01) + ram_we_n <= 0; + + ma <= #1 {DF,mb}; + next_state <= D3; + end + + D3: + begin + ram_we_n <= 1; + + if (jmp) + begin + pc <= mb; + ir <= 0; + mb <= 0; + next_state <= F0; + end + + if (!jmp) + begin + mb <= 0; + next_state <= E0; + end + end + + // EXECUTE + + E0: + begin + mb <= memory_bus; + next_state <= E1; + end + + E1: + begin + if (and) + ; + + if (isz) + begin + mb <= mb + 1; + if (mb == 12'b111111111111) + pc <= pc + 1; + end + + if (dca) + mb <= ac; + + if (jms) + mb <= pc; + + next_state <= E2; + end + + E2: + begin + if (isz || dca || jms) + ram_we_n <= 0; + + if (~jms) + ma <= #1 {IF,pc}; + + if (jms) + ma <= #1 {ma[14:12], ma[11:0] + 1}; + + next_state <= E3; + end + + E3: + begin + ram_we_n <= 1; + + if (and) + ac <= ac & mb; + + if (tad) + {l,ac} <= ac + mb; + + //if (tad) $display("tad - mb %o, ac %o l %o", mb, ac, l); + + if (dca) + ac <= 0; + + if (jms) + pc <= ma; + + ir <= 0; + next_state <= F0; + end + endcase + end + +endmodule + +/* 4kx12 static ram */ +module ram_4kx12(A, DI, DO, CE_N, WE_N); + + input[14:0] A; + input[11:0] DI; + input CE_N, WE_N; + output[11:0] DO; + + reg[11:0] ram [0:32767]; + integer i; + + initial + begin + for (i = 0; i < 32768; i=i+1) + ram[i] = 12'b0; + + ram[15'o0000] = 12'o5177; + ram[15'o0200] = 12'o7300; + ram[15'o0201] = 12'o1300; + ram[15'o0202] = 12'o1301; + ram[15'o0203] = 12'o3302; + ram[15'o0204] = 12'o7402; + ram[15'o0205] = 12'o5200; + +`include "focal.v" + ram[15'o0000] = 12'o5404; + ram[15'o0004] = 12'o0200; + end + + always @(negedge WE_N) + begin + if (CE_N == 0) + begin + $display("ram: write [%o] <- %o", A, DI); + ram[ A ] = DI; + end + end + +//always @(A) +// begin +// $display("ram: ce %b, we %b [%o] -> %o", CE_N, WE_N, A, ram[A]); +// end + +// assign DO = ram[ A ]; +assign DO = (^A === 1'bX || A === 1'bz) ? ram[0] : ram[A]; + +endmodule + diff --git a/cpu/pdp8_io.v b/cpu/pdp8_io.v new file mode 100644 index 0000000..186a4e7 --- /dev/null +++ b/cpu/pdp8_io.v @@ -0,0 +1,419 @@ +// PDP-8 i/o +// Based on descriptions in "Computer Engineering" +// Dev 2006 Brad Parker brad@heeltoe.com +// + +/* + iot's touched by focal + + 6022 PCF + 6203 CDF CIF 00 + 6402 PT08 + 6412 + 6422 + 6432 + 6442 + 6452 + 6462 + 6472 + 6764 DECTAPE + 6772 +*/ + +/* + RF08 + 7750 word count + 7751 current address + + 2048 words/track + + 660x + 661x + 662x + 664x + + 6601 DCMA Generates System Clear Pulse (SCLP) at IOP time 1. + Clears disk memory eaddress(DMA), Parity Eror Flag (PEF), + Data Request Late Flag (DRL), and sets logic to + initial state for read or write. Does not clear + interrupt enable or extended address register. + + 6603 DMAR Generate SCLP at IOP time 1. At IOP time 2, loads DMA + with AC and clears AC. Read continues for number words + in WC register (7750) + + 6605 DMAW Generate SCLP at IOP time 1. At IOP time 4, loads DMA + with AC and clears AC. When the disk word address is located + writing begins, disk address is incremented for each + word written + + 6611 DCIM clears disk interrupt enable and the extended address + registers at IOP time 1. + + 6612 DSAC At IOP time 2, skip if Address Confirmed (ADC) set indicating + the DMA address and disk word address compare. AC is then + cleared. + + 6615 DIML At IOP time 1, clear interrupt enable and memory address + extension registers. At IOP time 4, load interrupt enable + and memory address extension register with AC, clear AC. + + 6616 DIMA Clear ??? at IOP time 2. At IOP time 4 load AC with status + register. + + 6621 DFSE skip on error skip if DRL, PER WLS or NXD set + + 6622 ??? skip if data completion DCF set + + 6623 DISK skip on error or data completion; enabled at IOP 2 + + 6626 DMAC clear ac at IOP time 2 load AC from DMA at IOP time 4. + + 6641 DCXA Clears EMA + + 6643 DXAL Clears and loads EMA from AC. At IOP time 1, clear EMA, at + IOP time 2, load EMA with AC. Clear AC + + 6645 DXAC Clears AC and loads EMA into AC + + 6646 DMMT Maintenance + + uses 3 cycle data break + + ac 7:0, ac 11:0 => 20 bit {EMA,DMA} + 20 bit {EMA,DMA} = { disk-select, track-select 6:0, word-select 11:0 } + + status +*/ + +// EIE = WLS | DRL | NXD | PER + +/* + 3 cycle data break + + 1. An address is read from the device to indicate the location of the +word count register. This location specifies the number of words in +the block yet to be transferred. The address is always the same for a +given device. + + 2. The content of the specficified word count register is read from +memory and incremented by one. To transfer a block of n words, the +word count is set to -n during the programmed initialization of the +device. When this register is incremented to 0, a pulse is sent to +the device to terminate the transfer. + + 3. The location after the word count register contains the current +address register for the device transfer. The content of thise +register is set to 1 less than the location to be affected by the next +transfer. To transfer a block beginning at location A, the register is +originally set to A-1. + + 4. The content of the current address register is incremented by 1 +and then used to specify the location affected by the transfer. + + After the transfer of information has been accomplished through the +data break factility, input data (or new output data) is processed, +usually through the program interrupt facility. An interrupt is +requested when the data transfer is completed and the service routine +will process the information. + + xxx: + if (databreak_req) + begin + databreak_done <= 0; + next_state <= DB0; + end + + // read word count + DB0: + ma <= wc-address; + next_state <= DB1; + + // write word count - 1 + DB1: + mb <= memory_bus - 1; + ram_we_n <= 0; + if (mb == 0) databreak_done <= 1; + next_state <= DB2; + + // finish write + DB2: + ram_we_n <= 1; + next_state <= DB3; + + // read current address + DB3: + ma <= ma | 1; + next_state <= DB4; + + // write current address - 1 + DB4: + mb <= memory_bus + 1; + ram_we_n <= 0; + next_state <= DB5; + + // finish write + DB5: + ram_we_n <= 1; + next_state <= DB6; + + // set up read/write address + DB6: + ma <= mb; + next_state <= DB7; + + // do read or start write + DB7: + if (databreak_write) + begin + data <= memory_bus; + next_state <= F0; + end + else + begin + mb <= data; + ram_we_n <= 0; + next_state <= DB8; + end + + // finish write + DB8: + ram_we_n < = 1; + next_state <= F0; + + */ + + +module pdp8_io(clk, reset_n, iot, state, pc, ac, mb, + io_select, + io_data_out, io_data_avail, io_interrupt, io_skip, io_clear_ac); + + input clk, reset_n, iot; + input [11:0] pc; + input [11:0] ac; + input [11:0] mb; + input [3:0] state; + input [5:0] io_select; + + output reg [11:0] io_data_out; + output reg io_data_avail; + output reg io_interrupt; + output reg io_skip; + output reg io_clear_ac; + + + reg rx_int, tx_int; + reg [12:0] rx_data, tx_data; + reg tx_delaying; + reg [3:0] tx_delay; + + parameter F0 = 4'b0000; + parameter F1 = 4'b0001; + parameter F2 = 4'b0010; + parameter F3 = 4'b0011; + + parameter D0 = 4'b0100; + parameter D1 = 4'b0101; + parameter D2 = 4'b0110; + parameter D3 = 4'b0111; + + parameter E0 = 4'b1000; + parameter E1 = 4'b1001; + parameter E2 = 4'b1010; + parameter E3 = 4'b1011; + + + parameter PCA = 12'o4000; // photocell status + parameter DRE = 12'o2000; // data req enable + parameter WLS = 12'o1000; // write lock status + parameter EIE = 12'o0400; // error int enable + parameter PIE = 12'o0200; // photocell int enb + parameter CIE = 12'o0100; // done int enable + parameter MEX = 12'o0070; // memory extension + parameter DRL = 12'o0004; // data late error + parameter NXD = 12'o0002; // non-existent disk + parameter PER = 12'o0001; // parity error + + + always @(state) + begin + case (state) + F0: + begin + // sampled during f1 + io_skip <= 0; + io_data_avail <= 0; + io_clear_ac <= 0; + + if (iot) + case (io_select) + 6'o03: + if (mb[0]) + io_skip <= rx_int; + + 6'o04: + if (mb[0]) + begin + $display("tsf; tx_int %b, pc %o", tx_int, pc); + io_skip <= tx_int; + end + + 6'o60: // DCMA + if (mb[2:0] == 3'b001) + begin + DMA <= 0; + PEF < = 0; + DRL <= 0; + end + 6'o61: + case (mb[2:0]) +n 3'o1: // DCIM + begin + CIE <= 0; + EMA <= 0; + end + 3'o2: // DSAC +// xxx +assign ADC = DMA == DWA; + + begin + if (ADC) + begin + io_skip <= 1; + io_clear_ac <= 1; + end + end + 3'o5: // DIML + begin + CIE <= AC[8]; + EMA <= AC[7:0]; + end + 3'o6: // DIMA + begin + AC <= { PCA,DRE,WLS,EIE,PIE,CIE, MEX, DRL,NXD,PER }; + end + endcase // case(mb[2:0]) + + 6'o62: + case (mb[2:0]) + 3'o1: // DFSE + if (DRL | PER | WLS | NXD) + io_skip <= 1; + 3'o2: // ??? + if (DCF) + io_skip <= 1; + 3'o3: // DISK + if (DRL | PER | WLS | NXD | DCF) + io_skip <= 1; + endcase + endcase + end + + F1: + if (iot) + begin + $display("iot2 %t, state %b, mb %o, io_select %o", + $time, state, mb, io_select); + + case (io_select) + 6'o03: + begin + if (mb[1]) + rx_int <= 0; + if (mb[2]) + begin + io_data_out <= rx_data; + io_data_avail <= 1; + end + end + + 6'o04: + begin + if (mb[1]) + tx_int <= 0; + if (mb[2]) + begin + $display("tls; %o", ac); + tx_data <= ac; + tx_int <= 1; + tx_delaying <= 1; + tx_delay <= 4'b1111; + $display("set tx_int"); + end + end // case: 6'o04 + + 6'o60: + case (mb[2:0]) + 3'o03: // DMAR + begin + DMA <= AC; + io_clear_ac <= 0; + rf08_start_io <= 1; + rf08_rw <= 0; + end + + 3'o03: // DMAW + begin + DMA <= AC; + io_clear_ac <= 0; + rf08_start_io <= 1; + rf08_rw <= 1; + end + endcase // case(mb[2:0]) + + 6'o62: + case (mb[2:0]) + 6: // DMAC + begin +// io_clear_ac <= 1; + io_ac <= DMA; + end + endcase + + 6'o64: + case (mb[2:0]) + 1: // DCXA + EMA <= 0; + 3: // DXAL + begin + EMA <= AC; + io_clean_ac <= 1; + end + 5: // DXAC + begin + AC <= EMA; + end + endcase + + endcase + + end // if (iot) + + F2: + begin + if (io_interrupt) + $display("iot2 %t, reset io_interrupt", $time); + + // sampled during f0 + io_interrupt <= 0; + end + + F3: + begin + if (tx_delaying) + begin + tx_delay <= tx_delay - 1; + if (tx_delay == 4'b0) + begin + $display("iot2 %t, set io_interrupt", $time); + tx_delaying <= 0; + io_interrupt <= 1; + end + end + end + + + endcase // case(state) + end + +endmodule diff --git a/cpu/run.v b/cpu/run.v new file mode 100644 index 0000000..888599c --- /dev/null +++ b/cpu/run.v @@ -0,0 +1,68 @@ + +`include "pdp8.v" + +`timescale 1ns / 1ns + +module test; + + reg clk, reset_n; + reg[11:0] switches; + + pdp8 cpu(clk, reset_n, switches); + + initial + begin + $timeformat(-9, 0, "ns", 7); + + $dumpfile("pdp8.vcd"); + $dumpvars(0, test.cpu); + end + + initial + begin + clk = 0; + reset_n = 1; + + #1 begin + reset_n = 0; + end + + #100 begin + reset_n = 1; + end + +// #1500000 $finish; + #3000000 $finish; + end + + always + begin + #100 clk = 0; + #100 clk = 1; + end + + //---- + integer cycle; + + initial + cycle = 0; + + always @(posedge cpu.clk) + if (cpu.state == 4'b0000) + begin + cycle = cycle + 1; + #1 $display("cycle %d, r%b, pc %o, ir%o, ma %o, mb %o, jmp %b, l%b ac %o, i%b/%b", + cycle, cpu.run, cpu.pc, + cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac, + cpu.interrupt_enable, cpu.interrupt); + end + +// always @(posedge cpu.clk) +// begin +// #1 $display("state %b, runs %b, pc %o, ir %o, ma %o mb %o, jmp %b, l %b ac %o", +// cpu.state, cpu.run, cpu.pc, +// cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac); +// end + +endmodule +