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brad 2010-04-15 23:39:25 +00:00
parent 8be9d3cd42
commit c6008db64b
5 changed files with 103 additions and 87 deletions
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166
verif/fake_ide.v
View File

@ -1,83 +1,83 @@
module fake_ide(ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus);
input ide_dior;
input ide_diow;
input [1:0] ide_cs;
input [2:0] ide_da;
inout [15:0] ide_data_bus;
reg [7:0] data_out;
reg [7:0] cmd;
reg [7:0] status;
reg [7:0] drvhead;
integer fifo;
wire is_rd;
wire is_wr;
assign is_rd = ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
assign is_wr = ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
assign ide_data_bus = is_rd ? data_out : 12'bz;
initial
begin
status = 8'h50;
end
always @(*)
begin
if (ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
begin
if (ide_da != 0)
#1 $display("ide r cs %b; da %b; bus %x",
ide_cs, ide_da, ide_data_bus);
case (ide_da)
3'd0:
begin
if (fifo > 0)
begin
data_out = 0;
fifo = fifo - 1;
//$display("fifo %d", fifo);
end
if (fifo == 0)
begin
$display("ide empty!");
status = 8'h50;
cmd = 0;
end
end
3'd7:
data_out = status;
endcase
end
if (ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
begin
#1 $display("ide w cs %b; da %b; bus %x",
ide_cs, ide_da, ide_data_bus);
case (ide_da)
3'd6:
drvhead = ide_data_bus;
3'd7:
begin
//release ide_data_bus;
cmd = ide_data_bus;
#1 $display("ide cmd %x", cmd);
case (cmd)
8'h20:
begin
status = 8'h58;
fifo = 256;
end
endcase
end
endcase
end
end
endmodule
module fake_ide(ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus);
input ide_dior;
input ide_diow;
input [1:0] ide_cs;
input [2:0] ide_da;
inout [15:0] ide_data_bus;
reg [7:0] data_out;
reg [7:0] cmd;
reg [7:0] status;
reg [7:0] drvhead;
integer fifo;
wire is_rd;
wire is_wr;
assign is_rd = ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
assign is_wr = ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
assign ide_data_bus = is_rd ? data_out : 12'bz;
initial
begin
status = 8'h50;
end
always @(*)
begin
if (ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
begin
if (ide_da != 0)
#1 $display("ide r cs %b; da %b; bus %x",
ide_cs, ide_da, ide_data_bus);
case (ide_da)
3'd0:
begin
if (fifo > 0)
begin
data_out = 0;
fifo = fifo - 1;
//$display("fifo %d", fifo);
end
if (fifo == 0)
begin
$display("ide empty!");
status = 8'h50;
cmd = 0;
end
end
3'd7:
data_out = status;
endcase
end
if (ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
begin
#1 $display("ide w cs %b; da %b; bus %x",
ide_cs, ide_da, ide_data_bus);
case (ide_da)
3'd6:
drvhead = ide_data_bus;
3'd7:
begin
//release ide_data_bus;
cmd = ide_data_bus;
#1 $display("ide cmd %x", cmd);
case (cmd)
8'h20:
begin
status = 8'h58;
fifo = 256;
end
endcase
end
endcase
end
end
endmodule

2
verif/ram_s3board.v
View File

@ -110,7 +110,7 @@ module ram_s3board(ram_a, ram_oe_n, ram_we_n,
end
end
`ifdef debug_ram
`ifdef debug_s3ram
always @(ram_a or ram_oe_n or ram1_ce_n or ram_we_n or ram1_io)
begin
if (0)

7
verif/run.sh
View File

@ -1 +1,8 @@
cver +showpc +cycles=500000 +test=tss8_init.mem +pc=24200 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >xx
#cver +showpc +test=../tests/diags/MAINDEC-08-D5FA.mem +pc=0150 +switches=0000 +cycles=200000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >zz
#cver +showpc +test=../tests/diags/MAINDEC-08-D5EB.mem +pc=0200 +switches=4000 +cycles=50000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >zz
#grep "rf: go\!" xx
#cat xx | ../utils/ushow/ushow

5
verif/test_pdp8.v
View File

@ -5,6 +5,7 @@
`ifdef __CVER__
`define debug
`define sim_time
//`define debug_s3ram
`endif
//`define use_sim_ram_model
@ -240,8 +241,8 @@ module test;
n = $scan$plusargs("cycles=", arg);
if (n > 0)
begin
n = $sscanf(arg, "%o", max_cycles);
$display("arg %s cycles %o", arg, max_cycles);
n = $sscanf(arg, "%d", max_cycles);
$display("arg %s cycles %d", arg, max_cycles);
end
`endif

10
verif/test_tt.v
View File

@ -2,6 +2,8 @@
// testing top end for pdp8_tt.v
//
`define sim_time 1
`include "../verif/fake_uart.v"
`include "../rtl/brg.v"
`include "../rtl/pdp8_tt.v"
@ -23,6 +25,9 @@ module test_tt;
reg iot;
reg [3:0] state;
reg [11:0] mb_in;
reg uin;
wire uout;
pdp8_tt tt(.clk(clk),
.brgclk(brgclk),
@ -39,7 +44,9 @@ module test_tt;
.io_data_avail(io_data_avail),
.io_interrupt(io_interrupt),
.io_skip(io_skip));
.io_skip(io_skip),
.uart_in(uin),
.uart_out(uout));
reg [11:0] data;
reg sample_skip;
@ -52,6 +59,7 @@ module test_tt;
begin
@(posedge clk);
begin
uin = 0;
state = 4'h0;
mb_in = isn;
io_select = isn[8:3];